GB1216559A - Electronic binary multiplier - Google Patents

Abstract

1,216,559. Arithmetic circuitry. INTERNATIONAL BUSINESS MACHINES CORP. 20 June, 1968 [30 June, 1967], No. 29425/68. Heading G4A. An electronic binary multiplier comprises an array of multiplier cells, each adapted to generate a binary product signal from first and second binary input signals and each identified by a different two-digit co-ordinate (m, n), the same first binary input signal being applied in parallel to all cells with the same coordinate digit n, and the same second binary input signal being applied serially to all cells with the same co-ordinate digit m. Fig. 1 shows a binary multiplier comprising an array of cells 1 (large squares) each including flip-flops 2, 3, 4 having input gates (not shown) enabled by a common clock pulse train, and logic 5 which multiplies one bit of the multiplicand by a bit of the multiplier- and adds the result to a sum bit on a line 7 from the cell 1 in the next lower row and next left column (if any) and to a carry bit on a line 8 from the cell 1 in the same row and next left column (if any) to produce a sum bit and a carry bit on outgoing lines 7, 8 respectively. The multiplicand is applied in parallel at b0-b3 and is gated into the flip-flops 2 in the first column by a first clock pulse at which time the lowest order bit of the multiplier a0 is applied in parallel to the logic 5 of every cell 1 in the first column. The second clock pulse gates sum and carry bits on lines 7, 8 from the first column into flip-flops 4, 3 of the second column and at this time the second bit of the multiplier a1 is applied to the logic 5 of every cell of the second column, and so on. The bits of the product appear at P0-P7 in turn respectively. Since only one column is active at any time, a series of multiplications can be performed concurrently, a new one being started every clock pulse time. A second embodiment has 1, 1, 1, 2 extra cells at the right end of the first to fourth rows respectively and applies the bits of a third operand to the flip-flops 4 of the leftmost column and the lowest row (except in the rightmost cell), at the appropriate times, to evaluate AB + C where C is the third operand and A and B are a0-a3 and b0-b3 respectively. A third embodiment feeds the " third operand " inputs of the second embodiment from the outputs P0, P1 &c. In the cases of the outputs P0, P1, P2 this is done via shift registers of 3, 2, 1 stages respectively (assuming four rows of cells as in Fig. 1) to compensate for the relative delays between production of related signals at those outputs P0-P3 which feed the cells of the leftmost column. In this way a sum of products is obtainable, e.g. for multiplication of matrices.