GB1321026A - Data processing device - Google Patents

Abstract

1321026 Data processors CONTROLOGIC Inc 20 July 1971 [23 July 1970] 33941/71 Heading G4A A data processing unit, suitable for use as a piece part for constructing more complex data processors, comprises an assembly of registers 14 connected to an input bus 26 and an output bus 46; an arithmetic unit 22 having an input 42 connected to the registers 14 through the buses and an output 44 connected to the output bus, the processing unit having an external terminal 70 for connecting to the buses; a timing control 78 operable synchronously or asynchronously; and a control word decoder 76, the outputs of the timer and decoder being connected to the registers and arithmetic unit. A second terminal 68 supplies address information to the registers 14; a third terminal 88 supplies synchronizing signals to the timing control and a fourth terminal 94 supplies control information to the decoder 76. Each of the four terminals comprises a plurality of connections corresponding to the number of bits that the data processing unit can deal with in each case. In order to construct a larger processor the units can be combined in two ways. In Fig. 6A (not shown) the various bits of the data and address terminals 70, 68 are grouped together while those of the synchronizing and control terminals 88, 94 are linked together bit by bit; in this case the combined unit can deal with double length data words but normal length control words. In Fig. 6B (not shown) the bits of the data and address terminals are linked bit by bit and those of the sync. and control terminals are grouped together; now the combined unit can deal with double length control words but normal length data words. Further units can be combined in a similar way using any combination of these two basic ways. In the processing unit 10 the input bus 26 is connected to the terminal 70 and output bus 46 by inverters and/or amplifiers 72. Further internal input and output buses 28, 62 are connected by similar devices 74. The inputs to the arithmetic unit 22 contain registers 18, 20; register 18 receives data from internal bus 28 while register 20 receives data from both the input and output buses 26, 46. The arithmetic unit 22 comprises a full adder (Figs. 2, 2A, not shown) whose output can be shifted up or down one bit (Fig. 2C, not shown) and gates (Fig. 2B, not shown) for AND, OR, and EXCLUSIVE- OR decisions. The timing control 78 (Fig. 5, not shown) comprises a delay line oscillator and a shift register arranged to produce a four stage cycle of operations (Fig. 4B, not shown). In a complete installation (Fig. 7B) two processors 248, 250 each comprises one or more of the processing units. The first 248 performs the data computations while the second is programmed to perform the input/output functions; both have direct access to the main memory 260 of the computer and therefore work in parallel.