CN109194307B - Data processing method and system - Google Patents
Data processing method and system Download PDFInfo
- Publication number
- CN109194307B CN109194307B CN201810861079.5A CN201810861079A CN109194307B CN 109194307 B CN109194307 B CN 109194307B CN 201810861079 A CN201810861079 A CN 201810861079A CN 109194307 B CN109194307 B CN 109194307B
- Authority
- CN
- China
- Prior art keywords
- state
- prototype filter
- interpolation
- sampling
- divider
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Active
Links
Images
Classifications
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03H—IMPEDANCE NETWORKS, e.g. RESONANT CIRCUITS; RESONATORS
- H03H17/00—Networks using digital techniques
- H03H17/02—Frequency selective networks
- H03H17/06—Non-recursive filters
- H03H17/0621—Non-recursive filters with input-sampling frequency and output-delivery frequency which differ, e.g. extrapolation; Anti-aliasing
- H03H17/0635—Non-recursive filters with input-sampling frequency and output-delivery frequency which differ, e.g. extrapolation; Anti-aliasing characterized by the ratio between the input-sampling and output-delivery frequencies
- H03H17/065—Non-recursive filters with input-sampling frequency and output-delivery frequency which differ, e.g. extrapolation; Anti-aliasing characterized by the ratio between the input-sampling and output-delivery frequencies the ratio being integer
- H03H17/0657—Non-recursive filters with input-sampling frequency and output-delivery frequency which differ, e.g. extrapolation; Anti-aliasing characterized by the ratio between the input-sampling and output-delivery frequencies the ratio being integer where the output-delivery frequency is higher than the input sampling frequency, i.e. interpolation
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03H—IMPEDANCE NETWORKS, e.g. RESONANT CIRCUITS; RESONATORS
- H03H17/00—Networks using digital techniques
- H03H17/02—Frequency selective networks
- H03H17/0223—Computation saving measures; Accelerating measures
- H03H17/0225—Measures concerning the multipliers
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03H—IMPEDANCE NETWORKS, e.g. RESONANT CIRCUITS; RESONATORS
- H03H17/00—Networks using digital techniques
- H03H17/02—Frequency selective networks
- H03H17/0223—Computation saving measures; Accelerating measures
- H03H17/0227—Measures concerning the coefficients
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03H—IMPEDANCE NETWORKS, e.g. RESONANT CIRCUITS; RESONATORS
- H03H17/00—Networks using digital techniques
- H03H2017/0072—Theoretical filter design
- H03H2017/0081—Theoretical filter design of FIR filters
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03H—IMPEDANCE NETWORKS, e.g. RESONANT CIRCUITS; RESONATORS
- H03H17/00—Networks using digital techniques
- H03H17/02—Frequency selective networks
- H03H17/0223—Computation saving measures; Accelerating measures
- H03H2017/0245—Measures to reduce power consumption
Abstract
The embodiment of the invention provides a data processing method and a data processing system, which can adopt the same divider to carry out multiple operations under different working states in the resampling process of a sampling point, for example, in a first state, the divider is adopted to determine the sampling ratio of input and output frequencies, in a fourth state, the divider is adopted to determine target sampling data according to the accumulated sum of interpolation coefficients and the accumulated sum of products of the interpolation coefficients and original sampling data, and in the whole calculating process, the divider is multiplexed in different states. Furthermore, the invention can also time-division multiplex the multiplier in the third state to complete Lagrange interpolation calculation. The invention realizes the time-sharing multiplexing of the divider/multiplier, thereby obviously reducing the cost of the product and the power consumption of the chip and improving the competitiveness of the product.
Description
Technical Field
The present invention relates to the field of data processing technologies, and in particular, to a data processing method and system.
Background
With the wide application of digital audio and the popularization and popularization of various data interface technologies, audio signals can be transmitted to portable devices with the same data interface through external devices with various data interfaces, so that the portable devices with the same data interface can play the audio, for example, a device with a USB interface transmits audio to a portable audio device with a USB interface, a device with a bluetooth interface transmits audio to a portable audio device with a bluetooth interface, and the like.
Since the external device and the portable device are different devices, and the audio signals are transmitted in different two domains, it is necessary to perform asynchronous sampling on the audio signals from the external device to a sampling rate required by the playing before the audio signals can be played normally. The resampling is to transform the original sampling frequency into a new sampling frequency to meet the requirement of different sampling rates, and the commonly used algorithm is realized based on a low-pass filter plus extraction (or interpolation) structure, but a large amount of hardware resources are required in the realization process, and particularly, a plurality of groups of multipliers and dividers are required, for example, the dividers are required to be used in the calculation of the input-output sampling frequency ratio and the filter normalization; a large number of multipliers are used in the process of calculating the interpolation coefficient and FIR filtering, so that the area of a chip adopting the method is large, the hardware cost and the power consumption of the chip are greatly increased, and the product competitiveness is reduced.
Disclosure of Invention
The embodiment of the invention provides a data processing method and a data processing system, which reduce the area of a chip.
As a first aspect of the present invention, a data processing system is provided, which can perform multiple operations in different operating states by using a same divider during resampling of a sampling point, and the system may include: the device comprises a state controller, a divider, a first calculating unit, a second calculating unit and an initial position determining unit;
the state controller is used for controlling the system to enter different working states;
the system is in a first state, and the divider determines an input-output frequency sampling ratio;
the system is in a second state, the initial position determining unit determines the initial position of a prototype filter table and the initial position of original sampling data storage according to the input-output frequency sampling ratio;
in a third state of the system, the first computing unit determines an interpolation coefficient accumulated sum according to the initial position of the prototype filter table, and the second computing unit determines an accumulated sum of products of the interpolation coefficient and the original sample data according to the initial position of the original sample data;
and in a fourth state of the system, the divider determines target sampling data according to the accumulated sum of the interpolation coefficients and the accumulated sum of the products of the interpolation coefficients and the original sampling data.
Further, the first calculation unit may include one or more multipliers;
the multiplier is used for completing multiplication in a Lagrange interpolation algorithm in a time-sharing mode according to the prototype filter coefficient, the interpolation coefficient and the position difference among the prototype filter coefficients.
Preferably, the first calculating unit may include a first multiplier, a second multiplier and a fourth calculating unit;
the first calculating unit determines the position of the prototype filter coefficient in the prototype filter table according to the initial position of the prototype filter table, and continuously reads 4 adjacent prototype filter coefficients h 0-h 3 at the position; also determining the position difference of the interpolation coefficient and the prototype filter coefficient h0 according to the initial position of the prototype filter table;
the first multiplier and the second multiplier are used for completing multiplication operations in a deformed Lagrange interpolation algorithm in a time-sharing mode according to the position difference among the prototype filter coefficients h 0-h 3, the interpolation coefficient and the prototype filter coefficient h0 in 1-n-1 working clocks, and each multiplier completes a group of multiplication operations in each working clock period;
in the nth working clock, the fourth calculating unit adds the calculation results output by the first multiplier and the second multiplier in the (n-1) th working clock to obtain an interpolation coefficient.
Further, the first calculating unit may include a fifth calculating unit, configured to perform accumulation operation on the interpolation coefficients generated by the first calculating unit in sequence to obtain an accumulated sum of the interpolation coefficients.
Further, the second calculation unit may include a third multiplier;
and the third multiplier is used for calculating the accumulated sum of the products of the interpolation coefficients and the original sampling data in the (n + 1) th working clock.
Further, the method can also comprise the following steps: a third calculation unit;
the third calculating unit is used for determining a first clock number corresponding to a third specified number of input sampling periods and a second clock number corresponding to the third specified number of output sampling periods according to the input sampling clock and the output sampling clock;
the divider is used for dividing the first clock number and the second clock number to obtain the input-output frequency sampling ratio.
Further, when the state controller detects that a new sampling point arrives, the state controller outputs a second state control signal to the initial position determining unit to trigger the system to enter a second state;
after the second state is finished, the state controller outputs a third state control signal to the first computing unit to trigger the system to enter a third state;
after the third state is finished, the state controller outputs a fourth state control signal to the divider to trigger the system to enter a fourth state;
and after the fourth state is finished, the state controller outputs a first state control signal to the divider to trigger the system to enter the first state.
Preferably, the state controller can keep the system in an idle state or enter into a working state under the control of the enabling signal;
when the state controller detects that the enable signal is effective, the state controller outputs a first state control signal to the divider to trigger the system to enter a first state;
when the state controller detects that the enable signal is invalid, the state controller controls the system to enter an idle state.
In another aspect of the present invention, a data processing method is provided, wherein in a resampling process of a sampling point, a same divider is controlled to perform multiple operations in different working states; wherein the content of the first and second substances,
in a first state, determining an input-output frequency sampling ratio by using the divider;
in a second state, determining the initial position of a prototype filter table and the initial position of original sampling data storage according to the input-output frequency sampling ratio;
in a third state, determining an interpolation coefficient accumulated sum according to the initial position of the prototype filter table, and determining an accumulated sum of products of the interpolation coefficient and the original sampling data according to the initial position of the original sampling data storage;
and in a fourth state, determining target sampling data by adopting the divider according to the interpolation coefficient accumulated sum and the accumulated sum of the products of the interpolation coefficients and the original sampling data.
Further, in the third state, one or more multipliers may be used to perform multiplication in the lagrange interpolation algorithm in a time-sharing manner according to the prototype filter coefficients in the prototype filter table, the interpolation coefficients, and the position difference between the prototype filter coefficients.
The data processing system and the method provided by the embodiment of the invention can adopt the same divider to carry out multiple operations under different working states in the resampling process of a sampling point, for example, in a first state, the divider is adopted to determine the sampling ratio of input and output frequencies, in a fourth state, the divider is adopted to determine target sampling data according to the accumulated sum of interpolation coefficients and the accumulated sum of products of the interpolation coefficients and original sampling data, and in the whole calculation process, the divider is multiplexed in different states.
Furthermore, the invention can also time-division multiplex the multiplier in the third state to complete the Lagrange interpolation calculation.
The invention realizes the time-sharing multiplexing of the divider/multiplier, reduces the quantity of hardware, obviously reduces the area of a chip, and solves the problems that a large quantity of multipliers, dividers and other hardware are used for calculating the sampling frequency in a conventional mode in the prior art, the area of the chip is large, and the integration into a corresponding circuit is not facilitated, thereby obviously reducing the cost and the power consumption of the chip and improving the competitiveness of the product.
Drawings
The accompanying drawings, which are included to provide a further understanding of the invention and are incorporated in and constitute a part of this specification, illustrate embodiments of the invention and together with the description serve to explain the invention and not to limit the invention. In the drawings:
FIG. 1 is a diagram of operational clock and data waveforms in a data processing system according to an embodiment of the present invention;
FIG. 2 is a state flow diagram of a data processing system according to an embodiment of the present invention;
FIG. 3 is a block diagram of a data processing system according to an embodiment of the present invention;
FIG. 4 is a graph of Lagrangian interpolation coefficients in an embodiment of the present invention;
fig. 5 is a flowchart of a data processing method according to an embodiment of the present invention.
Detailed Description
In order to make the technical solutions and advantages of the embodiments of the present invention more apparent, the following further detailed description of the exemplary embodiments of the present invention is provided with reference to the accompanying drawings, and it is obvious that the described embodiments are only a part of the embodiments of the present invention, and are not exhaustive of all the embodiments. It should be noted that the embodiments and features of the embodiments may be combined with each other without conflict.
The data processing system in the embodiment of the invention can be applied to a portable device containing a processing chip and a memory.
In processing audio data, the audio data is usually resampled to meet the requirements of different frequencies. Resampling, i.e. transforming the original frequency to a new frequency to adapt to the requirements of different frequencies. In the resampling calculation, a filter algorithm, interpolation calculation, and the like are used, and a divider and a multiplier are mainly used in terms of hardware. In the conventional design, one divider is needed for carrying out one division operation, and a plurality of dividers are needed for carrying out a plurality of division operations; similarly, one multiplier needs to be used for one multiplication, and a plurality of multipliers need to be used for a plurality of multiplications. The more dividers and multipliers are used, the higher the hardware cost and the larger the chip area.
The inventor finds that, because the hardware for performing frequency processing has a fixed operating clock frequency, the frequency of the operating clock is often greater than that of the original sampling data during resampling, and meanwhile, the frequency of the operating clock is often greater than that of the resampling target data. Based on the above findings, the inventor believes that the difference between the working clock and the original sampling data and the difference between the working clock and the target data frequency can be utilized to control the same divider or multiplier to perform multiple operations under different states in the resampling process of one sampling point. In short, in a resampling process, a divider or a multiplier is subjected to time division multiplexing; so as to reduce the number of hardware, reduce the production cost and reduce the chip area.
FIG. 1 is a diagram of operating clock and data waveforms in a data processing system in accordance with a preferred embodiment of the present invention, wherein mclk is the operating clock; clkin is the input sampling clock (the sampling clock of the original sampled data); audio _ l _ in is left channel input data, audio _ r _ in is right channel input data, and both audio _ l _ in and audio _ r _ in are 24-bit data; clkout is the output sampling clock (the sampling clock for the target sample data); audio _ l _ out is left channel output data, audio _ r _ out is right channel output data, and both audio _ l _ out and audio _ r _ out are 24-bit data; reset _ en is an enable signal.
As shown in fig. 1, in the embodiment of the present invention, clkin and clkout are asynchronous, and original sample data corresponding to clkin needs to be processed to obtain target sample data corresponding to clkout. In a specific implementation, when the input audio has left and right channels, i.e., left channel input data and right channel input data as shown in fig. 1, the original sampling data (original audio data) may be divided into left and right channels to be processed respectively, so as to obtain target sampling data (target audio data) having left channel output data and right channel output data respectively, thereby playing the audio according to different channels. Although the embodiment of the present invention is exemplified by binaural audio data processing, it should be understood by those skilled in the art that the core ideas and methods of the present invention can also be applied to a mono audio data processing process.
FIG. 2 is a state flow diagram of a data processing system in accordance with a preferred embodiment of the present invention; as shown in fig. 2, in the embodiment of the present invention, the state controller enables the system to enter different operating states by sending the state control signal. When the state controller sends out the first state control signal, triggering the system to enter a first state S1; when the state controller detects that a new sampling point arrives (in this embodiment, the rising edge of the output sampling clock arrives), a second state control signal is output, and the system is triggered to enter a second state S2; after the second state S2 lasts for the first designated number of working clock cycles, the state controller outputs a third state control signal to trigger the system to enter a third state S3; when S3 is finished, the state controller outputs a fourth state control signal to trigger the system to enter a fourth state S4. The state transition of one time S1 → S2 → S3 → S4 corresponds to the resampling process of one sample point.
For one embodiment, the state controller may initially enter the first state S1 after the system is powered on;
as another embodiment, the state controller keeps the system in the idle state S0 or enters the working state under the control of the external enable signal reset _ en. For example, when the enable signal reset _ en is inactive (e.g., low), the state controller sleeps or issues an idle signal, the system is in an idle state S0, and the system does not operate. When the enable signal reset _ en is asserted (e.g., goes from low to high), the state controller issues the first state control signal, thereby triggering the system to enter the operating state from S1 to S4.
Fig. 3 is a schematic structural diagram of a data processing system according to an embodiment of the present invention. As shown in fig. 3, a data processing system provided in an embodiment of the present invention includes: the device comprises a state controller, a divider, a first calculating unit, a second calculating unit and an initial position determining unit.
The working principle of the embodiment shown in fig. 3 will be described below with reference to fig. 1 and 2.
[ first State ]
The state controller outputs a first state control signal to the divider, triggering the system to enter state S1. In the first state S1, the divider operates to determine the input-to-output frequency sampling ratio.
Preferably, the system may further comprise a third computing unit. Before the divider performs operation and determines the input-output frequency sampling ratio, a third computing unit may determine, according to the working clock mclk and the input sampling clock clkin, a first clock number corresponding to a third specified number of input sampling periods, and determine, according to the working clock mclk and the output sampling clock clkout, a second clock number corresponding to a third specified number of output sampling periods. Then, the divider may divide the first clock number by the second clock number to obtain the input-output frequency sampling ratio.
The first clock number may be the number of working clock cycles corresponding to the third specified number of input sampling cycles, for example, the number of working clock cycles corresponding to 1024 input sampling cycles is counted by the working clock mclk. The second clock number may be the number of working clock cycles corresponding to the third specified number of output sampling cycles, for example, the number of working clock cycles corresponding to 1024 output sampling cycles is counted by the working clock mclk.
In specific implementation, a person skilled in the art may set the third designated number by himself or herself in consideration of data accuracy, chip performance, and chip area.
The divider divides the first clock number and the second clock number to obtain an input-output frequency sampling ratio according to the following formula:
input/output frequency sampling ratio is first clock number/second clock number fout/fin
Where fin represents the original sampled data frequency and fout represents the target sampled data frequency.
In a preferred embodiment, the input/output frequency sampling ratio calculated by the divider may be output to the ratio detection unit for processing, and the ratio detection unit obtains the input/output frequency sampling ratio that needs to be up-converted or down-converted for the input sample. In order to further eliminate the jitter of the input and output sampling clocks, moving average filtering can be performed on the input and output frequency sampling ratio obtained by the proportion detection unit to obtain an optimized input and output frequency sampling ratio.
[ second State ]
When the state controller detects the rising edge of the output sampling clock clkout, it outputs a second state control signal to the initial position determining unit, triggering the system to enter a second state S2.
In the second state S2, the initial position determination unit determines the initial position of the prototype filter table and the initial position of the original sample data storage for the current filtering based on the input-output frequency sampling ratio.
As is well known, the prototype filter table is a coefficient table stored in advance in a memory. Wherein the coefficients are taken from the prototype filter table as initial position values of the prototype filter table for lagrangian coefficient interpolation calculation. And the initial position of the original sampling data storage is used for filtering when FIR filtering is performed, the original sampling data is extracted from the storage for filtering.
In specific implementation, a prototype filter table in the prior art may be used, or a prototype filter table may be implemented by using a filter design and analysis tool of MATLAB in the embodiment of the present invention. Taking an example of a low-pass equal-ripple filter (equal-ripple filter) consisting of 32 phases, each of 32-order, and 1024-order in total, the prototype filter coefficients generation parameters are shown in the following table.
Prototype filter coefficient generation parameter table:
since the filter coefficients are symmetric, the generated prototype filter coefficients can be stored using a read only memory size of 1024X24b (24 bits wide in coefficient bits) as long as half of the coefficients are stored.
In the embodiment of the present invention, the initial position of the prototype filter table and the initial position of the original sample data storage may be determined by using the prior art, which is not limited in the present invention.
Since the time required to determine the initial position of the prototype filter table and the initial position of the raw sample data store may be predetermined, the duration of S2 may also be predetermined, and in one particular implementation, the duration of the second state is a first specified number of operational clock cycles. Specifically, the first specified number may be 9. In one embodiment, a counter may be set to count the cycles of the operating clock mclk, and the second state may end when a first specified number of operating clock cycles has been counted. For example, when the first designated number is 9, the state delay counter state _ count is counted from 0, and when the state _ count is CNT2(CNT2 value is set to 8), the second state ends. And when the second state is finished, the state delay counter is cleared.
[ third State ]
After the second state is finished, the state controller outputs a third state control signal to the first computing unit, and triggers the system to enter a third state S3.
In the third state, the first calculating unit determines the accumulated sum of the interpolation coefficients of the current filtering according to the initial position of the prototype filter table, and the second calculating unit determines the accumulated sum of the products of the interpolation coefficients of the current filtering and the original sampling data according to the initial position stored by the original sampling data.
As a specific embodiment, the first calculation unit may include one or more multipliers; the multiplier is used for completing multiplication in a Lagrange interpolation algorithm in a time-sharing mode according to the prototype filter coefficient, the interpolation coefficient and the position difference among the prototype filter coefficients.
As a preferred embodiment, the first calculating unit may include a first multiplier, a second multiplier and a fourth calculating unit;
the first calculating unit determines the position of the prototype filter coefficient in the prototype filter table according to the initial position of the prototype filter table, and continuously reads 4 adjacent prototype filter coefficients h 0-h 3 at the position; also determining the position difference of the interpolation coefficient and the prototype filter coefficient h0 according to the initial position of the prototype filter table;
the first multiplier and the second multiplier are used for completing multiplication operations in a deformed Lagrange interpolation algorithm in a time-sharing mode according to the position difference among the prototype filter coefficients h 0-h 3, the interpolation coefficient and the prototype filter coefficient h0 in 1-n-1 working clocks, and each multiplier completes a group of multiplication operations in each working clock period;
in the nth working clock, the fourth calculating unit adds the calculation results output by the first multiplier and the second multiplier in the (n-1) th working clock to obtain an interpolation coefficient.
The second calculation unit may include a third multiplier for calculating an accumulated sum of products of the interpolation coefficients and the original sample data in the (n + 1) th operation clock.
The first calculating unit further comprises a fifth calculating unit, which is used for sequentially carrying out accumulation operation on the interpolation coefficients generated by the first calculating unit to obtain the accumulated sum of the interpolation coefficients.
The first calculating unit firstly obtains the position of the coefficient of the prototype filter in the prototype filter table, and continuously takes 4 coefficients at the position for interpolation filtering calculation. The interpolation filtering calculation can be realized by adopting a Lagrange interpolation algorithm. Fig. 4 is a graph of lagrangian interpolation coefficients according to an embodiment of the present invention, in which coefficients h 0-h 3 are 4 adjacent prototype filter coefficients continuously extracted from the prototype filter table.
The positions of the prototype filter coefficients in the prototype filter table are calculated using the following equation:
pos＝pos+step
where step represents a conversion factor, i.e. a step size, which indicates that the ratio of the proportional detection output is shifted left by k bits (k equals to 6), and the size of k determines the step size, i.e. determines the filtering order, and finally determines the calculation accuracy of the filter. pos represents the current coefficient position.
The initial position value of the prototype filter table obtained in the state of S2 is given pos and then calculated when the calculation is initial, that is, the current coefficient position pos is always determined by the last group of coefficient positions pos and the conversion factor step. Wherein pos is 36 bits in the present invention, and the upper 14 bits (pos [35:22]) is an integer part, i.e. the current coefficient position in the prototype filter table, and the prototype filter table is queried by this current coefficient position to obtain a current set of consecutive prototype filter coefficients h 0-h 3 for interpolation. The lower 22 bits (pos [21:0]) are a fractional part representing the position difference between the interpolation coefficient and h0, i.e., the D value in fig. 4. When calculating a new target sampling point, the pos value needs to be calculated after being reinitialized by the initial position value of the prototype filter table calculated by the state of S2.
The first multiplier and the second multiplier complete multiplication operation in the Lagrange interpolation algorithm in a time-sharing mode according to prototype filter coefficients h 0-h 3, the position difference D between the interpolation coefficient and h0 and the Lagrange interpolation algorithm.
Taking the commonly used third-order lagrange interpolation algorithm in the prior art as an example, the commonly used calculation formula of the third-order lagrange interpolation algorithm is as follows:
coef＝[–(D–1)*(D–2)*(D–3)/6]*h0
+[D*(D–2)*(D–3)/2]*h1
+[–D*(D–1)*(D–3)/2]*h2
+[D*(D–1)*(D–2)/6]*h3
where coef denotes an interpolation coefficient, and D denotes a position difference between the interpolation coefficient and h 0.
The above equation includes 12 multiplication operations, so the prior art needs up to 12 multipliers to realize the operations. The inventor finds that the above expression can be regarded as summation of 4 groups of addends, and each group of addends is the product of multiplication of 4 groups of multipliers, so in order to reduce the number of multipliers and achieve the purpose of time-sharing multiplexing multipliers, as a specific embodiment, 4 multipliers can be adopted, each multiplier performs 3 times of multiplication operation in a time-sharing manner to obtain a group of addends, and finally, the final output results of the 4 multipliers are added to obtain the coef value.
As a more preferred implementation, the embodiment of the present invention performs a deformation process on the lagrangian interpolation calculation formula, so that when the system calculates according to the deformed formula, the product can be obtained by multiplying with as few multipliers as possible, and each multiplier input to a multiplier may be a sum of several sets of addends or a product of several sets of multipliers. Therefore, when the multipliers are configured, the number of the multipliers is selected according to the number of addends and the product of multiplication, and the time division multiplexing process of each multiplier is determined.
Therefore, the inventors have grouped and extracted the formula transformation of the above formula with h0 and h1 as a group and h2 and h3 as a group respectively to obtain the following formula:
coef＝(D–2)*(D–3)/2*[-(D-1)*h0/3+D*h1]+D*(D-1)/2*[-(D-3)*h2+(D-2)*h3/3]
the modified lagrangian interpolation formula includes 2 sets of 8 multiplication operations. The multipliers before and after each multiplication number are respectively used as the input of the multiplier according to the multiplication number, and the multiplication operation is completed in one working clock period by one multiplier before and after the multiplication number. Thus, 2 multipliers can be selected, and each multiplier completes 4 multiplication operations in a time sharing mode. Therefore, the traditional Lagrange algorithm is deformed to reduce the times of multiplication, the multipliers are used as few as possible, the multiplication is completed in a time-sharing mode, the number of the multipliers can be greatly reduced, and the utilization rate of each multiplier is improved.
Obviously, the design idea and method of the present invention are not only applicable to the third-order lagrangian algorithm in the present embodiment, but also applicable to the calculation situation of other lagrangian algorithms.
In one particular implementation, n may be greater than or equal to 5. For the purpose of clearly describing the core idea of the present invention, n-5 is taken as an example in the following. At this time, Cycle0 to Cycle4 represent n as 5 duty cycles.
In cycles 0-3, the first multiplier and the second multiplier complete multiplication in a lagrange interpolation algorithm in a time-sharing manner according to the prototype filter coefficients h 0-h 3, the interpolation coefficient and the position difference D between the prototype filter coefficients h0, and the calculation process can be shown in the following table. Where inputs a and b represent the two inputs (two multipliers) of the multiplier, respectively.
First multiplier
Second multiplier
At Cycle4, the fourth calculation unit adds the calculation outputs of the two multipliers at Cycle3 to obtain an interpolation coefficient coef: (D-2) (D-3)/2 [ - (D-1) × h0/3+ D × h1] + D [ - (D-3) × h2+ (D-2) × h3/3 ].
And sequentially and circularly calculating, namely calculating the number of interpolation coefficients from the current initial position to the end of the coefficient table, and representing the number of orders of filtering according to the actual calculation.
In the specific implementation, the multiplier may be utilized in consideration of the maximum time efficiency according to the preparation condition of the multiplier, and the multiplier may be configured for the input a and the input b of the multiplier in each Cycle, which is not limited to the above listed situation. For example, if the D value and h0, h1 values are ready at the time of Cycle0, the multiplication calculations performed by the first multiplier or the second multiplier listed in the above table at Cycle0 and Cycle1 may be interchanged.
After the interpolation coefficient coef is generated, the fifth calculation unit accumulates the interpolation coefficients to obtain an interpolation coefficient accumulated sum. The cumulative formula is as follows:
where coef _ accum is the accumulated value of the interpolation coefficients, and coef (i) is the ith interpolation coefficient value.
After the interpolation coefficient coef is generated, the third multiplier is used to calculate the cumulative sum of the products of the interpolation coefficient and the original sampling data in the (n + 1) th working clock (Cycle5 when n is 5).
The calculation formula is as follows:
samp _ accum is the value of the interpolation coefficient multiplied by the input sample data, coef (i) is the value of the ith interpolation coefficient, and sample (i) is the ith input sample data (when the two-channel audio data is processed, 24-bit left channel or 24-bit right channel data).
The original sample data may be read in the memory according to the initial position of the sample data storage obtained in S2; the original sampling data is stored in the SRAM, and the data is read and written by the address controller. In the invention, 128X48b is used, and the audio data is 24-bit double-channel with the depth of 128.
In the embodiment of the invention, the reading of the original sampling data and the calculation of the interpolation coefficient are two parallel processes, and mutual interference does not occur.
In particular, the calculation process of the third multiplier can be as shown in the following table. Where input a and input b represent the two inputs (two multipliers) of the third multiplier, respectively.
Third multiplier
| Clock | Cycle5 | Cycle10 | Cycle11 |
| Input a | coef(0) | coef(1) | coef(2) |
| Input b | sample(0) | sample(1) | sample(2) |
| Output of | coef(0)*sample(0) | coef(1)*sample(1) | coef(2)*sample(2) |
The cumulative results are as follows:
since the interpolation coefficient in this embodiment needs 5 cycles to complete the calculation, the interpolation coefficient and the input original sample data may be taken at the time of calculating the first Cycle (Cycle5, Cycle10 …) of the next interpolation coefficient each time, and the multiply-accumulate processing may be performed.
It will be appreciated that each time the calculated interpolation coefficient will remain in the next 5 cycles, it is modified to a new interpolation coefficient when it is calculated. The accumulated sum is thus calculated at the next interpolation coefficient calculation, i.e. at cycle0 for the next 5 cycles. The two things of calculating interpolation coefficient and accumulated value are paralleled.
The above cycles are all working clocks. In the two-channel audio data processing, the left and right channel calculation methods are the same, namely samp _ accum _ l and samp _ accum _ r are calculated respectively.
It should be noted that, in the embodiment of the present invention, there are many coefficients in the prototype filter table, and how many coefficients represent how many orders of filtering from the current initial position to the end of the coefficient table, based on actual calculation. For example, 10 interpolation coefficients are finally calculated (each calculated by different sets of values h 0-h 3 and D), which is 10 orders, and 10 data are taken from the sample data memory and multiplied by the 10 interpolation coefficients.
From the above, in a preferred embodiment of the present invention, only 3 multipliers are used to complete the whole operation process, thereby significantly reducing the hardware cost.
[ fourth State ]
After the third state is finished, the state controller outputs a fourth state control signal to the divider, and triggers the system to enter a fourth state S4.
In the fourth state, the divider determines the target sample data according to the interpolation coefficient cumulative sum and the cumulative sum of the products of the interpolation coefficients and the original sample data. The duration of the fourth state is a second specified number of duty clock cycles. In particular, the second specified number may be 78.
Due to different input-output sampling ratios, the number of the calculated interpolation coefficients is different, namely the number of the interpolation coefficients is different, and normalization processing can be performed.
As a preferred embodiment, the divider may be multiplexed to perform normalization calculation to output target sample data. The normalized calculation formula is:
filter_out＝samp_accum/coef_accum；
wherein, filter _ out is the target sampling data, samp _ accum is the sum of interpolation coefficient and original sampling data (samp _ accum _ l or samp _ accum _ r in case of dual channel), coef _ accum is the sum of interpolation coefficient.
When the state controller counts the duration of the fourth state, a first state control signal is sent out to enable the system to enter a first state S1, so that when the system waits for a new sampling point to arrive (the rising edge of the output sampling clock arrives), the system enters S2 to start the resampling calculation of the new sampling point, and the steps are sequentially circulated according to the sequence.
As a preferred embodiment, when the state controller detects that the falling edge of the enable signal, reset _ en, arrives, the state controller may control the system to enter the idle state S0.
The data processing system provided by the embodiment of the invention outputs a first state signal through the state controller, triggers the system to enter a first state, in the state, the divider determines the sampling ratio of the input and output frequencies, then, on the rising edge of the output sampling clock, the state controller outputs a second state control signal, triggers the system to enter a second state, in the second state, the initial position determining unit determines the initial position of the prototype filter table and the initial position of the original sampling data storage according to the sampling ratio of the input and output frequencies, then, after the second state is finished, the state controller outputs a third state control signal, triggers the system to enter a third state, in the third state, the first calculating unit adopts two multipliers for time division multiplexing to determine the interpolation coefficient accumulation sum according to the initial position of the prototype filter table, and the second calculating unit adopts one multiplier, determining the cumulative sum of the products of the interpolation coefficients and the original sample data according to the initial position of the original sample data storage; finally, after the third state is finished, the state controller outputs a fourth state control signal to trigger the system to enter the fourth state, in the fourth state, the divider determines target sampling data according to the interpolation coefficient accumulation sum and the accumulation sum of the product of the interpolation coefficient and the original sampling data, so that the resampling calculation of one sampling point is finished, and in the whole calculation process, the multiplier and the divider are multiplexed in different states, so that the number of hardware is reduced, the area of a chip is reduced, the production cost is obviously reduced, and the problems that a large number of multipliers, dividers and other hardware are used for calculating the sampling frequency by using a conventional mode in the prior art, the area of the chip is large, and the cost is very high are solved.
Fig. 5 is a flowchart of a data processing method according to an embodiment of the present invention, and as shown in fig. 5, the embodiment of the present invention provides a data processing method, in a resampling process of a sampling point, a same divider is controlled to perform multiple operations in different working states; the method can comprise the following steps:
101. in a first state, determining an input-output frequency sampling ratio by using the divider;
in this operating state, as a preferred embodiment, first, the first clock number corresponding to the third specified number of input sampling cycles is determined according to the operating clock mclk and the input sampling clock clkin shown in fig. 2, and the second clock number corresponding to the third specified number of output sampling cycles is determined according to the operating clock mclk and the output sampling clock clkout. Then, the divider may divide the first clock number by the second clock number to obtain the input-output frequency sampling ratio.
The first clock number may be the number of working clock cycles corresponding to the third specified number of input sampling cycles, for example, the number of working clock cycles corresponding to 1024 input sampling cycles is counted by the working clock mclk. The second clock number may be the number of working clock cycles corresponding to the third specified number of output sampling cycles, for example, the number of working clock cycles corresponding to 1024 output sampling cycles is counted by the working clock mclk.
In specific implementation, a person skilled in the art may set the third designated number by himself or herself in consideration of data accuracy, chip performance, and chip area.
The divider divides the first clock number and the second clock number to obtain an input-output frequency sampling ratio according to the following formula:
input/output frequency sampling ratio is first clock number/second clock number fout/fin
Where fin represents the original sampled data frequency and fout represents the target sampled data frequency.
In a preferred embodiment, the input/output frequency sampling ratio calculated by the divider may be subjected to a ratio detection process to obtain an input/output frequency sampling ratio that requires up-conversion or down-conversion of the input sample. In order to further eliminate the jitter of the input and output sampling clocks, moving average filtering can be performed on the input and output frequency sampling ratio obtained after the proportional detection processing, so as to obtain the optimized input and output frequency sampling ratio.
102. In a second state, determining the initial position of a prototype filter table and the initial position of original sampling data storage according to the input-output frequency sampling ratio;
in a preferred embodiment, the first state is switched to the second state when the arrival of a new sampling point is detected. In the second state, the initial position of the prototype filter table and the initial position of the original sample data storage are determined according to the input-output frequency sampling ratio.
In an embodiment of the present invention, the duration of the second state is a first specified number of working clock cycles. Specifically, the first specified number may be 9.
103. In a third state, determining an interpolation coefficient accumulated sum according to the initial position of the prototype filter table, and determining an accumulated sum of products of the interpolation coefficient and the original sampling data according to the initial position of the original sampling data storage;
and after the second state is finished, entering a third state. In a third state, an accumulated sum of interpolation coefficients is determined based on the initial position of the prototype filter table, and an accumulated sum of products of interpolation coefficients and the original sample data is determined based on the initial position of the original sample data store.
And in a third state, one or more multipliers are adopted to complete multiplication operation in the Lagrange interpolation algorithm in a time-sharing manner according to the prototype filter coefficients in the prototype filter table, the interpolation coefficients and the position difference among the prototype filter coefficients.
As a preferred implementation, the lagrangian interpolation algorithm formula commonly used in the art can be modified according to the principle that the number of multiplication operations in the algorithm is reduced as much as possible and the multiplication operations are completed in a time-sharing manner by using as few multipliers as possible. And selecting the number of multipliers according to the number of addends and the product of multiplication contained in the deformed Lagrange algorithm formula, and determining the time division multiplexing process of each multiplier.
As a specific embodiment, when a common third-order lagrangian interpolation algorithm is used, two multipliers may be used to perform multiplication in the modified lagrangian interpolation algorithm formula in a time-sharing manner. Wherein the content of the first and second substances,
firstly, determining the position of a prototype filter coefficient in a prototype filter table according to the initial position of the prototype filter table, and continuously reading 4 adjacent prototype filter coefficients h 0-h 3 at the position; determining the position difference D of the interpolation coefficient and the prototype filter coefficient h0 according to the initial position of the prototype filter table;
secondly, in the 1 st to n-1 th working clocks in the present state, two multipliers are adopted to complete the multiplication operation in the deformed Lagrange interpolation algorithm in a time-sharing manner according to the position difference among the prototype filter coefficients h0 to h3, the interpolation coefficient and the prototype filter coefficient h0, and each multiplier completes a group of multiplication operation in each working clock period;
and then, in the nth working clock, adding the calculation results output by the first multiplier and the second multiplier in the (n-1) th working clock respectively to obtain an interpolation coefficient.
Then, a third multiplier is used to calculate the cumulative sum of the products of the interpolation coefficients and the original sample data in the (n + 1) th working clock cycle.
And after the interpolation coefficient is generated, the interpolation coefficients are sequentially subjected to accumulation operation to obtain the accumulation sum of the interpolation coefficients.
104. And in a fourth state, determining target sampling data by adopting the divider according to the interpolation coefficient accumulated sum and the accumulated sum of the products of the interpolation coefficients and the original sampling data.
As a preferred embodiment, the duration of the fourth state is a second specified number of cycles of the working clock. Specifically, the divider divides the accumulated sum of the product of the interpolation coefficient and the original sampling data by the accumulated sum of the interpolation coefficient to obtain the target sampling data.
105. And after the fourth state is finished, returning to the step 101, or entering an idle state.
As a specific implementation manner, the first state S1 may be entered after the system is powered on, and after the fourth state is ended, the process returns to step 101 to enter the first state;
as another embodiment, there may be an idle state. That is, when it is detected that the enable signal is invalid, the idle state is entered. When the enable signal is active, return to step 101 to enter the first state.
In the initial state of the data processing method, whether an enable signal is valid is detected, and if the enable signal is valid, the step 101 is executed; in the execution process of steps 101-105, whether the enable signal is invalid or not can be detected at any time, once the enable signal is invalid, the execution of the current step is stopped, and the current step enters an idle state.
For other specific execution processes of the data processing method provided by the embodiment of the present invention, reference may be made to the content of the foregoing data processing system, which is not described herein again.
In the data processing method provided by the embodiment of the invention, a divider is adopted to determine an input-output frequency sampling ratio in a first state, an initial position of a prototype filter table and an initial position of original sampling data storage are determined according to the input-output frequency sampling ratio in a second state, an interpolation coefficient accumulated sum is determined according to the initial position of the prototype filter table in a third state, and the accumulated sum of products of the interpolation coefficient and the original sampling data is determined according to the initial position of the original sampling data storage; the method comprises the steps of using one or more multipliers to complete multiplication operation in a Lagrange interpolation algorithm in a time-sharing mode according to position differences among prototype filter coefficients, interpolation coefficients and the prototype filter coefficients in a prototype filter table, multiplexing the dividers in a fourth state, determining target sampling data according to interpolation coefficient accumulation sums and accumulation sums of products of the interpolation coefficients and original sampling data, and completing resampling calculation of a sampling point.
As will be appreciated by one skilled in the art, embodiments of the present invention may be provided as a method, system, or computer program product. Accordingly, the present invention may take the form of an entirely hardware embodiment, an entirely software embodiment or an embodiment combining software and hardware aspects. Furthermore, the present invention may take the form of a computer program product embodied on one or more computer-usable storage media (including, but not limited to, disk storage, CD-ROM, optical storage, and the like) having computer-usable program code embodied therein.
The present invention is described with reference to flowchart illustrations and/or block diagrams of methods, apparatus (systems), and computer program products according to embodiments of the invention. It will be understood that each flow and/or block of the flow diagrams and/or block diagrams, and combinations of flows and/or blocks in the flow diagrams and/or block diagrams, can be implemented by computer program instructions. These computer program instructions may be provided to a processor of a general purpose computer, special purpose computer, embedded processor, or other programmable data processing apparatus to produce a machine, such that the instructions, which execute via the processor of the computer or other programmable data processing apparatus, create means for implementing the functions specified in the flowchart flow or flows and/or block diagram block or blocks.
These computer program instructions may also be stored in a computer-readable memory that can direct a computer or other programmable data processing apparatus to function in a particular manner, such that the instructions stored in the computer-readable memory produce an article of manufacture including instruction means which implement the function specified in the flowchart flow or flows and/or block diagram block or blocks.
These computer program instructions may also be loaded onto a computer or other programmable data processing apparatus to cause a series of operational steps to be performed on the computer or other programmable apparatus to produce a computer implemented process such that the instructions which execute on the computer or other programmable apparatus provide steps for implementing the functions specified in the flowchart flow or flows and/or block diagram block or blocks.
While preferred embodiments of the present invention have been described, additional variations and modifications in those embodiments may occur to those skilled in the art once they learn of the basic inventive concepts. Therefore, it is intended that the appended claims be interpreted as including preferred embodiments and all such alterations and modifications as fall within the scope of the invention.
It will be apparent to those skilled in the art that various changes and modifications may be made in the present invention without departing from the spirit and scope of the invention. Thus, if such modifications and variations of the present invention fall within the scope of the claims of the present invention and their equivalents, the present invention is also intended to include such modifications and variations.
Claims (10)
1. A data processing system is characterized in that in the resampling process of a sampling point, the same divider is adopted to carry out multiple operations under different working states, and the data processing system comprises the following steps: the device comprises a state controller, a divider, a first calculating unit, a second calculating unit and an initial position determining unit;
the state controller is used for controlling the system to enter different working states;
the system is in a first state, and the divider determines an input-output frequency sampling ratio;
when the system is in a second state, the initial position determining unit determines the initial position of the prototype filter table and the initial position of original sampling data storage according to the input-output frequency sampling ratio;
in a third state of the system, the first computing unit determines an interpolation coefficient accumulated sum according to the initial position of the prototype filter table, and the second computing unit determines an accumulated sum of products of the interpolation coefficient and the original sample data according to the initial position of the original sample data;
and in a fourth state of the system, the divider determines target sampling data according to the accumulated sum of the interpolation coefficients and the accumulated sum of the products of the interpolation coefficients and the original sampling data.
2. The system of claim 1, wherein the first computing unit comprises one or more multipliers;
the multiplier is used for completing multiplication in a Lagrange interpolation algorithm in a time-sharing mode according to the prototype filter coefficient, the interpolation coefficient and the position difference among the prototype filter coefficients.
3. The system of claim 2, further comprising: the first calculating unit comprises a first multiplier, a second multiplier and a fourth calculating unit;
the first calculation unit determines the position of the prototype filter coefficient in the prototype filter table according to the initial position of the prototype filter table, and continuously reads 4 adjacent prototype filter coefficients h 0-h 3 at the position of the prototype filter coefficient in the prototype filter table; also determining the position difference of the interpolation coefficient and the prototype filter coefficient h0 according to the initial position of the prototype filter table;
the first multiplier and the second multiplier are used for completing multiplication operations in a deformed Lagrange interpolation algorithm in a time-sharing mode according to the position difference among the prototype filter coefficients h 0-h 3, the interpolation coefficient and the prototype filter coefficient h0 in 1-n-1 working clocks, and each multiplier completes a group of multiplication operations in each working clock period;
in the nth working clock, the fourth calculating unit adds the calculation results output by the first multiplier and the second multiplier in the (n-1) th working clock to obtain an interpolation coefficient.
4. The system according to claim 2, wherein the first computing unit comprises a fifth computing unit, configured to sequentially perform an accumulation operation on the interpolation coefficients generated by the first computing unit to obtain the accumulated sum of the interpolation coefficients.
5. The system of claim 3, wherein the second computing unit comprises a third multiplier;
and the third multiplier is used for calculating the accumulated sum of the products of the interpolation coefficients and the original sampling data in the (n + 1) th working clock.
6. The system of claim 1, further comprising: a third calculation unit;
the third calculating unit is used for determining a first clock number corresponding to a third specified number of input sampling periods and a second clock number corresponding to the third specified number of output sampling periods according to the input sampling clock and the output sampling clock;
the divider is used for dividing the first clock number and the second clock number to obtain the input-output frequency sampling ratio.
7. The system according to one of claims 1 to 6,
when the state controller detects that a new sampling point arrives, the state controller outputs a second state control signal to the initial position determining unit to trigger the system to enter a second state;
after the second state is finished, the state controller outputs a third state control signal to the first computing unit to trigger the system to enter a third state;
after the third state is finished, the state controller outputs a fourth state control signal to the divider to trigger the system to enter a fourth state;
and after the fourth state is finished, the state controller outputs a first state control signal to the divider to trigger the system to enter the first state.
8. The system of claim 7, wherein the state controller keeps the system in an idle state or enters an operating state under the control of an enable signal;
when the state controller detects that the enable signal is effective, the state controller outputs a first state control signal to the divider to trigger the system to enter a first state;
when the state controller detects that the enable signal is invalid, the state controller controls the system to enter an idle state.
9. A data processing method is characterized in that in the resampling process of a sampling point, the same divider is controlled to carry out multiple operations under different working states; wherein the content of the first and second substances,
in a first state, determining an input-output frequency sampling ratio by using the divider;
in a second state, determining the initial position of a prototype filter table and the initial position of original sampling data storage according to the input-output frequency sampling ratio;
in a third state, determining an interpolation coefficient accumulated sum according to the initial position of the prototype filter table, and determining an accumulated sum of products of the interpolation coefficient and the original sampling data according to the initial position of the original sampling data storage;
and in a fourth state, determining target sampling data by adopting the divider according to the interpolation coefficient accumulated sum and the accumulated sum of the products of the interpolation coefficients and the original sampling data.
10. The data processing method of claim 9, wherein: and in a third state, one or more multipliers are adopted to complete multiplication operation in the Lagrange interpolation algorithm in a time-sharing manner according to the prototype filter coefficients in the prototype filter table, the interpolation coefficients and the position difference among the prototype filter coefficients.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201810861079.5A CN109194307B (en) | 2018-08-01 | 2018-08-01 | Data processing method and system |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201810861079.5A CN109194307B (en) | 2018-08-01 | 2018-08-01 | Data processing method and system |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| CN109194307A CN109194307A (en) | 2019-01-11 |
| CN109194307B true CN109194307B (en) | 2022-05-27 |
Family
ID=64937639
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN201810861079.5A Active CN109194307B (en) | 2018-08-01 | 2018-08-01 | Data processing method and system |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN109194307B (en) |
Families Citing this family (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN109885970A (en) * | 2019-03-20 | 2019-06-14 | 泉州昆泰芯微电子科技有限公司 | One kind is tabled look-up digital circuit and its processing method |
| CN110708069B (en) * | 2019-06-24 | 2023-05-02 | 珠海全志科技股份有限公司 | Asynchronous sampling rate conversion device and conversion method |
| CN110784226B (en) * | 2019-10-08 | 2022-12-02 | 中国科学院微电子研究所 | Data processing method and data processing device based on PCM compression coding |
| CN113630212B (en) * | 2021-08-05 | 2024-03-19 | 深圳市思码逻辑技术有限公司 | Downsampling method and downsampling device for digital signals |
| CN113766205B (en) * | 2021-09-07 | 2024-02-13 | 上海集成电路研发中心有限公司 | Tone mapping circuit and image processing apparatus |
Citations (39)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH06197222A (en) * | 1992-12-25 | 1994-07-15 | Fuji Xerox Co Ltd | Image processor |
| US5331346A (en) * | 1992-10-07 | 1994-07-19 | Panasonic Technologies, Inc. | Approximating sample rate conversion system |
| CN1251192A (en) * | 1997-11-22 | 2000-04-19 | 皇家菲利浦电子有限公司 | Audio processing arrangement with multiple sources |
| US6313772B1 (en) * | 1999-08-24 | 2001-11-06 | Thomson Licensing S.A. | Complex carrier signal generator for determining cyclic wave shape |
| CN1454347A (en) * | 2000-10-16 | 2003-11-05 | 诺基亚公司 | Multiplier and shift device using signed digit representation |
| JP2004147214A (en) * | 2002-10-25 | 2004-05-20 | Tokai Univ | Filter bank circuit and its design assisting method |
| US6987821B1 (en) * | 1999-09-20 | 2006-01-17 | Broadcom Corporation | Voice and data exchange over a packet based network with scaling error compensation |
| CN1925323A (en) * | 2005-08-30 | 2007-03-07 | 冲电气工业株式会社 | Sampling rate converting method and circuit |
| CN101039291A (en) * | 2006-03-16 | 2007-09-19 | 中国科学院上海微系统与信息技术研究所 | Method and apparatus for correcting residual carrier frequency deviation, fixed phase and amplitude deviation |
| CN101051261A (en) * | 2006-04-07 | 2007-10-10 | 冲电气工业株式会社 | Rounding computing method and computing device therefor |
| CN101083461A (en) * | 2007-07-13 | 2007-12-05 | 北京创毅视讯科技有限公司 | Drop sampling filtering process and drop sampling filter |
| CN101297354A (en) * | 2005-10-28 | 2008-10-29 | 索尼英国有限公司 | Audio processing |
| CN101304305A (en) * | 2008-06-23 | 2008-11-12 | 捷顶微电子（上海）有限公司 | System and method for implementing input signal amplitude normalization |
| CN101309349A (en) * | 2007-05-15 | 2008-11-19 | 索尼株式会社 | Image pickup apparatus and method of correcting captured image data |
| CN101447968A (en) * | 2008-12-29 | 2009-06-03 | 宁波中科集成电路设计中心有限公司 | Frequency deviation capturing method based on pilot signals in a DRM receiver |
| CN101521497A (en) * | 2009-04-14 | 2009-09-02 | 北京中星微电子有限公司 | Self-adapting up-sampling filter |
| CN101840322A (en) * | 2010-01-08 | 2010-09-22 | 北京中星微电子有限公司 | Method for multiplexing filter arithmetic element and filter arithmetic system |
| CN101847088A (en) * | 2010-02-05 | 2010-09-29 | 谭洪舟 | Low-cost arithmetical logic unit based on module and operation code multiplexing |
| CN101873277A (en) * | 2010-06-10 | 2010-10-27 | 复旦大学 | VLSI structure suitable for suppressing channel estimation and equalization algorithms of long echo in DTMB system |
| CN101894559A (en) * | 2010-08-05 | 2010-11-24 | 展讯通信（上海）有限公司 | Audio processing method and device thereof |
| CN101986636A (en) * | 2010-11-19 | 2011-03-16 | 中兴通讯股份有限公司 | Despiking coefficient update method and device suitable for frequency hopping and power fluctuation system |
| CN102185587A (en) * | 2011-03-21 | 2011-09-14 | 浙江大学 | Low-power-consumption multi-order interpolation half-band filter with two-phase structure |
| CN102685055A (en) * | 2011-03-15 | 2012-09-19 | 中国科学院微电子研究所 | Device and method for interpolating, extracting and multiplexing multiple data streams |
| CN102739195A (en) * | 2012-06-06 | 2012-10-17 | 华为技术有限公司 | Processing method, device and system of FIR (finite impulse response) filter |
| CN103119848A (en) * | 2010-09-24 | 2013-05-22 | 株式会社岛津制作所 | Data processing method and device |
| CN103345379A (en) * | 2013-06-09 | 2013-10-09 | 暨南大学 | Complex number multiplying unit and realizing method thereof |
| CN103487806A (en) * | 2013-08-26 | 2014-01-01 | 北京理工大学 | Doppler parameter quadratic fitting method based on time division multiplexing |
| CN103487805A (en) * | 2013-08-26 | 2014-01-01 | 北京理工大学 | Doppler parameter linear fitting method based on time division multiplexing |
| CN104378321A (en) * | 2014-11-26 | 2015-02-25 | 英特格灵芯片(天津)有限公司 | Method and circuit for integrating adaptive equalization parameter adjusting and transmission performance testing |
| CN104810791A (en) * | 2015-05-13 | 2015-07-29 | 国网智能电网研究院 | FPGA (Field Programmable Gate Array)-based differential protection method |
| CN105187078A (en) * | 2015-08-05 | 2015-12-23 | 广州润芯信息技术有限公司 | Digital system for image rejection of low-intermediate-frequency receiver and implementation method thereof |
| CN105245202A (en) * | 2015-10-23 | 2016-01-13 | 厦门科灿信息技术有限公司 | Digital slide average low-pass filter and filtering method thereof |
| CN105867876A (en) * | 2016-03-28 | 2016-08-17 | 武汉芯泰科技有限公司 | Multiply accumulator, multiply accumulator array, digital filter and multiply accumulation method |
| CN106165454A (en) * | 2014-04-02 | 2016-11-23 | 韦勒斯标准与技术协会公司 | Acoustic signal processing method and equipment |
| CN106301287A (en) * | 2016-08-20 | 2017-01-04 | 航天恒星科技有限公司 | A kind of method for resampling and device |
| CN106330240A (en) * | 2015-06-18 | 2017-01-11 | 大唐半导体设计有限公司 | High-low local oscillation generation circuit and apparatus of achieving multiple radios |
| CN106936405A (en) * | 2015-12-30 | 2017-07-07 | 普天信息技术有限公司 | The method and device of single channel digital FIR filter is realized based on FPGA |
| CN107679117A (en) * | 2017-09-18 | 2018-02-09 | 西安交通大学 | A kind of whole audience dense point Rapid matching system |
| CN108020717A (en) * | 2016-10-28 | 2018-05-11 | 三星电机株式会社 | Digital frequency measuring equipment and the camera model including the equipment |
Family Cites Families (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US7756487B2 (en) * | 2006-08-29 | 2010-07-13 | Texas Instruments Incorporated | Local oscillator with non-harmonic ratio between oscillator and RF frequencies using pulse generation and selection |
| US8363734B2 (en) * | 2008-01-12 | 2013-01-29 | Huaya Microelectronics | Multi-directional comb filtering in a digital video decoder |
-
2018
- 2018-08-01 CN CN201810861079.5A patent/CN109194307B/en active Active
Patent Citations (39)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5331346A (en) * | 1992-10-07 | 1994-07-19 | Panasonic Technologies, Inc. | Approximating sample rate conversion system |
| JPH06197222A (en) * | 1992-12-25 | 1994-07-15 | Fuji Xerox Co Ltd | Image processor |
| CN1251192A (en) * | 1997-11-22 | 2000-04-19 | 皇家菲利浦电子有限公司 | Audio processing arrangement with multiple sources |
| US6313772B1 (en) * | 1999-08-24 | 2001-11-06 | Thomson Licensing S.A. | Complex carrier signal generator for determining cyclic wave shape |
| US6987821B1 (en) * | 1999-09-20 | 2006-01-17 | Broadcom Corporation | Voice and data exchange over a packet based network with scaling error compensation |
| CN1454347A (en) * | 2000-10-16 | 2003-11-05 | 诺基亚公司 | Multiplier and shift device using signed digit representation |
| JP2004147214A (en) * | 2002-10-25 | 2004-05-20 | Tokai Univ | Filter bank circuit and its design assisting method |
| CN1925323A (en) * | 2005-08-30 | 2007-03-07 | 冲电气工业株式会社 | Sampling rate converting method and circuit |
| CN101297354A (en) * | 2005-10-28 | 2008-10-29 | 索尼英国有限公司 | Audio processing |
| CN101039291A (en) * | 2006-03-16 | 2007-09-19 | 中国科学院上海微系统与信息技术研究所 | Method and apparatus for correcting residual carrier frequency deviation, fixed phase and amplitude deviation |
| CN101051261A (en) * | 2006-04-07 | 2007-10-10 | 冲电气工业株式会社 | Rounding computing method and computing device therefor |
| CN101309349A (en) * | 2007-05-15 | 2008-11-19 | 索尼株式会社 | Image pickup apparatus and method of correcting captured image data |
| CN101083461A (en) * | 2007-07-13 | 2007-12-05 | 北京创毅视讯科技有限公司 | Drop sampling filtering process and drop sampling filter |
| CN101304305A (en) * | 2008-06-23 | 2008-11-12 | 捷顶微电子（上海）有限公司 | System and method for implementing input signal amplitude normalization |
| CN101447968A (en) * | 2008-12-29 | 2009-06-03 | 宁波中科集成电路设计中心有限公司 | Frequency deviation capturing method based on pilot signals in a DRM receiver |
| CN101521497A (en) * | 2009-04-14 | 2009-09-02 | 北京中星微电子有限公司 | Self-adapting up-sampling filter |
| CN101840322A (en) * | 2010-01-08 | 2010-09-22 | 北京中星微电子有限公司 | Method for multiplexing filter arithmetic element and filter arithmetic system |
| CN101847088A (en) * | 2010-02-05 | 2010-09-29 | 谭洪舟 | Low-cost arithmetical logic unit based on module and operation code multiplexing |
| CN101873277A (en) * | 2010-06-10 | 2010-10-27 | 复旦大学 | VLSI structure suitable for suppressing channel estimation and equalization algorithms of long echo in DTMB system |
| CN101894559A (en) * | 2010-08-05 | 2010-11-24 | 展讯通信（上海）有限公司 | Audio processing method and device thereof |
| CN103119848A (en) * | 2010-09-24 | 2013-05-22 | 株式会社岛津制作所 | Data processing method and device |
| CN101986636A (en) * | 2010-11-19 | 2011-03-16 | 中兴通讯股份有限公司 | Despiking coefficient update method and device suitable for frequency hopping and power fluctuation system |
| CN102685055A (en) * | 2011-03-15 | 2012-09-19 | 中国科学院微电子研究所 | Device and method for interpolating, extracting and multiplexing multiple data streams |
| CN102185587A (en) * | 2011-03-21 | 2011-09-14 | 浙江大学 | Low-power-consumption multi-order interpolation half-band filter with two-phase structure |
| CN102739195A (en) * | 2012-06-06 | 2012-10-17 | 华为技术有限公司 | Processing method, device and system of FIR (finite impulse response) filter |
| CN103345379A (en) * | 2013-06-09 | 2013-10-09 | 暨南大学 | Complex number multiplying unit and realizing method thereof |
| CN103487806A (en) * | 2013-08-26 | 2014-01-01 | 北京理工大学 | Doppler parameter quadratic fitting method based on time division multiplexing |
| CN103487805A (en) * | 2013-08-26 | 2014-01-01 | 北京理工大学 | Doppler parameter linear fitting method based on time division multiplexing |
| CN106165454A (en) * | 2014-04-02 | 2016-11-23 | 韦勒斯标准与技术协会公司 | Acoustic signal processing method and equipment |
| CN104378321A (en) * | 2014-11-26 | 2015-02-25 | 英特格灵芯片(天津)有限公司 | Method and circuit for integrating adaptive equalization parameter adjusting and transmission performance testing |
| CN104810791A (en) * | 2015-05-13 | 2015-07-29 | 国网智能电网研究院 | FPGA (Field Programmable Gate Array)-based differential protection method |
| CN106330240A (en) * | 2015-06-18 | 2017-01-11 | 大唐半导体设计有限公司 | High-low local oscillation generation circuit and apparatus of achieving multiple radios |
| CN105187078A (en) * | 2015-08-05 | 2015-12-23 | 广州润芯信息技术有限公司 | Digital system for image rejection of low-intermediate-frequency receiver and implementation method thereof |
| CN105245202A (en) * | 2015-10-23 | 2016-01-13 | 厦门科灿信息技术有限公司 | Digital slide average low-pass filter and filtering method thereof |
| CN106936405A (en) * | 2015-12-30 | 2017-07-07 | 普天信息技术有限公司 | The method and device of single channel digital FIR filter is realized based on FPGA |
| CN105867876A (en) * | 2016-03-28 | 2016-08-17 | 武汉芯泰科技有限公司 | Multiply accumulator, multiply accumulator array, digital filter and multiply accumulation method |
| CN106301287A (en) * | 2016-08-20 | 2017-01-04 | 航天恒星科技有限公司 | A kind of method for resampling and device |
| CN108020717A (en) * | 2016-10-28 | 2018-05-11 | 三星电机株式会社 | Digital frequency measuring equipment and the camera model including the equipment |
| CN107679117A (en) * | 2017-09-18 | 2018-02-09 | 西安交通大学 | A kind of whole audience dense point Rapid matching system |
Non-Patent Citations (4)
| Title |
|---|
| Kalman 滤波器的硬件优化设计与仿真;白雪;《计算机工程与设计》;20110816;第32卷(第8期);2655-2659 * |
| Low-voltage FIR filter for receivers used in communication systems;L. Lita;《27th International Spring Seminar on Electronics Technology: Meeting the Challenges of Electronics Technology Progress, 2004》;20050801;434-438 * |
| 基于DSP的数字音频均衡器设计;王超;《电子科技》;20120415;第25卷(第4期);60-64 * |
| 应用于MB-OFDM UWB系统的频率综合器的研究与设计;江旭东;《中国优秀博硕士学位论文全文数据库(硕士)》;20090315;I135-137 * |
Also Published As
| Publication number | Publication date |
|---|---|
| CN109194307A (en) | 2019-01-11 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| CN109194307B (en) | Data processing method and system | |
| CN109271133B (en) | Data processing method and system | |
| JP2007166535A5 (en) | ||
| CN104202016A (en) | Any times variable signal up-sampling implementation method and system based on look-up table method | |
| CN102510325B (en) | Digital shunt system | |
| CN101072019B (en) | Wave filter and its filtering method | |
| US6788738B1 (en) | Filter accelerator for a digital signal processor | |
| CN108762719B (en) | Parallel generalized inner product reconstruction controller | |
| US5016011A (en) | Increased performance of digital integrated circuits by processing with multiple-bit-width digits | |
| CN104348446B (en) | A kind of method and filter for realizing FIR filtering | |
| CN114448390A (en) | Biquad digital filter device and implementation method | |
| RU2460130C1 (en) | Method for digital recursive band-pass filtering and digital filter for realising said method | |
| CN101840322B (en) | The arithmetic system of the method that filter arithmetic element is multiplexing and wave filter | |
| CN102253924B (en) | Method for realizing root extraction arithmetic on hardware and root extraction arithmetic device | |
| CN200976573Y (en) | Sample rate converter | |
| US4942396A (en) | To-digit-serial converters for systems processing data in digit-serial format | |
| CN1330089C (en) | Method for combining limiting pulse responsive filting with under sampling | |
| Mintzer | Parallel and cascade microprocessor implementations for digital signal processing | |
| KR101584917B1 (en) | Multi-stage filter apparatus and Method for filtering Using the same | |
| RU2262131C1 (en) | Device for modeling decision taking process | |
| CN109857973A (en) | Infrared data filtering method and device | |
| US7290022B2 (en) | Method and filter arrangement for digital recursive filtering in the time domain | |
| SU1218395A1 (en) | Device for implementing fast fourier transform | |
| Vaithiyanathan et al. | Comparative Study of Single MAC FIR Filter Architectures with Different Multiplication Techniques | |
| CN104467740B (en) | Multi-channel digital filter based on FPGA |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| PB01 | Publication | ||
| PB01 | Publication | ||
| SE01 | Entry into force of request for substantive examination | ||
| SE01 | Entry into force of request for substantive examination | ||
| GR01 | Patent grant | ||
| GR01 | Patent grant |