CN101873277A - VLSI structure suitable for suppressing channel estimation and equalization algorithms of long echo in DTMB system - Google Patents

Abstract

The invention belongs to the technical field of wireless digital communications, in particular to a very large scale integrated circuit (VLSI) structure suitable for suppressing the channel estimation and equalization of a long echo in a digital television/terrestrial multimedia broadcasting (DTMB) system. An channel estimation algorithm adopted by the invention comprises the following steps of: precisely estimating the trailing of a frame header in a frame body and the trailing of the frame body in the frame header by an iterative method; then reconstructing a frame body to acquire precise frame body data; and equalizing the data by using linear interpolation to eliminate the influence of a long multipath on transmission data. The hardware structure provided by the invention comprises a top-level control module, a first in first out (FIFO) module, a fast fourier transform (FFT)/ inverse fast fourier transform (IFFT) module at an N point, an FFI/IFFT module at an N1 point, an interpolation module, a minimum mean squared error (MMSE) module and a frame header/frame body reconstruction module. The algorithm is simplified according to a system clock and a time sequence relation to fulfill the aim of time sharing multiplex of a main module. Compared with the VLSI structure before simplification, the VLSI structure has the advantages of greatly reducing the hardware resources and power consumption.

Description

A kind of DTMB system that is applicable to suppresses the VLSI structure of long echo channel estimating and equalization algorithm

Technical field

The invention belongs to the radio digital communication technical field, be specifically related to a kind of VLSI hardware configuration, can directly apply to channel estimating and balance module in the digital TV ground transmission national standard system.

Background technology

China Digital TV ground transmission system (DTMB) is to propose in August, 2006, has comprised two kinds of transmission modes of multicarrier and single carrier in the system.Wherein the multi-carrier transmission pattern adopts time-domain synchronization OFDM technology (TDS_OFDM); single carrier mode is not carried out the OFDM modulation; different with other standards is not have pilot frequency information among the DTMB; but adopt the frame head of quasi-cyclic pseudo random sequence (PN sequence) as Frame; so both can improve channel capacity; can resist intersymbol interference (ISI) again and play protection effect at interval, can also be used for system synchronization and channel estimating in receiver end PN sequence simultaneously.

The signal frame of DTMB system is made of frame head and frame two parts, has defined three kinds of frame head modes for being suitable in the different application scenario standards, i.e. PN420, PN595 and PN945.Under PN420 and PN945 pattern, PN inserts frame data front as frame head and forms a kind of quasi-cyclic form.Frame head comprises preamble, PN sequence, back synchronously, and wherein preamble and back are the cyclic extensions of PN sequence synchronously, and sends with the power that is higher than data 3dB.The PN595 pattern adopts the pseudo-random binary sequence of 10 rank maximum lengths, is that length is preceding 595 chips of 1023 m sequence, does not have quasi-cyclic characteristic.Frame head power is identical with frame power.Frame comprises 3780 symbols, and wherein 3744 is valid data, and 36 is system information symbol (TPS).Under multi-carrier mode, carry out the OFDM modulation of 3780 subcarriers, adjacent sub-carrier is spaced apart 2kHz.Do not carry out subcarrier-modulated under single carrier mode, bandwidth is 7.56MHz.

The channel that digital television ground broadcast transmission system faced is the frequency selectivity multipath channel, just needs accurately in order to obtain preferably receptivity that channel estimating compensates receiving data.A kind of fairly simple channel estimation methods be the Chinese invention patent " based on the relevant channel estimator for ground digital multimedia broadcast system of time domain " (grant number is 200710044718.0) of Fudan University application propose based on the relevant channel estimation methods of time domain, but this method requires frame head to have accurate circulation form, and the frame head of PN595 pattern does not satisfy accurate circulation form requirement, so this method can not be used for the syntype channel estimating.Another kind method is based on the frequency domain channel estimation method of FFT, under the less channel situation of multipath delay, only need to utilize the frame head data that receives and local PN sequence to be divided by and be transformed into time domain then at frequency domain, utilize the method for interpolation can obtain channel information accurately again, thereby carry out equilibrium, but can not ignore in the phase mutual interference between frame head and the frame under the adverse circumstances that have long echo, the influence that in channel estimation process, just need eliminate disturb by certain method, thus channel information and frame information carry out equilibrium to obtain comparatively accurately.Pattern for multicarrier, the Chinese invention patent of Tsing-Hua University application " the iteration elimination method that pseudo random sequence is filled in a kind of OFDM modulating system " (grant number is 200510012127.6) (being made as patent 1) thus having proposed a kind of method by iteration eliminates gradually and disturbs the algorithm that carries out channel estimating between frame head and the frame, this algorithm can well be resisted the interference of long echo, but single carrier mode is not but mentioned, the algorithm that the present invention proposes is compared all patterns of slightly simplifying and support the DTMB standard definition with patent 1, also proposed a kind of VLSI framework according to algorithm.

Summary of the invention

The object of the present invention is to provide the channel estimating and the balanced VLSI implementation structure that can suppress long echo in a kind of DTMB system,, reduce power consumption to reduce hardware resource.

Algorithm introduction of the present invention:

Provided the channel estimating and the balanced specific algorithm of the inhibition long echo of correspondence of the present invention earlier before introducing hardware configuration, and compare with patent 1, by comparative result as can be seen, this algorithm is simpler than patent 1.

Fig. 1 is the signal structure schematic diagram of transmitting terminal and receiving terminal, wherein (a) represents the signal of transmitting terminal, (b) be the schematic diagram behind the data process channel, because the influence of multipath, hangover all can appear in frame head and frame, (c) be the signal structure of receiving terminal, the individual data of preceding L (L is a channel length) that demonstrate frame head and frame among the figure are the overlapping of hangover and frame head or frame.Formula (1) has been represented the composition of frame data.

$r_{i,k}=\left\{\begin{array}{cc}{x}_{i-1,k+N}+y_{i,k}+w_{i,k},& 0\&le;k<L-1\\ y_{i,k}+w_{i,k},& L\&le;k<M\\ x_{i-1,k-M}+y_{i,k}+w_{i,k},& M\&le;k<M+L-1\\ x_{i-1,k-M}+w_{i,k},& M+L-1\&le;k<M+N\\ x_{i-1,k-M}+y_{i+1,k-M-N}+w_{i,k},& M+N\&le;k<M+N+L-1\end{array}\right.---\left(1\right)$

R is for receiving data in the formula, and x is a frame head data, and y is the frame data, and w is a white Gaussian noise, and M is a frame head length, and N is a frame length, and L is a channel length.

(1) for front cross frame, frame head data that utilization receives and known local PN sequence are transformed into time domain again by being divided by on the time domain, obtain the channel impulse response (CIR) of frame head.Computing formula is:

$\left.\begin{array}{c}{\left\{h_{i,k}\right\}}_{k=0}^{L-1}={\mathrm{<figure-callout\; id="1"\; label="ifft\; N"\; filenames="HSA00000149291600011.png"\; state="\{\{state\}\}">ifft</figure-callout>}}_{N_{}}\end{array}\right[{\mathrm{fft}}_{N_1}\left({\left\{r_{i,k}\right\}}_{k=0}^{M-1}\right)/{\mathrm{fft}}_{N_1}\left({\left\{{\mathrm{PN}}_{i,k}\right\}}_{k=0}^{M-1}\right)]---\left(2\right)$

N in the formula ₁Be 2048, the frequency response values of calculating is carried out MMSE (least mean-square error) filtering, obtain estimated value more accurately, calculate of the hangover of the second frame frame head with the impulse response and the local PN sequence of the filtered second frame frame head then frame.Formula is as follows:

${\left\{y_{i,k}\right\}}_{k=0}^{N1-1}={\mathrm{ifft}}_{N_1}({\mathrm{fft}}_{N_1}{\left\{h_{i,k}\right\}}_{k=0}^{L-1}*{\mathrm{fft}}_{N_1}{\left\{{\mathrm{PN}}_{i,k}\right\}}_{k=0}^{M-1}),(i=2)---\left(3\right)$

${\left\{\mathrm{tail}{\left(\mathrm{PN}\right)}_{i,k}\right\}}_{k=0}^{L-1}={\left\{y_{i,k}\right\}}_{k=N_1-L}^{N_1-1},(i=2)---\left(4\right)$

The frame data of (2) first frames abandon, and are as follows since the frame treatment step of second frame:

1) utilizes i-2 and i-1 (initial value of i is 3) frame CIR

With

By approach based on linear interpolation, obtain the CIR of i-1 frame frame and i frame frame head, be respectively

With The invention is not restricted to only use linear interpolation method, also available other interpolation method.

2) ideal of utilizing formula (3) to calculate i frame frame head receives data

With the data that receive Deduct

Can obtain i-1 frame frame and stay hangover in the i frame frame head

3) hangover of i-1 frame frame head

Obtain in step (1), i-1 frame frame is stayed the hangover in the i frame frame head In previous step is handled, also obtain, can reconstruct the data of frame like this, be shown below:

${\left\{x_{i-1,k}\right\}}_{k=0}^{N-1}={\left\{r_{i-1,k}\right\}}_{k=0}^{N-1}-{\left\{\mathrm{tail}{\left(\mathrm{PN}\right)}_{i-1,k}\right\}}_{k=0}^{L-1}+{\left\{\mathrm{tail}{\left(\mathrm{DATA}\right)}_{i-1,k}\right\}}_{k=0}^{L-1}---\left(5\right)$

I-1 frame frame

Also draw in step 1), equilibrium obtains the estimated value s of i-1 frame frame data _{I, k},

${\left\{S_{i,k}\right\}}_{k=0}^{N-1}={\mathrm{fft}}_N\left({\{x_{i-1},k\}}_{k=0}^{N-1}\right)/{\mathrm{fft}}_N\left({\left\{{\mathrm{ha}}_{i-1,k}\right\}}_{k=0}^{L-1}\right)---\left(6\right)$

N is 3780 in the formula (6), under multi-carrier mode, directly will

Send and remove the operation that TPS (system information) conciliates constellation mapping.If single carrier mode, also will with

Forward time domain (as the formula (7)) to and remove the operation that TPS (system information) conciliates constellation mapping then.

${\left\{s_{i-1,k}\right\}}_{k=0}^{N-1}={\mathrm{ifft}}_N\left({\left\{S_{i-1,k}\right\}}_{k=0}^{N-1}\right)---\left(7\right)$

Separating data after the constellation mapping passes to outer receiver and carries out channel-decoding.

4) utilize

Back 1024 data and

Upgrade i-1 frame frame and stay hangover in the i frame frame head,

${\left\{\mathrm{tail}{\left(\mathrm{DATA}\right)}_{i-1,k}\right\}}_{k=0}^{L-1}={\left\{{\mathrm{ifft}}_{N_1}\right[{\mathrm{fft}}_{N_1}\left({\left\{s_{i-1,k}\right\}}_{k=0}^{N-1}\right)*{\mathrm{fft}}_{N_1}\left({\left\{{\mathrm{ha}}_{i-1,k}\right\}}_{k=0}^{L-1}\right)\left]\right\}}_{k=N}^{N+L-1}---\left(8\right)$

New i frame frame head value is

${\left\{r_{i,k}\right\}}_{k=0}^{L-1}={\left\{r_{i,k}\right\}}_{k=0}^{L-1}-{\left\{\mathrm{tail}{\left(\mathrm{DATA}\right)}_{i-1,k}\right\}}_{k=0}^{L-1}---\left(9\right)$

5) utilize the frame head value that draws in the step 4) to ask the new impulse response of i frame frame head

${\left\{h_{i,k}\right\}}_{k=0}^{L-1}={\mathrm{ifft}}_{N_1}[{\mathrm{fft}}_{N_1}\left({\left\{r_{i,k}\right\}}_{k=0}^{M-1}\right)/{\mathrm{fft}}_{N_1}\left({\left\{{\mathrm{PN}}_{i,k}\right\}}_{k=0}^{M-1}\right)]---\left(10\right)$

Through obtaining channel impulse response value more accurately after the MMSE filtering, formula (3) and (4) in the repeating step (1) obtain new

This is the hangover of i frame frame head to the next frame frame, preserves and the reconstruct of frame when being used for next frame and handling.In the patent 1 with by the second time iteration produce

Calculate with the frame head PN sequence of i frame

Be sent to next frame as final hangover, doing like this to increase by twice N ₁The FFT/IFFT processing procedure of point promptly has more 2063*2=4126 clock cycle, thus if cause adopting the time-sharing multiplex of FFT then the time of a frame occurs handling greater than the problem of the duration of a frame, that is to say can not be constantly the processing received signal.

6) with the hangover in the step 5)

Reconstruct one order i frame frame head obtains final frame head impulse response then after formula (10) and MMSE filtering again With it and the impulse response of former frame frame head

Transmit together and carry out the processing of next frame.Processing procedure is with (2).

Table 1

Parameter	Value
		Symbol rate	?7.56
The constellation mapping mode	?16QAM
		The frame head length M	?420
The frame length N	?3780
		The FFT points N 1	?2048
The FFT points N	?3780
		Doppler frequency shift	?10Hz
Subcarrier spacing	?2kHZ

Table 2

The path	Time-delay (us)	Power (db)
			??1	??1.85	??0
??2	??0	??-18
			??3	??1.95	??-20
??4	??3.57	??-20
			??5	??7.54	??-10
??6	??31.9	??0

Table 1 is the Matlab simulation parameter, invents anti-long echo characteristic in order to test this, has elitely decided Chinese test 8 (CDT8) channel, and power and the identical echo of main footpath intensity are arranged in this channel, and delaying time is that 31.9us, table 2 have provided the parameter of CDT8 channel.The Matlab simulation result as shown in Figure 2, among the figure as can be seen in this algorithm and the patent 1 iterations be to compare in 2 o'clock, performance has very little decline, is 4*10 at BER (bit error rate) ^-3The time, the high 3db of the SNR of this algorithm (signal to noise ratio).

System channel estimator VLSI structural design:

Fig. 3 is the hardware structure diagram of algorithm for this reason, and the frame of broken lines representation module is multiplexing among the figure.Whole hardware configuration mainly comprises following module: the FFT/IFFT module that top layer control module, fifo module, N are ordered, N ₁The FFT/IFFT module of point, interpolating module, MMSE filtration module (in Fig. 2, not drawing) and frame head/frame reconstructed module.

Table 3

The module title	Quantity
		The top layer control module	??1
N point FFT/IFFT	??1
		??N 1Point FFT	??1
??N 1Point IFFT	??1
		Interpolating module	??1
MMSE (least mean-square error estimation)	??1
		Balanced	??1
Divider	??1
		Multiplier	??1
Reconstruct	??1
		??RAM	Some

Table 3 is the hardware resource that comprises of structure for this reason.Multi-carrier mode with PN420 is function and the architectural feature that example is specifically introduced each module below.

The top layer control module, its function is worked under different mode in order for controlling each module by state machine, and the accurately controlling clock cycle, and the time of satisfying processing one frame is consistent with the time that frame data continue.These control signals comprise that the writing of generation, each RAM of the input enable signal of each module, the status signal of each module work, local PN sequence enables and read to enable and write address and read address signal etc.Also have remaining time after all calculating are finished under determined clock frequency among the present invention, the clock of then during this period of time closing all modules except that FIFO activates corresponding clock again up to the data that receive next frame.

Fifo module adopts two block RAMs (being designated as RAM0 and RAM1 respectively), to back one frame operation, realizes pipeline processes when can realize depositing former frame, saves clock.The frame head positional information that this module provides with synchronization module and 24 (wherein real part and imaginary part bes' each 12) frame data are input, when detecting frame head position signalling prc_start and be high level, the enable signal of writing of RAM0 is changed to height, unison counter (being write address) begins counting, and write data every 8 data in RAM, this is because the data of input are 8 times of over-samplings.In like manner, when next frame head position signalling arrives, data are write RAM1, use so in turn, when counter meter to 4200 (420 frame head information and 3780 frame information), stop to write.To read enable signal when in calculating, needing frame head or frame data and be changed to height, be input to corresponding module.

N ₁The FFT/IFFT module of point, the algorithm of FFT and IFFT is very similar, but considers sequence problem, realizes FFT and IFFT operation respectively with two modules among the present invention.Their function has to put on the frequency domain removes calculating channel impulse response value, and dot product is calculated the convolution value of frame head and channel impulse response, and the hangover of calculating frame head and frame.The present invention adopts base 4 frequency domain extraction method, totally six level structures, and calculating the clock cycle that needs is 2063.

The MMSE module, this module is positioned at N ₁The back of the FFT/IFFT module of point.MMSE filtering can be regulated formula according to adaptive threshold in the MMSE algorithm and carry out filtering at dateout, the filtering method effect is relatively good like this, can carry out filtering to dateout according to the default fixed threshold of the simulation result of algorithm performance in addition, like this can shortcut calculation, save the clock cycle.Among the present invention for easy usefulness be that the back is a kind of, but be not limited to that this is a kind of.

N point FFT/IFFT module, its function is that data are carried out equilibrium, divides single carrier and multicarrier two kinds of pattern outputs.When doing complex division, carry out the equilibrium of amplitude and phase place respectively.The cordic module is adopted in the equilibrium of phase place, and the equilibrium of amplitude is used look-up table to add multiplier and realized.Adopt 6 grades of frequency domain extraction methods among the present invention, radix is 5x7x4x3x3x3, and calculating the clock cycle that needs is 3808.

Interpolating module, its function are to carry out interpolation, are promptly obtained the estimated value of channel impulse response of i-1 frame frame and i frame frame head by interpolation method by the channel impulse response of i-2 that estimates and i-1 frame frame head.Easy for calculating, what adopt among the present invention is approach based on linear interpolation, but does not limit to and this method, in addition also available arest neighbors interpolation, low-pass filtering interpolation, Wiener filtering interpolation etc.

Reconstructed module, its function comprises according to N ₁The hangover that some FFT module is calculated, or the convolution value of frame head and channel adds reducing accordingly.Effect is to eliminate influencing each other between frame head and frame, the circular convolution form of structure frame head frame.

For the area of chip estimate, we have made comprehensively design of the Design Compiler instrument of synopsys company, and compages show removes that the design's area is approximately 330,000 equivalent gates outside the memory.

Description of drawings

Fig. 1 is the signal model of transmitting terminal and receiving terminal, and wherein the signal model of (a) expression transmitting terminal (b) for the model through frame head behind the channel and frame, (c) is the signal model of receiving terminal.

Fig. 2 is overall framework and a data flow diagram of the present invention.

Fig. 3 compares with the bit error rate of patent 1 under CDT8 (China's test 8) the different signal to noise ratios of channel for the present invention.

Embodiment

This scheme is used for the realization based on the channel estimating part of DTMB system receiver, through verifying on FPGA, has obtained good effect (the FPGA model is EP2S130F102C5).Multi-carrier mode with PN420 is the concrete steps that example is introduced this channel estimating implementation method below:

Fig. 2 is the hardware structure diagram of algorithm for this reason, and the frame of broken lines representation module is multiplexing among the figure.Whole hardware configuration mainly comprises following module: the FFT/IFFT module that top layer control module, fifo module, N are ordered, N ₁The FFT/IFFT module of point, interpolating module, MMSE filtration module (in Fig. 2, not drawing) and frame head/frame reconstructed module.

With the example that is treated to of a frame, step is as follows:

(1) at first local PN sequence is N ₁Put FFT (calculating that relates to FFT/IFFT herein all mends 0 in the back for the curtailment part) and store this calculating and need 2063 clock cycle altogether, because this result will use 4 times in the subsequent calculations process, can directly read usefulness the time like this and do not need to recomputate, both can save the clock cycle, can reduce power consumption again.

(2) output of then previous frame being handled With

Read the input of handling as this frame (i.e. i-1 frame) and enter interpolating module from RAM, the major function of interpolating module is this frame frame of this frame of estimation frame and the channel impulse response of next frame frame head

With

Utilize the simplest approach based on linear interpolation to obtain at this:

${\left\{{\mathrm{ha}}_{i-1,k}\right\}}_{k=0}^{L-1}={\left\{h_{i-1,k}\right\}}_{k=0}^{L-1}+0.5({\left\{h_{i-1,k}\right\}}_{k=0}^{L-1}-{\left\{h_{i-2,k}\right\}}_{k=0}^{L-1})$

${\left\{h_{i,k}\right\}}_{k=0}^{L-1}={\left\{h_{i-1,k}\right\}}_{k=0}^{L-1}+\left(\right\{{h_{i-1,k}\}}_{k=0}^{L-1}-{\left\{h_{i-2,k}\right\}}_{k=0}^{L-1})$

This calculating only need just can be calculated and be finished a clock cycle, and the result is delivered to N point and N respectively ₁Point FFT module.

(3) with N point and N ₁The input enable signal of some FFT module is changed to height, continues N point and N respectively ₁The individual clock cycle, will

FFT FFT as a result _N(ha) deposit among the RAM, and

FFT result

Enter multiplication module, another input signal of multiplier is to read among the RAM

Result after both are multiplied each other outputs to N ₁Point IFFT module is converted to time domain, obtains the approximation theory value of frame head information, and this theoretical value M (frame head data number) data afterwards are the hangover estimated value of frame head, are designated as tail _i(head) also storage.

(4) read the frame head information of next frame from FIFO, and deduct the approximation theory value of the frame head information that previous step calculates, that obtain promptly is the hangover tail of frame to the next frame frame head _I-1(DATA).From FIFO, read frame, and from RAM, read frame head that upper level calculates hangover tail frame _I-1(head), frame information is deducted tail _I-1(head) and add tail _I-1(DATA) can construct the circular convolution form of frame.

(5) frame that reconstructs is input to N point FFT module, the input enable signal is changed to height, at this moment distance once more

Input individual clock cycle of 4126 (2063x2), and input duration N equals 3780, so can not cause conflict, after FFT calculates and finishes with RAM in FFT _N(ha) enter into divider module together, the frequency domain S value that obtains estimating is deposited among the RAM.Simultaneously will

Be input to N ₁Point FFT module obtains

And store among the RAM.

(6) under multi-carrier mode, because data are modulated through OFDM at transmitting terminal, be equivalent to be the IFFT that N is ordered, the S value that this thing obtains is the emission data that estimate, with this value output.Calculate the s value of time domain then, promptly S is the IFFT that N is ordered, because calculating, the FFT that N is ordered needs 3808 clock cycle, want not only to realize FFT but also realize IFFT with a module, can not pile line operation, the low level duration must be greater than 3808 clock cycle at interval for their input enable signal, so be input to N point FFT module with reading the S value after counter controls time-delay 3808 clock cycle, and it is low to select FFT/IFFT signal fft_ifft_sel to be changed to, and realizes the calculating of IFFT.

(7) recomputate tail _I-1(DATA), back 1024 data with the s value that obtains are input to N ₁Point FFT module is with among result and the RAM

Be input to multiplication module together, at process N ₁Change to time domain behind the some IFFT, back 1024 data are the hangover tail of frame to next frame _I-1(DATA).Frame head information is deducted this hangover and adds tail _i(head) promptly reconstruct the frame head of i frame.

(8) frame head that reconstructs is input to N ₁The point FFT and with the result with Obtain new after being divided by through IFFT

Enter the MMSE module then, obtain more accurately after the filtering

(9)

Be input to N ₁The point FFT and with the result with Obtain frame head theoretical value more accurately through IFFT after multiplying each other, this theoretical value M (frame head data number) data afterwards are the hangover estimated value of frame head, are designated as tail _i(head) also storage is called when next frame is handled by the time.

(10) frame head information is deducted hangover tail _I-1(DATA) and add tail _i(head) reconstruct the frame head of i frame once more.The frame head that reconstructs is input to N ₁The point FFT and with the result with

Obtain new after being divided by through IFFT

Enter the MMSE module then, obtain final after the filtering

And storage waits until that next frame calls when handling.

Advantage of the present invention is by reasonable arrangement sequential, realizes the time-sharing multiplex of main modular, has reduced so greatly the area of chip. And also considered to add the control clock of crossing the threshold in the design, greatly reduced power consumption.

Claims (2)

1. one kind is applicable to that the DTMB system suppresses long echo channel estimating and balanced VLSI structure, is characterized in that it comprises with lower module: the FFT/IFFT module that top layer control module, fifo module, N are ordered, N ₁The FFT/IFFT module of point, interpolating module, MMSE filtration module and frame head/frame reconstructed module; Wherein:

Described top layer control module, its function is worked under different mode in order for controlling each module by state machine, and the accurately controlling clock cycle, the time of satisfying processing one frame is consistent with the time that frame data continue, close the clock of all modules except that fifo module if there is residue the time, activate corresponding clock again up to the data that receive next frame;

Described fifo module adopts two block RAMs, to back one frame operation, realizes pipeline processes when realizing depositing former frame;

Described N ₁The FFT/IFFT module of point, its function has: point removes calculating channel impulse response value on the frequency domain, and dot product is calculated the convolution value of frame head and channel impulse response, and the hangover of calculating frame head and frame;

Described MMSE module is positioned at N ₁The FFT/IFFT module rear of point, MMSE module are regulated formula according to adaptive threshold in the MMSE algorithm and are carried out filtering at dateout, and according to the default fixed threshold of the simulation result of algorithm performance dateout are carried out filtering;

Described N point FFT/IFFT module, its function is that data are carried out equilibrium, divides single carrier and multicarrier two kinds of pattern outputs; Wherein, when doing complex division, the cordic module is adopted in the equilibrium of phase place, and the equilibrium of amplitude is adopted look-up table to add multiplier and realized;

Described interpolating module, its function are to carry out interpolation, are promptly obtained the estimated value of channel impulse response of i-1 frame frame and i frame frame head by interpolation method by the channel impulse response of i-2 that estimates and i-1 frame frame head;

Described reconstructed module, its function comprises according to N ₁The hangover that some FFT module is calculated, or the convolution value of frame head and channel adds reducing accordingly, to eliminate influencing each other between frame head and frame, the circular convolution form of structure frame head frame.

2. the DTMB system that is applicable to according to claim 1 suppresses long echo channel estimating and balanced VLSI structure, it is characterized in that the handling process of this structure is:

Earlier the local PN sequence of this frame is passed through N ₁Point FFT, and deposit among the RAM; Move interpolating module, obtain the channel estimation value of present frame frame and next frame frame head

Then will

Deliver to N point FFT module, simultaneously will

Be N ₁Point FFT and with RAM in the FFT result of PN by multiplier, be IFFT again, the result who obtains subtracts each other the calculating of finishing the frame hangover with FIFO output ground frame head information, the frame information of utilizing fifo module to export is then finished the reconstruct of frame;

The frame data that reconstruct are done FFT and the equilibrium operation module that N is ordered, meanwhile right

Be N ₁The point FFT, carry out then frame head reconstruct and

Renewal and enter next iteration; In second time iterative process, at first obtain frame head data and stay the hangover in the frame and deposit when next frame is handled by the time among the RAM and call, upgrade then frame head and

And will

Deposit when next frame is handled by the time among the RAM and call.

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