CN109194307A - Data processing method and system - Google Patents
Data processing method and system Download PDFInfo
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- CN109194307A CN109194307A CN201810861079.5A CN201810861079A CN109194307A CN 109194307 A CN109194307 A CN 109194307A CN 201810861079 A CN201810861079 A CN 201810861079A CN 109194307 A CN109194307 A CN 109194307A
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03H—IMPEDANCE NETWORKS, e.g. RESONANT CIRCUITS; RESONATORS
- H03H17/00—Networks using digital techniques
- H03H17/02—Frequency selective networks
- H03H17/06—Non-recursive filters
- H03H17/0621—Non-recursive filters with input-sampling frequency and output-delivery frequency which differ, e.g. extrapolation; Anti-aliasing
- H03H17/0635—Non-recursive filters with input-sampling frequency and output-delivery frequency which differ, e.g. extrapolation; Anti-aliasing characterized by the ratio between the input-sampling and output-delivery frequencies
- H03H17/065—Non-recursive filters with input-sampling frequency and output-delivery frequency which differ, e.g. extrapolation; Anti-aliasing characterized by the ratio between the input-sampling and output-delivery frequencies the ratio being integer
- H03H17/0657—Non-recursive filters with input-sampling frequency and output-delivery frequency which differ, e.g. extrapolation; Anti-aliasing characterized by the ratio between the input-sampling and output-delivery frequencies the ratio being integer where the output-delivery frequency is higher than the input sampling frequency, i.e. interpolation
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03H—IMPEDANCE NETWORKS, e.g. RESONANT CIRCUITS; RESONATORS
- H03H17/00—Networks using digital techniques
- H03H17/02—Frequency selective networks
- H03H17/0223—Computation saving measures; Accelerating measures
- H03H17/0225—Measures concerning the multipliers
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03H—IMPEDANCE NETWORKS, e.g. RESONANT CIRCUITS; RESONATORS
- H03H17/00—Networks using digital techniques
- H03H17/02—Frequency selective networks
- H03H17/0223—Computation saving measures; Accelerating measures
- H03H17/0227—Measures concerning the coefficients
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03H—IMPEDANCE NETWORKS, e.g. RESONANT CIRCUITS; RESONATORS
- H03H17/00—Networks using digital techniques
- H03H2017/0072—Theoretical filter design
- H03H2017/0081—Theoretical filter design of FIR filters
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03H—IMPEDANCE NETWORKS, e.g. RESONANT CIRCUITS; RESONATORS
- H03H17/00—Networks using digital techniques
- H03H17/02—Frequency selective networks
- H03H17/0223—Computation saving measures; Accelerating measures
- H03H2017/0245—Measures to reduce power consumption
Abstract
A kind of data processing method and system are provided in the embodiment of the present invention, it can be during the resampling of a sampled point, multiple operation is carried out under different working conditions using the same divider, such as in first state, input and output frequency sampling ratio is determined using divider, in the 4th state, using the divider according to interpolation coefficient it is cumulative and and interpolation coefficient and original sampling data product add up and, determine destination sample data, in entire calculating process, divider is multiplexed in different states.Further, the present invention can also in the third state time-sharing multiplex multiplier, with complete Lagrange's interpolation calculating.Since the present invention realizes divider/multiplier time-sharing multiplex, the cost and chip power-consumption of product can be significantly reduced, the competitiveness of product is improved.
Description
Technical field
The present invention relates to technical field of data processing more particularly to a kind of data processing methods and system.
Background technique
With the extensive use of digital audio, the promotion and popularization of various data interface techniques, audio signal can pass through
External equipment with various data-interfaces is transmitted to the portable device with identical data interface, so that having identical
The portable device of data-interface can play the audio, for example, the equipment with USB interface is to the portable of USB interface
Formula audio frequency apparatus transmits audio, the equipment with blue tooth interface and transmits audio to the portable audio device with blue tooth interface
Deng.
Since external equipment and portable device are different equipment, audio signal is transmitted in two different domains, this is just
It needs first to carry out asynchronous-sampling to the audio signal from external equipment just to may be implemented just at the sample rate required with broadcasting
Often play.Original sampling frequency conversion is requirement of the new sample frequency to adapt to different sample rates by resampling, usually
The algorithm used is to add extraction (or interpolation) structure to realize based on low-pass filter, but need to occupy during realizing a large amount of
Hardware resource such as calculating input and output sample frequency ratio and filtering in particular for multiple groups multiplier and divider is used
Device will use divider when normalizing；A large amount of multiplier is used when calculating interpolation coefficient and FIR is filtered, so that using
The chip area of this mode is larger, greatly increases hardware cost and chip power-consumption, and reduces product competitiveness.
Summary of the invention
A kind of data processing method and system are provided in the embodiment of the present invention, reduce the area of chip.
As the first aspect of the present invention, a kind of data processing system is provided, it can be in the resampling process of a sampled point
In, multiple operation is carried out under different working conditions using the same divider, the system may include: state controller,
Divider, the first computing unit, the second computing unit, initial position determination unit；
The state controller enters different working conditions for controlling the system；
For the system in first state, the divider determines input and output frequency sampling ratio；
The system is in the second state, and the initial position determination unit is according to the input and output frequency sampling than true
Determine the initial position of ptototype filter table and the initial position of original sampling data storage；
For the system in the third state, first computing unit is true according to the initial position of the ptototype filter table
Determine interpolation coefficient it is cumulative and and second computing unit interpolation system determined according to the initial position that original sampling data stores
It is several with the cumulative of original sampling data product and；
The system is in the 4th state, and the divider is added up according to the interpolation coefficient and and the interpolation coefficient
With the cumulative of original sampling data product and, determine destination sample data.
Further, first computing unit may include one or more multipliers；
The multiplier is used for according to the position between ptototype filter coefficient, interpolation coefficient and ptototype filter coefficient
The multiplying in Lagrange's interpolation algorithm is completed in difference, timesharing.
Preferably, first computing unit may include the first multiplier, the second multiplier and the 4th computing unit；
First computing unit determines that ptototype filter coefficient is filtered in prototype according to the initial position of ptototype filter table
The position of wave device table, and 4 adjacent 0~h3 of ptototype filter coefficient h are continuously read in the position；Also according to ptototype filter
The initial position of table determines the alternate position spike of interpolation coefficient and ptototype filter coefficient h 0；
First multiplier and the second multiplier are used in the 1~n-1 work clock, are filtered according to the prototype
Deformed Lagrange is completed in alternate position spike between 0~h3 of device coefficient h, interpolation coefficient and ptototype filter coefficient h 0, timesharing
Multiplying in interpolation algorithm, each multiplier complete one group of multiplying in each operating clock cycle；
In n-th of work clock, the 4th computing unit is by the first multiplier and the second multiplier in (n-1)th work
The calculated result for making clock output is added to obtain interpolation coefficient.
Further, first computing unit may include the 5th computing unit, for successively calculating described first
The interpolation coefficient that unit generates carries out accumulating operation, obtain the interpolation coefficient it is cumulative and.
Further, second computing unit may include third multiplier；
The third multiplier is used in (n+1)th work clock, calculates interpolation coefficient and original sampling data product
It is cumulative and.
Further, it may also include that third computing unit；
The third computing unit is used for according to input sample clock and output sampling clock, determines third specified quantity
The output sampling period corresponding second clock number of input sample period corresponding first clock number and the third specified quantity；
The divider obtains the input and output frequency for first clock number and the second clock number to be divided by
Rate samples ratio.
Further, when the state controller detects that new sampled point arrives, the state controller output the
Two-state controls signal to the initial position determination unit, triggers the system into the second state；
After second state, the state controller output third state controls signal to first calculating
Unit triggers the system and enters the third state；
After the third state, state controller the 4th state control signal of output to the divider,
The system is triggered into the 4th state；
After four state, the state controller output first state control signal to the divider,
It triggers the system and enters first state.
Preferably, the state controller can make system keep idle state under the control of enable signal or enter work
State；
When state controller detects that enable signal is effective, the state controller output first state control signal is extremely
The divider, triggering system enter first state；
When state controller detects that enable signal is invalid, the state controller control system enters idle state.
As another aspect of the present invention, a kind of data processing method is provided, during the resampling of a sampled point,
It controls the same divider and carries out multiple operation under different working conditions；Wherein,
In the first state, input and output frequency sampling ratio is determined using the divider；
In the second condition, the initial position and original according to the input and output frequency sampling than determining ptototype filter table
The initial position of beginning sampled data storage；
In a third condition, determine that interpolation coefficient adds up and Yi Jigen according to the initial position of the ptototype filter table
According to the initial position that the original sampling data stores determine the cumulative of interpolation coefficient and original sampling data product and；
Under the 4th state, using the divider according to the interpolation coefficient is cumulative and and the interpolation coefficient and original
Beginning sampled data product cumulative and, determine destination sample data.
It further, in a third condition, can be using one or more multipliers, according to the original in ptototype filter table
Alternate position spike between mode filter coefficient, interpolation coefficient and ptototype filter coefficient, timesharing are completed in Lagrange's interpolation algorithm
Multiplying.
Data processing system and method provided in an embodiment of the present invention can adopt during the resampling of a sampled point
Multiple operation is carried out under different working conditions with the same divider, such as in first state, is determined using divider defeated
Enter output frequency sampling ratio, in the 4th state, using the divider according to interpolation coefficient is cumulative and and interpolation coefficient and original
Beginning sampled data product cumulative and, determine destination sample data, in entire calculating process, divider is in different states
Multiplexing.
Further, the present invention can also in the third state time-sharing multiplex multiplier, to complete in terms of Lagrange's interpolation
It calculates.
Since the present invention realizes divider/multiplier time-sharing multiplex, the quantity of hardware is reduced, hence it is evident that reduce core
The area of piece, a large amount of multiplier, divider will be used using usual manner calculating sample frequency in the prior art by solving
Equal hardware, chip area is larger, is unfavorable for being integrated to the problems in corresponding circuit, so as to significantly reduce product cost and
Chip power-consumption improves the competitiveness of product.
Detailed description of the invention
The drawings described herein are used to provide a further understanding of the present invention, constitutes a part of the invention, this hair
Bright illustrative embodiments and their description are used to explain the present invention, and are not constituted improper limitations of the present invention.In the accompanying drawings:
Fig. 1 is the work clock and data waveform figure in the embodiment of the present invention in data processing system；
Fig. 2 is the state flow chart of data processing system provided in an embodiment of the present invention；
Fig. 3 is the structural schematic diagram of data processing system provided in an embodiment of the present invention；
Fig. 4 is Lagrange interpolation coefficient figure in the embodiment of the present invention；
Fig. 5 is the flow chart of data processing method provided in an embodiment of the present invention.
Specific embodiment
In order to which technical solution in the embodiment of the present invention and advantage is more clearly understood, below in conjunction with attached drawing to the present invention
Exemplary embodiment be described in more detail, it is clear that described embodiment is only that a part of the invention is implemented
Example, rather than the exhaustion of all embodiments.It should be noted that in the absence of conflict, embodiment and reality in the present invention
The feature applied in example can be combined with each other.
Data processing system in the embodiment of the present invention can be applied to set containing processing chip and the portable of memory
It is standby.
Be treated in journey to audio data, in order to meet the requirement of different frequency, usually will to audio data into
Row resampling.Original frequency transformation is requirement of the new frequency to adapt to different frequency by resampling.In the meter of resampling
In calculation, filtering algorithm, interpolation calculation etc. can be used, mainly uses divider, multiplier in hardware aspect.In conventional design,
It carries out a division arithmetic just to need to carry out multiple division arithmetic using a divider, it is necessary to use multiple dividers；Together
Sample, carry out multiplication operation, it is necessary to use a multiplier, carry out multiple multiplying, it is necessary to multiply using multiple
Musical instruments used in a Buddhist or Taoist mass.Divider and number of multipliers use more, and hardware cost is higher, and chip area is also bigger.
Inventors have found that due to working clock frequency of the hardware with fixation for carrying out frequency processing, and work clock
The frequency of original sampling data when frequency is often greater than resampling, the frequency for working at the same time clock can be greater than resampling toward contact
The frequency of target data.Based on above-mentioned discovery, it has been recognised by the inventors that can use work clock and original sampling data and work
Difference between clock and target data frequency controls the same divider or multiplies during the resampling of a sampled point
Musical instruments used in a Buddhist or Taoist mass carries out multiple operation in the state of difference.In short, during a resampling, by divider or multiplier timesharing
Multiplexing；To reduce hardware quantity, production cost is reduced, reduces chip area.
Fig. 1 is the work clock and data waveform figure in a kind of preferred embodiment of the present invention in data processing system, wherein
Mclk is work clock；Clkin is input sample clock (sampling clock of original sampling data)；Audio_l_in is L channel
Input data, audio_r_in are right channel input data, and audio_l_in and audio_r_in are 24 data；clkout
To export sampling clock (sampling clocks of destination sample data)；Audio_l_out is L channel output data, audio_r_
Out is right channel output data, and audio_l_out and audio_r_out are 24 data；Resample_en is enabled letter
Number.
As shown in Figure 1, in embodiments of the present invention, clkin and clkout be it is asynchronous, need to the corresponding original of clkin
Beginning sampled data is handled, and the corresponding destination sample data of clkout are obtained.In the specific implementation, when input audio has a left side
When right channel, that is, can be to original sampling data as shown in Figure 1 when L channel input data, right channel input data
(original audio data) divides left and right acoustic channels to be respectively processed, and respectively obtains with L channel output data and right channel output number
According to destination sample data (target audio data), to play audio according to different sound channel.Although the embodiment of the present invention
It is so that dual-channel audio data is handled as an example, but one of ordinary skilled in the art should be it is found that core of the invention thought
And method is also applicable to monaural audio data treatment process.
Fig. 2 is a kind of state flow chart for the data processing system that preferred embodiment provides of the present invention；As shown in Fig. 2,
In the embodiment of the present invention, state controller makes system enter different working condition by sending state control signal.When state control
When device processed issues first state control signal, triggering system enters first state S1；When state controller detects new sampling
It (detects that the rising edge of output sampling clock arrives in the present embodiment) when point arrives, exports the second state control signal, touching
Hair system enters the second state S2；After the second state S2 continues the first specified quantity operating clock cycle, state controller is defeated
The third state controls signal out, and triggering system enters third state S3；After S3, state controller exports the 4th state control
Signal processed, triggering system enter the 4th state S4.S1 → S2 → S3 → S4 state converts the weight of a corresponding sampled point
Sampling process.
As a kind of embodiment, when the state controller is initial, even if system the can be entered upon power-up of the system
One state S1；
As another embodiment, the state controller makes under the control of external enable signal resample_en
System keeps idle state S0 or enters working condition.Such as, when enable signal resample_en is invalid (such as low level), shape
The suspend mode of state controller issues idle signal, and system is in idle condition S0, and system does not work.As enable signal resample_
(high level such as is risen to from low level) when en is effective, state controller issues first state and controls signal, and thus triggering system
System enters the working condition of S1~S4.
Fig. 3 is the structural schematic diagram of data processing system provided in an embodiment of the present invention.As shown in figure 3, the present invention is implemented
The data processing system that example provides includes: state controller, divider, the first computing unit, the second computing unit, initial position
Determination unit.
The working principle of the present embodiment shown in Fig. 3 will be described in combination with Fig. 1, Fig. 2 below.
[first state]
For the state controller output first state control signal to divider, triggering system enters S1 state.First
When state S1, divider carries out operation, determines input and output frequency sampling ratio.
Preferably, the system may also include third computing unit.Operation is carried out in divider, determines input and output frequency
Before sampling ratio, third computing unit can use according to work clock mclk and input sample clock clkin to determine third
The input sample period of specified quantity corresponding first clock number, and according to work clock mclk and output sampling clock clkout
Output sampling period corresponding second clock number to determine third specified quantity.Then, divider can be by the first clock number
It is divided by with second clock number, obtains input and output frequency sampling ratio.
First clock number can be the input sample period corresponding operating clock cycle number of third specified quantity,
For example, counting the number of 1024 input sample periods corresponding operating clock cycle by work clock mclk.Described second
Clock number can be the output sampling period corresponding operating clock cycle number of third specified quantity, for example, when passing through work
Clock mclk counts the number of 1024 output sampling periods corresponding operating clock cycle.
In the specific implementation, those skilled in the art can comprehensively consider the face of the data precision, chip performance and chip
Accumulate size, third specified quantity described in sets itself.
First clock number and second clock number are divided by by the divider, obtain the formula of input and output frequency sampling ratio such as
Under:
Input and output frequency sampling ratio=the first clock number/second clock number=fout/fin
Wherein, fin represents original sampling data frequency, and fout represents destination sample data frequency.
In the specific implementation, clock signal is likely to occur phenomena such as shake, delay, as a kind of better embodiment, warp
The input and output frequency sampling ratio being calculated by divider can be exported to be handled to scale detection unit, is detected by ratio
Unit obtains the input and output frequency sampling ratio for needing that up or down transformation is carried out to input sample sample.It is defeated in order to further eliminate
Enter to export the shake of sampling clock, rolling average can be carried out with the input and output frequency sampling ratio that comparative example detection unit obtains
Filtering, the input and output frequency sampling ratio after being optimized.
[the second state]
When state controller detects the rising edge arrival of output sampling clock clkout, state controller output second
State control signal triggers system and enters the second state S2 to initial position determination unit.
In second state S2, prototype of the initial position determination unit according to input and output frequency sampling than determining this filtering
The initial position of initial position and the original sampling data storage of filter table.
It is also known that ptototype filter table is a coefficient table being stored in advance in memory.Wherein, it is filtered from prototype
Take coefficient as the initial position value of ptototype filter table for carrying out Lagrange coefficient interpolation calculation in wave device table.And it is former
Original sampling data is extracted when the initial position of beginning sampled data storage is then used for FIR filtering from memory to be filtered.
In the specific implementation, ptototype filter table in the prior art can be used, the embodiment of the present invention can also be used
In ptototype filter table is realized by the design of the filter of MATLAB and analysis tool.It is made of with one 32 phases, often
A 32 rank of phase, amount to 1024 ranks low pass equiripple filter (equiripple filter) for, ptototype filter system
It is as shown in the table that number generates parameter.
Ptototype filter coefficient generates parameter list:
Since filter coefficient is that symmetrically, as long as the coefficient of storage half, read-only memory size, which can be used, is
1024X24b (coefficient bit wide 24) stores the ptototype filter coefficient of generation.
The initial position and crude sampling of ptototype filter table can be determined using the prior art in embodiments of the present invention
The initial position of data storage, the present invention is without limitation.
Due to determine the initial position of ptototype filter table and the initial position of original sampling data storage it is required when
Between be can be predetermined, therefore, the duration of S2 is also can be predetermined, specifically realizes process at one
In, the duration of the second state is the first specified quantity operating clock cycle.Specifically, which can be 9.
In the specific implementation, a counter can be set to count to the period of work clock mclk, when counting down to the first finger
When fixed number amount operating clock cycle, the second state terminates.For example, when the first specified quantity is 9, adoption status delay counter
State_count is calculated since 0, and when state_count==CNT2 (CNT2 value is set as 8), the second state terminates.Second
At the end of state, state delay counter O reset.
[third state]
After the second state, state controller exports the third state and controls signal to first computing unit, touching
Hair system enters third state S3.
In the third state, the first computing unit determines the interpolation system of this filtering according to the initial position of ptototype filter table
Number it is cumulative and, the second computing unit determines the interpolation coefficient and original of this filtering according to the initial position that original sampling data store
Beginning sampled data product cumulative and.
As a kind of specific embodiment, first computing unit may include one or more multipliers；It is described to multiply
Musical instruments used in a Buddhist or Taoist mass is used for according to the alternate position spike between ptototype filter coefficient, interpolation coefficient and ptototype filter coefficient, and glug is completed in timesharing
Multiplying in bright day interpolation algorithm.
As a kind of preferred embodiment, first computing unit may include the first multiplier, the second multiplier and
Four computing units；
First computing unit determines that ptototype filter coefficient is filtered in prototype according to the initial position of ptototype filter table
The position of wave device table, and 4 adjacent 0~h3 of ptototype filter coefficient h are continuously read in the position；Also according to ptototype filter
The initial position of table determines the alternate position spike of interpolation coefficient and ptototype filter coefficient h 0；
First multiplier and the second multiplier are used in the 1~n-1 work clock, are filtered according to the prototype
Deformed Lagrange is completed in alternate position spike between 0~h3 of device coefficient h, interpolation coefficient and ptototype filter coefficient h 0, timesharing
Multiplying in interpolation algorithm, each multiplier complete one group of multiplying in each operating clock cycle；
In n-th of work clock, the 4th computing unit is by the first multiplier and the second multiplier in (n-1)th work
The calculated result for making clock output is added to obtain interpolation coefficient.
Second computing unit may include third multiplier, and the third multiplier is used in (n+1)th work
In clock, calculate the cumulative of interpolation coefficient and original sampling data product and.
First computing unit further includes the 5th computing unit, for successively inserting what first computing unit generated
Value coefficient carries out accumulating operation, obtain the interpolation coefficient it is cumulative and.
Wherein, first computing unit obtains ptototype filter coefficient in the position of ptototype filter table first, and
The position continuously takes 4 coefficients to calculate for filtering interpolation.Filtering interpolation is calculated can be realized using Lagrange's interpolation algorithm.Figure
4 be Lagrange interpolation coefficient figure in the embodiment of the present invention, and wherein 0~h3 of coefficient h is and continuously takes from ptototype filter table
The adjacent ptototype filter coefficient of 4 out.
Ptototype filter coefficient is calculated in the position of ptototype filter table using following formula:
Pos=pos+step
Wherein, step represents conversion factor, i.e. step-length, and expression ratio detection output ratio moves to left k (k=6), and k's is big
Small decision step-length, that is, determine filter order, the final computational accuracy for determining filter.Pos represents current coefficient position.
The initial position value for the ptototype filter table that will first obtain under S2 state when calculating initial assigns pos and calculates again,
That is current coefficient position pos is always determined by upper one group of coefficient positions pos and conversion factor step.Wherein pos is in the present invention
It is 36, (pos [35:22]) 14 high is integer part, i.e. current coefficient position in ptototype filter table is current by this
Coefficient positions are inquired ptototype filter table and are obtained when the continuous h0~h3 ptototype filter coefficient of previous group is used for interpolation calculation.It is low
22 (pos [21:0]) are fractional part, indicate the alternate position spike between interpolation coefficient and h0, i.e. D value in Fig. 4.When each meter
When new destination sample point, the initial position value for the ptototype filter table that pos value needs to be gone out with S2 state computation is again initial
It is calculated again after change.
First multiplier and the second multiplier are according to the position between 0~h3 of ptototype filter coefficient h, interpolation coefficient and h0
The multiplying in Lagrange's interpolation algorithm is completed in poor D and Lagrange's interpolation algorithm, timesharing.
By taking three ranks Lagrange's interpolation algorithm commonly used in the prior art as an example, three rank Lagrange's interpolation algorithms are commonly used
Calculation formula are as follows:
Coef=[- (D -1) * (D -2) * (D -3)/6] * h0
+[D*(D–2)*(D–3)/2]*h1
+[–D*(D–1)*(D–3)/2]*h2
+[D*(D–1)*(D–2)/6]*h3
Wherein, coef indicates that interpolation coefficient, D indicate the alternate position spike between interpolation coefficient and h0.
It include 12 multiplyings in above formula, therefore the prior art realizes that such operation needs use up to 12 multiplication
Device.Inventors have found that above formula is considered as 4 groups of addend summations, and every group of addend is the product that 4 groups of multipliers are multiplied, therefore in order to
The number of multiplier is reduced, realizes the purpose of time-sharing multiplex multiplier, as a kind of specific embodiment, can be multiplied using 4
Musical instruments used in a Buddhist or Taoist mass, each multiplier timesharing does 3 multiplyings and acquires one group of addend, finally again by the final output knot of 4 multipliers
Fruit is added and acquires coef value.
As one kind, more preferably embodiment, the embodiment of the present invention do above-mentioned Lagrange's interpolation calculation formula at deformation
Reason, when so that this system being calculated according to deformed formula, use multiplier multiplication quadrature that can be few as far as possible, and as multiplication
Each multiplier of the input of device, may each be that several groups of addends are added with or be the product that several groups of multipliers are multiplied.It thus then can be
When configuring multiplier, according to the quantity of the number of addend and the product selection multiplier being multiplied, and the timesharing of each multiplier is determined
Multiplex process.
Therefore, inventor is by above formula respectively with h0, h1 for one group, and with h2, h3 for one group, grouping is extracted common factor formula and deformed
To following formula:
Coef=(D -2) * (D -3)/2* [- (D-1) * h0/3+D*h1]+D* (D-1)/2* [- (D-3) * h2+ (D-2) * h3/
3]
It include 2 groups of totally 8 multiplyings in deformed Lagrange's interpolation formula.It will be before and after each multiplication sign according to multiplication sign
Multiplier, respectively as the input of multiplier, multiplier before and after a multiplication sign completes multiplication fortune in an operating clock cycle
It calculates.2 multipliers may be selected as a result, 4 multiplyings are completed in each multiplier timesharing.As it can be seen that will be passed in the embodiment of the present invention
The Lagrangian Arithmetic deformation of system utilizes multiplier few as far as possible to reduce multiplying number, and multiplying is completed in timesharing,
The number of multiplier can be greatly reduced, and improve the utilization rate of each multiplier.
Obviously, this mentality of designing of the invention and method are applicable not only to the calculation of three rank Lagranges in the present embodiment
Method is also applicable to the calculating situation of other Lagrangian Arithmetics.
During a concrete implementation, n can be more than or equal to 5.To clearly describe core of the invention thought,
Below by taking n=5 as an example.At this point, respectively representing n=5 operating clock cycle with Cycle0~Cycle4.
In Cycle0~Cycle3, first multiplier and second multiplier are according to ptototype filter coefficient h 0
The multiplication in Lagrange's interpolation algorithm is completed in alternate position spike D between~h3, interpolation coefficient and ptototype filter coefficient h 0, timesharing
Operation, calculating process can be as shown in the table.Wherein, it input a and inputs b and respectively represents two of multiplier inputs (two multiply
Number).
First multiplier
Second multiplier
In Cycle4, two multipliers are added in the calculating output of Cycle3 and obtain interpolation coefficient by the 4th computing unit
Coef:(D -2) * (D -3)/2* [- (D-1) * h0/3+D*h1]+D* (D-1)/2* [- (D-3) * h2+ (D-2) * h3/3].
Calculating is circuited sequentially in this way, from current initial position until coefficient table caudal knot beam, calculates and how many a interpolation coefficients arrived, just
The filtering of how many ranks is represented, is subject to practical calculating.
It should be noted that in the specific implementation, it can also be according to the preparation of multiplier, and fully consider peak aging
Ground utilizes multiplier, configures multiplier in the input a and input b that each Cycle is above-mentioned multiplier, and is not limited to feelings listed by table
Shape.For example, if D value and h0, h1 value have been prepared for when Cycle0 arrives, the first multiplier or second listed by upper table
Multiplier can be interchanged in the multiplication calculating that Cycle0 and Cycle1 is carried out.
After above-mentioned interpolation coefficient coef is generated, the 5th computing unit, which is added up the interpolation coefficient to obtain interpolation coefficient, to be tired out
Adduction.Totalization formula is as follows:
Wherein coef_accum is the accumulated value of interpolation coefficient, and coef (i) is i-th of interpolation coefficient value.
After above-mentioned interpolation coefficient coef is generated, third multiplier for (when n=5, being in (n+1)th work clock
Cycle5), calculate the cumulative of interpolation coefficient and original sampling data product and.
Calculation formula are as follows:
Wherein samp_accum is interpolation coefficient and input sampling data multiplies accumulating value, and coef (i) is i-th of interpolation coefficient
Value, sample (i) be i-th of input sampling data (when for dual-channel audio data handle when, then can be 24 L channels or
24 right datas).
Original sampling data can be read in memory according to the initial position of the sampled data storage obtained in S2；It is former
Beginning sampled data stores in sram, reads and writes data by address control unit.128X48b, audio data are used in the present invention
For 24 binary channels, depth 128.
In embodiments of the present invention, reading original sampling data and calculating interpolation coefficient is two parallel processes, mutually
Between do not interfere.
In the specific implementation, the calculating process of third multiplier can be as shown in the table.Wherein, input a and input b difference
Represent two inputs (two multipliers) of third multiplier.
Third multiplier
| Clock | Cycle5 | Cycle10 | Cycle11 |
| Input a | coef(0) | coef(1) | coef(2) |
| Input b | sample(0) | sample(1) | sample(2) |
| Output | coef(0)*sample(0) | coef(1)*sample(1) | coef(2)*sample(2) |
Accumulation result is as follows:
It needs 5 cycle to complete to calculate by interpolation coefficient in this present embodiment, therefore next insert can calculated every time
Interpolation coefficient and input original sampling data are taken at the time of first cycle (Cycle5, Cycle10 ...) of value coefficient, are done and are multiplied
Accumulation process.
It is understood that the interpolation coefficient calculated every time will be kept in next 5 cycle, work as calculating
Out when new interpolation coefficient, it is revised as new interpolation coefficient.Therefore when next interpolation coefficient calculates, i.e., next
Calculated when the cycle0 in 5 cycle periods it is cumulative and.It calculates interpolation coefficient and calculating this two pieces thing of accumulated value is parallel.
The above cycle is work clock.In dual-channel audio data processing, left and right acoustic channels calculation method is the same, that is, divides
Samp_accum_l and samp_accum_r are not calculated.
It should be noted that in embodiments of the present invention, having many coefficients in ptototype filter table, from current initial bit
It sets until coefficient table caudal knot beam, how many coefficient, just represents the filtering of how many ranks, be subject to practical calculating.Such as final calculating
10 interpolation coefficients (each is calculated by different groups of h0~h3 and D value) out, then being exactly 10 ranks, need from sampling
10 data and this 10 interpolation coefficients are taken to be multiplied accumulating in data storage.
As shown in the above, in one preferred embodiment of the invention, 3 multipliers be only used, just completed
Whole calculating processes, significantly reduces hardware cost.
[the 4th state]
After the third state, state controller exports the 4th state control signal to the divider, triggers system
Into the 4th state S4.
In 4th state, divider according to interpolation coefficient it is cumulative and and interpolation coefficient and original sampling data product tire out
Adduction, determines destination sample data.The duration of 4th state is the second specified quantity operating clock cycle.Specifically, should
Second specified quantity can be 78.
Since different input and output sample ratio, the number of calculated interpolation coefficient be it is different, i.e., order is not
The same, it can be normalized.
As a kind of preferred embodiment, the divider can be multiplexed, calculating is normalized, to export destination sample number
According to.Normalize calculation formula are as follows:
Filter_out=samp_accum/coef_accum；
Wherein filter_out is destination sample data, and samp_accum is that interpolation coefficient and original sampling data multiply accumulating
(when two-channel, be samp_accum_l or samp_accum_r), coef_accum be the cumulative of interpolation coefficient and.
When the duration that the state controller counts the 4th state arrives, then first state control signal is issued,
System is set to enter first state S1, thus when system waits new sampled point to arrive (rising edge of output sampling clock arrives),
It is calculated with starting the resampling of new sampled point into S2, and is circuited sequentially by said sequence.
As a kind of preferred embodiment, when state controller detects that the failing edge of enable signal resample_en arrives
When, state controller can control system and enter idle state S0.
Data processing system provided in an embodiment of the present invention exports first state signal, triggering system by state controller
System enters first state, and in the state, divider determines input and output frequency sampling ratio, then, in output sampling clock
Rising edge, state controller export the second state control signal, and triggering system enters the second state, in the second state, initial bit
Initial position and original sampling data of the determination unit according to input and output frequency sampling than determining ptototype filter table is set to store
Initial position, then, after the second state, state controller export the third state control signal, triggering system enter
The third state, in the third state, the first computing unit uses two multiplier time-sharing multiplexes, with according to ptototype filter table just
Beginning position determine interpolation coefficient it is cumulative and and the second computing unit using a multiplier, to be deposited according to original sampling data
The initial position of storage determine the cumulative of interpolation coefficient and original sampling data product and；Finally, after the third state, state
Controller exports the 4th state control signal, and triggering system enters the 4th state, and in the 4th state, divider is according to interpolation coefficient
It is cumulative and and interpolation coefficient and original sampling data product cumulative and, determine destination sample data, so far completion one is adopted
The resampling of sampling point calculates, and in entire calculating process, multiplier and divider are multiplexed in different states, therefore, reduces
The quantity of hardware, reduces the area of chip, hence it is evident that reduces production cost, solves and utilize usual manner in the prior art
The hardware such as a large amount of multiplier, divider will be used by calculating sample frequency, and chip area is larger, the very high problem of cost.
Fig. 5 is the flow chart of data processing method provided in an embodiment of the present invention, as shown in figure 5, the embodiment of the present invention mentions
For a kind of data processing method, during the resampling of a sampled point, the same divider is controlled in different work shapes
Multiple operation is carried out under state；It may include steps of:
101, input and output frequency sampling ratio in the first state, is determined using the divider；
As a kind of better embodiment, under this working condition, work clock mclk and input according to Fig.2, first
Sampling clock clkin is come input sample period corresponding first clock number that determines third specified quantity, and according to work clock
Mclk determines the output sampling period of third specified quantity corresponding second clock number with output sampling clock clkout.So
Afterwards, the first clock number and second clock number can be divided by by divider, obtain input and output frequency sampling ratio.
First clock number can be the input sample period corresponding operating clock cycle number of third specified quantity,
For example, counting the number of 1024 input sample periods corresponding operating clock cycle by work clock mclk.Described second
Clock number can be the output sampling period corresponding operating clock cycle number of third specified quantity, for example, when passing through work
Clock mclk counts the number of 1024 output sampling periods corresponding operating clock cycle.
In the specific implementation, those skilled in the art can comprehensively consider the face of the data precision, chip performance and chip
Accumulate size, third specified quantity described in sets itself.
First clock number and second clock number are divided by by the divider, obtain the formula of input and output frequency sampling ratio such as
Under:
Input and output frequency sampling ratio=the first clock number/second clock number=fout/fin
Wherein, fin represents original sampling data frequency, and fout represents destination sample data frequency.
In the specific implementation, clock signal is likely to occur phenomena such as shake, delay, as a kind of better embodiment, warp
The input and output frequency sampling ratio being calculated by divider can carry out ratio detection processing, be needed with obtaining to input sample
The input and output frequency sampling ratio of sample progress up or down transformation.In order to further eliminate the shake of input and output sampling clock,
Moving average filtering can be carried out with the input and output frequency sampling ratio obtained after comparative example detection processing, it is defeated after being optimized
Enter output frequency sampling ratio.
102, in the second condition, the initial position according to the input and output frequency sampling than determining ptototype filter table
With the initial position of original sampling data storage；
The second state is transformed into from first state when detecting that new sampled point arrives as a kind of preferred embodiment.
In the second condition, the initial position and original sampling data according to input and output frequency sampling than determining ptototype filter table are deposited
The initial position of storage.
In embodiments of the present invention, the duration of the second state is the first specified quantity operating clock cycle.Specifically,
First specified quantity can be 9.
103, in a third condition, according to the initial position of the ptototype filter table determine interpolation coefficient it is cumulative and, with
And according to the initial position that the original sampling data stores determine the cumulative of interpolation coefficient and original sampling data product and；
After the second state, that is, enter the third state.In the third state, according to the initial bit of ptototype filter table
Set determining interpolation coefficient it is cumulative and, and interpolation coefficient and crude sampling are determined according to the initial position that original sampling data stores
Data product cumulative and.
In a third condition, using one or more multipliers, according in ptototype filter table ptototype filter coefficient,
The multiplying in Lagrange's interpolation algorithm is completed in alternate position spike between interpolation coefficient and ptototype filter coefficient, timesharing.
, can be according to the multiplying number reduced to the greatest extent in algorithm as a kind of preferred implementation, and utilize few as far as possible
The principle of multiplying is completed in multiplier timesharing, is deformed to common Lagrange's interpolation algorithmic formula in the art.And
According to the quantity of the number of addend included in deformed Lagrangian Arithmetic formula and the product selection multiplier being multiplied, and
Determine the time-sharing multiplex process of each multiplier.
As a kind of specific embodiment, when using common three ranks Lagrange's interpolation algorithm, can be multiplied using two
The multiplying in deformed Lagrange's interpolation algorithmic formula is completed in musical instruments used in a Buddhist or Taoist mass timesharing.Wherein,
Firstly, determining ptototype filter coefficient in the position of ptototype filter table according to the initial position of ptototype filter table
It sets, and continuously reads 4 adjacent 0~h3 of ptototype filter coefficient h in the position；Also according to the initial bit of ptototype filter table
Set the alternate position spike D of determining interpolation coefficient and ptototype filter coefficient h 0；
Secondly, being filtered using two multipliers according to the prototype in the 1~n-1 work clock under this state
Deformed Lagrange is completed in alternate position spike between 0~h3 of device coefficient h, interpolation coefficient and ptototype filter coefficient h 0, timesharing
Multiplying in interpolation algorithm, each multiplier complete one group of multiplying in each operating clock cycle；
Then, in n-th of work clock, by the first multiplier and the second multiplier respectively in (n-1)th work clock
The calculated result of output is added to obtain interpolation coefficient.
Then, using third multiplier in (n+1)th operating clock cycle, interpolation coefficient and crude sampling number are calculated
According to the cumulative of product and.
Also, after interpolation coefficient generation, interpolation coefficient is successively also subjected to accumulating operation, it is cumulative to obtain interpolation coefficient
With.
104, under the 4th state, using the divider according to the interpolation coefficient is cumulative and and the interpolation coefficient
With the cumulative of original sampling data product and, determine destination sample data.
As a kind of preferred embodiment, the duration of the 4th state is the second specified quantity operating clock cycle.Specifically
Ground, divider add up and are divided by by interpolation coefficient with the cumulative of original sampling data product and with interpolation coefficient, obtain target and adopt
Sample data.
105, after the 4th state, return step 101, or enter idle state.
As a kind of specific embodiment, it can enter first state S1 upon power-up of the system, then in the 4th state knot
Shu Hou, return step 101, into first state；
As another embodiment, there can be idle state.That is, when detecting that enable signal is invalid, into the free time
State.When enable signal is effective, return step 101 enters first state.
Wherein, under the original state of notebook data processing method, whether detection enable signal is effective, effectively thens follow the steps
101；It is whether invalid that enable signal can be detected at any time in step 101~105 implementation procedures, once in vain, then stop current
Step executes, into idle state.
Other specific implementation procedures of data processing method provided by the embodiment of the present invention can refer to aforementioned data processing
The content of system, this place are not repeating.
Data processing method provided in an embodiment of the present invention determines that input is defeated using a divider in first state
Frequency sampling ratio out, in the second state, according to input and output frequency sampling than determining ptototype filter table initial position and
The initial position of original sampling data storage determines interpolation system according to the initial position of ptototype filter table in the third state
Number it is cumulative and, and the tired of interpolation coefficient and original sampling data product is determined according to the initial position that original sampling data stores
Adduction；It wherein can be using one or more multipliers according to ptototype filter coefficient, the interpolation coefficient in ptototype filter table
Alternate position spike between ptototype filter coefficient, the multiplying in Lagrange's interpolation algorithm is completed in timesharing, in the 4th state
It is interior, be multiplexed the divider according to interpolation coefficient it is cumulative and and interpolation coefficient and original sampling data product add up and, really
Set the goal sampled data, and the resampling for so far completing a sampled point calculates, in entire calculating process, multiplier and divider
It is multiplexed in different states, therefore, reduces the quantity of hardware, reduce the area of chip, hence it is evident that production cost is reduced,
The hardware such as a large amount of multiplier, divider, core will be used using usual manner calculating sample frequency in the prior art by solving
Piece area is larger, the very high problem of cost.
It should be understood by those skilled in the art that, the embodiment of the present invention can provide as method, system or computer program
Product.Therefore, complete hardware embodiment, complete software embodiment or reality combining software and hardware aspects can be used in the present invention
Apply the form of example.Moreover, it wherein includes the computer of computer usable program code that the present invention, which can be used in one or more,
The computer program implemented in usable storage medium (including but not limited to magnetic disk storage, CD-ROM, optical memory etc.) produces
The form of product.
The present invention be referring to according to the method for the embodiment of the present invention, the process of equipment (system) and computer program product
Figure and/or block diagram describe.It should be understood that every one stream in flowchart and/or the block diagram can be realized by computer program instructions
The combination of process and/or box in journey and/or box and flowchart and/or the block diagram.It can provide these computer programs
Instruct the processor of general purpose computer, special purpose computer, Embedded Processor or other programmable data processing devices to produce
A raw machine, so that being generated by the instruction that computer or the processor of other programmable data processing devices execute for real
The device for the function of being specified in present one or more flows of the flowchart and/or one or more blocks of the block diagram.
These computer program instructions, which may also be stored in, is able to guide computer or other programmable data processing devices with spy
Determine in the computer-readable memory that mode works, so that it includes referring to that instruction stored in the computer readable memory, which generates,
Enable the manufacture of device, the command device realize in one box of one or more flows of the flowchart and/or block diagram or
The function of being specified in multiple boxes.
These computer program instructions also can be loaded onto a computer or other programmable data processing device, so that counting
Series of operation steps are executed on calculation machine or other programmable devices to generate computer implemented processing, thus in computer or
The instruction executed on other programmable devices is provided for realizing in one or more flows of the flowchart and/or block diagram one
The step of function of being specified in a box or multiple boxes.
Although preferred embodiments of the present invention have been described, it is created once a person skilled in the art knows basic
Property concept, then additional changes and modifications may be made to these embodiments.So it includes excellent that the following claims are intended to be interpreted as
It selects embodiment and falls into all change and modification of the scope of the invention.
Obviously, various changes and modifications can be made to the invention without departing from essence of the invention by those skilled in the art
Mind and range.In this way, if these modifications and changes of the present invention belongs to the range of the claims in the present invention and its equivalent technologies
Within, then the present invention is also intended to include these modifications and variations.
Claims (10)
1. a kind of data processing system, which is characterized in that can be during the resampling of a sampled point, using the same division
Device carries out multiple operation under different working conditions, comprising: state controller, divider, the first computing unit, second calculate
Unit, initial position determination unit；
The state controller enters different working conditions for controlling the system；
For the system in first state, the divider determines input and output frequency sampling ratio；
For the system in the second state, the initial position determination unit is more former than determining according to the input and output frequency sampling
The initial position of the initial position of mode filter table and original sampling data storage；
In the third state, first computing unit is determined according to the initial position of the ptototype filter table and is inserted the system
Value coefficient it is cumulative and and second computing unit according to the initial position that original sampling data store determine interpolation coefficient and
Original sampling data product cumulative and；
The system is in the 4th state, and the divider is according to the interpolation coefficient is cumulative and and the interpolation coefficient and original
Beginning sampled data product cumulative and, determine destination sample data.
2. system according to claim 1, which is characterized in that first computing unit includes one or more multiplication
Device；
The multiplier is used for according to the alternate position spike between ptototype filter coefficient, interpolation coefficient and ptototype filter coefficient, point
When complete Lagrange's interpolation algorithm in multiplying.
3. system according to claim 2, which is characterized in that further include: first computing unit includes the first multiplication
Device, the second multiplier and the 4th computing unit；
First computing unit determines ptototype filter coefficient in ptototype filter according to the initial position of ptototype filter table
The position of table, and 4 adjacent 0~h3 of ptototype filter coefficient h are continuously read in the position；Also according to ptototype filter table
Initial position determines the alternate position spike of interpolation coefficient and ptototype filter coefficient h 0；
First multiplier and the second multiplier are used in the 1~n-1 work clock, according to the ptototype filter system
Deformed Lagrange's interpolation is completed in alternate position spike between number h0~h3, interpolation coefficient and ptototype filter coefficient h 0, timesharing
Multiplying in algorithm, each multiplier complete one group of multiplying in each operating clock cycle；
In n-th of work clock, the 4th computing unit is by the first multiplier and the second multiplier in (n-1)th work
The calculated result of clock output is added to obtain interpolation coefficient.
4. system according to claim 2, which is characterized in that first computing unit includes the 5th computing unit, is used
Carry out accumulating operation in the interpolation coefficient for successively generating first computing unit, obtain the interpolation coefficient it is cumulative and.
5. system according to claim 3, which is characterized in that second computing unit includes third multiplier；
The third multiplier is used in (n+1)th work clock, and calculating interpolation coefficient is tired with original sampling data product
Adduction.
6. system according to claim 1, which is characterized in that further include: third computing unit；
The third computing unit is used for according to input sample clock and output sampling clock, the input for determining third specified quantity
The output sampling period corresponding second clock number of sampling period corresponding first clock number and the third specified quantity；
The divider obtains the input and output frequency and adopts for first clock number and the second clock number to be divided by
Sample ratio.
7. according to claim 1 to system described in one of 6, which is characterized in that
When the state controller detects that new sampled point arrives, the state controller exports the second state control signal
To the initial position determination unit, the system is triggered into the second state；
After second state, it is single to first calculating that the state controller output third state controls signal
Member triggers the system and enters the third state；
After the third state, the state controller exports the 4th state control signal to the divider, triggering
The system enters the 4th state；
After four state, the state controller output first state controls signal to the divider, triggering
The system enters first state.
8. system according to claim 7, which is characterized in that the state controller make under the control of enable signal be
Blanket insurance holds idle state or enters working condition；
When state controller detects that enable signal is effective, state controller output first state controls signal to described
Divider, triggering system enter first state；
When state controller detects that enable signal is invalid, the state controller control system enters idle state.
9. a kind of data processing method, which is characterized in that during the resampling of a sampled point, control the same divider
Multiple operation is carried out under different working conditions；Wherein,
In the first state, input and output frequency sampling ratio is determined using the divider；
In the second condition, it than the initial position of determining ptototype filter table and original is adopted according to the input and output frequency sampling
The initial position of sample data storage；
In a third condition, according to the initial position of the ptototype filter table determine interpolation coefficient it is cumulative and, and according to institute
State original sampling data storage initial position determine the cumulative of interpolation coefficient and original sampling data product and；
Under the 4th state, using the divider according to the interpolation coefficient it is cumulative and and the interpolation coefficient adopt with original
Sample data product cumulative and, determine destination sample data.
10. data processing method as claimed in claim 9, it is characterised in that: in a third condition, using one or more multiplication
Device divides according to the alternate position spike between ptototype filter coefficient, interpolation coefficient and the ptototype filter coefficient in ptototype filter table
When complete Lagrange's interpolation algorithm in multiplying.
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