CN212367589U - Self-adaptive data decoding circuit and LED unit circuit - Google Patents
Self-adaptive data decoding circuit and LED unit circuit Download PDFInfo
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- CN212367589U CN212367589U CN202021839312.9U CN202021839312U CN212367589U CN 212367589 U CN212367589 U CN 212367589U CN 202021839312 U CN202021839312 U CN 202021839312U CN 212367589 U CN212367589 U CN 212367589U
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Abstract
The utility model relates to a LED circuit technical field specifically discloses a self-adaptation data decoding circuit, wherein, include: the device comprises a signal edge detection processing circuit, a reset code detection circuit, a reference code decoding circuit and a data packet decoding circuit; the signal edge detection processing circuit is used for outputting a mark signal when a rising edge or a falling edge of a data code is detected, wherein each frame of data comprises a reset code, a reference code and a data packet which are sequentially connected, the data packet comprises a plurality of data codes, the length of the reference code is N times of the length of one data code in the data packet, and N is a natural number greater than 1; the reset code detection circuit is used for generating a reset signal; the reference code decoding circuit is used for decoding the reference code in each frame of data to obtain a reference code decoding result; the data code decoding circuit is used for decoding the data packet. The utility model also discloses a LED unit circuit. The utility model provides a self-adaptation data decoding circuit can realize that self-adaptation data decode.
Description
Technical Field
The utility model relates to a LED circuit technical field especially relates to a self-adaptation data decoding circuit and including this self-adaptation data decoding circuit's LED unit circuit.
Background
At present, LEDs are widely applied in many fields such as decoration, illumination, advertisement, stage lighting and the like. Generally, LEDs require a special integrated circuit for driving control, i.e., LED driving circuits. In the following description, the combination of an LED and its corresponding driver circuit is referred to as an LED unit. In practical application, a plurality of LED units are generally connected in parallel or in series to form a larger LED project. In order to make each LED unit work as required, it is necessary to send corresponding data to each LED unit through the controller. In the parallel application project, the general method is to set an address for each LED unit, and each LED unit receives corresponding data sent from the master controller according to the address of the LED unit.
The main controller sends data according to an agreed data format, and the LED unit can receive corresponding data according to the address of the LED unit. The data transmission rate is generally agreed when the product is designed, and is a fixed data transmission rate. The advantage of the fixed data transmission rate is that the data decoding at the receiving end of the LED unit is simple, but the disadvantage of the fixed data transmission rate is also obvious, and there are the following points:
firstly, a plurality of LED units are connected to form a system, if a relatively long connecting line occurs when the LED units are connected, or a plurality of LED units are used in the same system, for the driving output port of the main controller, the load is relatively large, the distortion of data sent to each LED unit is relatively large, and finally the probability of decoding failure of the LED units is increased, and the LED units cannot normally operate under severe conditions.
Secondly, the decoding problem of the LED unit is that the data transmission rate is fixed, which requires the decoding of the data by the LED unit to be performed according to the fixed rate, and the LED unit generally has a clock with a fixed frequency for decoding the received data, but the internal clock frequency is dependent on the application conditions, such as voltage change, temperature change, etc., and causes the internal clock of the LED unit to change. In addition, in the integrated circuit processing link, process deviations can also cause clock frequency deviations. Because the clock frequency deviation causes the probability of failure of the LED unit in decoding the data from the main controller to be greatly increased, the requirements on product design and production process are higher in order to ensure that the LED unit can decode smoothly.
In addition, in practical applications, the fixed data transmission rate is difficult to satisfy different application occasions, for example, sometimes, there are few LED units in engineering, but customers need a higher data transmission rate to improve the refresh rate, and in such a case, the fixed data transmission rate cannot be realized.
Disclosure of Invention
The utility model provides a self-adaptation data decoding circuit reaches LED unit circuit including this self-adaptation data decoding circuit, the fixed time of the data transmission rate who exists in the solution correlation technique decodes the technology that must lead to according to fixed rate and the higher problem of production requirement.
As a first aspect of the present invention, there is provided an adaptive data decoding circuit, including: the device comprises a signal edge detection processing circuit, a reset code detection circuit, a reference code decoding circuit and a data packet decoding circuit, wherein the output end of the signal edge detection processing circuit and the output end of the reset code detection circuit are connected with the input end of the reference code decoding circuit, and the output end of the reference code decoding circuit is connected with the data packet decoding circuit;
the signal edge detection processing circuit is used for detecting the rising edge or the falling edge of a data code in each frame of data and outputting a mark signal when the rising edge or the falling edge of the data code is detected, wherein each frame of data comprises a reset code, a reference code and a data packet which are sequentially connected, the data packet comprises a plurality of data codes, the length of the reference code is N times of the length of one data code in the data packet, and N is a natural number greater than 1;
the reset code detection circuit is used for generating a reset signal after the reset code in each frame of data is identified;
the reference code decoding circuit is used for decoding a reference code in each frame of data according to the mark signal and the reset signal to obtain a reference code decoding result;
and the data code decoding circuit is used for generating the decoding rate of a data packet according to the reference code decoding result and decoding the data packet according to the decoding rate of the data code.
Further, the adaptive data decoding circuit comprises a first clock signal, and the input end of the signal edge detection processing circuit and the input end of the reference code decoding circuit both input the first clock signal.
Furthermore, the adaptive data decoding circuit includes a counter circuit and a data comparator circuit, an output terminal of the reference code decoding circuit is connected to a first input terminal of the data comparator circuit, an output terminal of the counter circuit is connected to a second input terminal of the data comparator circuit, an output terminal of the data comparator circuit is connected to the data packet decoding circuit, the counter circuit is configured to input an enable signal and a first clock signal and output a counter result, the data comparator circuit is configured to generate a second clock signal according to the counter result and the reference code decoding result, and the second clock signal is configured to be input to the data packet decoding circuit.
Furthermore, the adaptive data decoding circuit comprises an RS flip-flop, an R end of the RS flip-flop is connected to the second clock signal, an S end of the RS flip-flop is connected to the flag signal, an output end Q of the RS flip-flop is connected to an enable signal end of the counter circuit, and the RS flip-flop is configured to output the enable signal according to the flag signal and the second clock signal.
Furthermore, the adaptive data decoding circuit includes a D flip-flop, a D end of the D flip-flop is connected to the output end of the data comparator circuit, a clock signal end of the D flip-flop is connected to the first clock signal, and an output end Q of the D flip-flop outputs a second clock signal.
Further, the length of the reference code is 8 times the length of one data code in the data packet.
As another aspect of the present invention, there is provided an LED unit circuit, wherein, including: the controller can send multi-frame data to each LED unit, and the adaptive data decoding circuit in each LED unit can decode each received frame data according to a corresponding decoding rate.
Further, each LED unit is connected with the controller through a data line.
Further, each LED unit and the controller are in communication connection through a power line carrier.
The embodiment of the utility model provides a self-adaptation data decoding circuit, because all set up the reference code in every frame data, and the length of reference code can be self-defined, and the length of reference code is proportional to the setting of the length of a data code in with the data packet, when the LED unit received data, at first decode the reference code, the decoding rate of data packet can be confirmed according to the length of reference code, can decode for the data packet according to corresponding rate and prepare in advance like this, thereby can realize self-adaptation data and decode, no longer receive the influence of making the best of transmission rate.
Drawings
The accompanying drawings, which are included to provide a further understanding of the invention and are incorporated in and constitute a part of this specification, illustrate embodiments of the invention and together with the description serve to explain the principles of the invention and not to limit the invention.
Fig. 1 is a specific embodiment of an LED unit circuit provided by the present invention.
Fig. 2 is another specific embodiment of the LED unit circuit provided by the present invention.
Fig. 3 is a block diagram of the adaptive data decoding circuit provided by the present invention.
Fig. 4 is a schematic diagram of a frame data structure provided by the present invention.
Fig. 5 is a schematic diagram of data waveforms in the reset code, the reference code and the data packet in one frame of data.
Fig. 6 is a schematic diagram of a specific circuit structure of the adaptive data decoding circuit provided by the present invention.
Fig. 7 is a timing diagram of decoding waveforms of the data 1 code and the data 0 code provided by the present invention.
Fig. 8 is a schematic diagram of a frame of data according to an embodiment of the present invention.
Fig. 9 is a schematic circuit diagram of a reference code decoding circuit provided by the present invention.
Fig. 10 is a schematic circuit diagram of a signal edge detection processing circuit according to the present invention.
Detailed Description
It should be noted that the embodiments and features of the embodiments of the present invention may be combined with each other without conflict. The present invention will be described in detail below with reference to the accompanying drawings in conjunction with embodiments.
In order to make the technical solution of the present invention better understood, the technical solution of the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings in the embodiments of the present invention, and it is obvious that the described embodiments are only some embodiments of the present invention, not all embodiments. Based on the embodiments in the present invention, all other embodiments obtained by a person skilled in the art without creative efforts shall belong to the protection scope of the present invention.
It should be noted that the terms "first," "second," and the like in the description and claims of the present invention and in the drawings described above are used for distinguishing between similar elements and not necessarily for describing a particular sequential or chronological order. It is to be understood that the data so used may be interchanged under appropriate circumstances for purposes of describing the embodiments of the invention herein. Furthermore, the terms "comprises," "comprising," and "having," and any variations thereof, are intended to cover a non-exclusive inclusion, such that a process, method, system, article, or apparatus that comprises a list of steps or elements is not necessarily limited to those steps or elements expressly listed, but may include other steps or elements not expressly listed or inherent to such process, method, article, or apparatus.
In order to solve the problem that the LED unit that exists among the prior art must decode according to fixed rate, the embodiment of the utility model provides a LED unit circuit, as shown in fig. 1 and fig. 2, including controller and a plurality of LED unit, every LED unit all with controller communication connection, and every LED unit all includes the adaptive data decoding circuit, the controller can send multiframe data to every LED unit, and the adaptive data decoding circuit in every LED unit all can decode each frame data of receiving according to the decoding rate that corresponds.
It should be understood that the embodiment of the present invention provides an adaptive data decoding circuit, which can set as required within a certain range, and can enable each LED unit to successfully and accurately complete data decoding without decoding at a fixed rate.
As shown in fig. 1, each LED unit is connected to the controller through a data line.
As shown in fig. 2, each LED unit is communicatively coupled to the controller via a power line carrier.
It will be appreciated that each LED unit and the controller may be arranged for data transmission via a power line carrier.
It should be understood that the controller may include an MCU, etc., and may be selected according to the requirement, which is not limited herein.
It should be noted that all the LED units connected to the main controller can receive all the data at the same time, and each LED unit decodes the data sent from the main controller and receives the data according to its address. The master controller transmits data in units of frames.
An adaptive data decoding circuit that enables adaptive rate decoding for each LED unit is described in detail below.
Fig. 3 is a block diagram of an adaptive data decoding circuit according to an embodiment of the present invention, as shown in fig. 3, including: the circuit comprises a signal edge detection processing circuit 100, a reset code detection circuit 200, a reference code decoding circuit 300 and a data packet decoding circuit 400, wherein the output end of the signal edge detection processing circuit 100 and the output end of the reset code detection circuit 200 are both connected with the input end of the reference code decoding circuit 300, and the output end of the reference code decoding circuit 300 is connected with the data packet decoding circuit 400;
the signal edge detection processing circuit 100 is configured to detect a rising edge or a falling edge of a data code in each frame of data, and output a flag signal when the rising edge or the falling edge of the data code is detected, where each frame of data includes a reset code, a reference code, and a data packet that are sequentially connected, the data packet includes a plurality of data codes, the length of the reference code is N times the length of one data code in the data packet, and N is a natural number greater than 1;
the reset code detection circuit 200 is configured to generate a reset signal after identifying a reset code in each frame of data;
the reference code decoding circuit 300 is configured to decode a reference code in each frame of data according to the flag signal and the reset signal to obtain a reference code decoding result;
the data code decoding circuit 400 is configured to generate a decoding rate of a data packet according to the reference code decoding result, and decode the data packet according to the decoding rate of the data code.
It should be noted that, in the embodiment of the present invention, a frame of data specifically means that a frame of data starts with a reset code, followed by a reference code, followed by a data packet. A schematic diagram of a frame data timing waveform is shown in fig. 4.
For the data frame structure who adopts fixed frequency transmission data, the utility model provides a self-adaptation data decoding circuit's data frame structure has increased the reference code, can accept sending end data code length and select at will in certain extent, and for the LED unit that can only accept fixed data code length, the range of application is wider, and is stronger to application environment adaptability. Since the transmitting end can change the data code length freely within the required range, in practical engineering, the transmitting rate can be changed as required to obtain more excellent effects, for example, the data transmitting rate can be increased to increase the display frame rate of the LED unit, and the transmitting rate can be decreased to enable normal operation under the condition of a particularly large number of points.
Since the data is transmitted by a single line, the decoding of the data is performed by judging the signal level change and the duration of the high and low levels. All data codes are connected by taking the falling edge of the signal as the start of all data codes, and then taking the falling edge as the end of the current data code and the start of the next data code. The data frames are connected with each other through reset codes. Here, all data codes are started according to the falling edge, and the rising edge can also be used as the start of the data codes as long as the design specification of the LED unit corresponds to the specification of the data sent by the master controller. The above-mentioned data code is a general term for the reference code and each bit of data in the data packet.
The components of a frame of data are described in detail below. The description here follows with the falling edge of the signal starting as a data code.
And the reset code defines that the continuous high level of the data signal exceeds a certain length as the reset code. The reset code has two functions, the first function is to determine that a frame of new data starts to be sent, and for the LED unit circuit, when the reset code is detected, preparation for receiving the new data is needed, namely, the decoding work of the reference code and the data packet is started at any time; the second function is to validate the previous frame data, that is, the LED unit circuit only temporarily stores the data when decoding the data packet and receiving the data packet belonging to the LED unit circuit, and the LED unit circuit waits until the next reset code is loaded into its working register for use.
And a reference code, wherein the first data code after the reset code is defined as the reference code. The reference code functions to determine the data transmission rate. The length of the reference code is N times the length of one data code in the data packet.
And the data packet defines that the sum of all data codes after the reference code is the data packet. There are two types of data codes: a data 1 code and a data 0 code.
The reference code and the data packet are both data signalsThe falling edge starts, continues at the low level for a predetermined time, then changes to the high level, and ends after keeping the predetermined time. The waveforms of the reset code, reference code and data packet are shown in FIG. 5, TDIs the high level time length of the data 1 code, and the high and low level lengths of all code patterns are referenced to TDTo be defined. In general, the length T of the reset coderesetWhich may be defined as hundreds of microseconds to milliseconds. T isDThe high level time length is not longer than the reset code, regardless of the reference code or the data code.
Table 1 definition table of reset code, reference code and data packet in frame data
Note that T isDThe high level time length of the data 1 code is shown, and the high level length and the low level length of all code patterns are referenced to TDTo be defined. The length of the reference code is N times the length of one data code in the data packet, and N is more than or equal to 2.
When transmitting data, the transmitting end may transmit the data in units of frames. The reset code, the reference code and the data codes in all the data packets in a frame of data are sent out continuously, if necessary, a certain high level idle time can be added between the codes, but the high level idle time is ensured not to be more than TresetOtherwise, it may be mistaken by the circuit as a reset code. The idle time between frames can be connected by high level, and there is no time requirement.
After a frame data structure is determined, a specific implementation process of transmitting data to an adaptive data decoding circuit for decoding is described below, where data transmission refers to that a transmitting end transmits data as required under an agreed specification, and a receiving end decodes input data to obtain correct data. The receiving end is referred to as an LED unit in the present invention. The process of accurately obtaining the data belonging to the LED unit from the data sent by the sending end is called adaptive decoding, the circuit for completing the adaptive decoding is called an adaptive decoding circuit, and the schematic diagram of the principle of the adaptive decoding circuit is shown in fig. 6. The LED unit circuit includes other module circuits except the adaptive decoding circuit, which are not described here, and the present invention only introduces the adaptive decoding circuit.
In the following description, DI represents a data signal; CK1 is the clock signal of the LED unit circuit; the DO is data obtained after the decoding circuit completes decoding, and is generally 8-bit or multi-bit data processed to be convenient for subsequent circuits; a 1 represents a logic high level and a 0 represents a logic low level.
The signal edge detection processing circuit 100 is responsible for detecting the falling edge of the DI signal, and outputs a flag signal DIPL for other module circuits when the DI signal falls, wherein the DIPL signal is a positive pulse.
It should be understood that the adaptive data decoding circuit includes a first clock signal CK1, and the input terminal of the signal edge detection processing circuit 100 and the input terminal of the reference code decoding circuit 300 both input the first clock signal CK 1.
The reset code detection circuit 200 generates a reset signal reset after successfully detecting the reset code, and the reset signal reset is a positive pulse. After receiving the reset signal, the reference code decoding circuit 300 first sets the output ED signal to 0, and then prepares to calculate the length of the reference code, where the interval time between the first two falling edges of DI after the reset signal is the length of the reference code, and the length of the reference code is calculated by counting the first clock signal CK 1. After the reference code decoding circuit calculates the length of the reference code, the length is divided by 2N and then stored as Q, the Q is output from an output end of the Q in real time to be used by other related circuits, and meanwhile, an output signal ED is set to be 1 for other circuits to use. At this point, the reference code decoding is completed, and the reference code decoding circuit stops working until the next reset signal works again according to the above-mentioned flow.
Specifically, as shown in fig. 6, the adaptive data decoding circuit includes a counter circuit 500 and a data comparator circuit 600, an output terminal of the reference code decoding circuit 300 is connected to a first input terminal of the data comparator circuit 600, an output terminal of the counter circuit 500 is connected to a second input terminal of the data comparator circuit 600, an output terminal of the data comparator circuit 600 is connected to the data packet decoding circuit 400, the counter circuit 500 is configured to input an enable signal and a first clock signal and output a counter result, the data comparator circuit 600 is configured to generate a second clock signal CK2 according to the counter result and the reference code decoding result, and the second clock signal CK2 is configured to be input to the data packet decoding circuit 400.
Further specifically, as shown in fig. 6, the adaptive data decoding circuit includes an RS flip-flop 700, an R end of the RS flip-flop 700 is connected to the second clock signal, an S end of the RS flip-flop 700 is connected to the flag signal, an output end Q of the RS flip-flop 700 is connected to an enable signal end of the counter circuit, and the RS flip-flop 700 is configured to output the enable signal according to the flag signal and the second clock signal.
More specifically, as shown in fig. 6, the adaptive data decoding circuit includes a D flip-flop 800, a D terminal of the D flip-flop 800 is connected to the output terminal of the data comparator circuit 600, a clock signal terminal of the D flip-flop 800 is connected to the first clock signal, and an output terminal Q of the D flip-flop 800 outputs a second clock signal CK 2.
Specifically, the ED signal is set to 1 after the reference code decoding is completed, and other related circuits start the packet decoding when the ED signal is equal to 1. The flag signal DIPL from the signal edge detection processing circuit 100 indicates the start of a data code, and the flag signal DIPL causes the output terminal Q of the RS flip-flop 700 to output 1, and the output terminal Q of the RS flip-flop 700 is connected to the input terminal EN of the counter circuit 500, and when the input terminal EN of the counter circuit 500 becomes 1, its internal counter starts to operate, that is, counts with the clock CK1, and outputs the result Q of the counter in real time. The input terminal a and the input terminal B of the data comparator circuit 600 are connected to the output Q of the reference code decoding circuit 300 and the output Q of the counter circuit 500, respectively. When the inputs a and B of the data comparator circuit 600 are equal, its output terminal Y outputs 1. The input terminal D of the D flip-flop 800 is connected to the output terminal Y of the data comparator circuit 600, and when the input terminal D of the D flip-flop 800 becomes 1, the output terminal Q thereof outputs 1 by the clock CK thereof. The output Q of the D flip-flop 800 outputs the second clock signal CK 2. The second clock signal CK2 is connected to the input port R of the RS flip-flop 700 and also connected to the clock terminal CK of the data decoding circuit 400. When the second clock signal CK2 becomes 1, the output Q of the RS flip-flop 700 is set to 0, so that the counter circuit 500 stops operating, and the output Q thereof is set to 0, so that the output Y of the data comparator circuit 600 accordingly becomes 0, and finally the second clock signal CK2 becomes 0 again.
As can be seen from the above-described operation of the related circuit, a pulse signal CK2 is generated from the beginning of the DI falling edge to a certain time point. Specific timing waveforms refer to fig. 7.
Suppose that the length of one data code in a data packet is TLThe length of the reference code is N x TLAfter each data code is processed by the above-mentioned circuit, it will be 1/2TLThe time point generates the second clock signal CK 2. If the lengths of the high and low levels of the data 1 code and the data 0 code are properly defined and the data DI is stored while being clocked by the second clock signal CK2, the data 1 code and the data 0 code can respectively obtain corresponding values of 1 and 0. This completes the decoding of the one-bit data code.
And all data in the data packet are decoded in sequence according to the method, and other related circuits of the LED unit obtain own data according to the specific definition of the data packet in the data frame and the address of the LED unit.
As can be seen from the above data decoding process, within a certain range, regardless of the data code length TLWhat is, as long as satisfy the length of reference code and be the data code length N times's in the data packet relation, adopt the embodiment of the utility model provides a self-adaptation data decoding circuit, LED unit can both correctly distinguish data 1 sign indicating number and data 0 sign indicating number. T isLDifferent lengths represent different data transmission rates. That is, the rate at which the controller sends data need not be fixed to a certain value, but rather set to a certain range, the LED units can decode and acquire the data correctly.
When an actual product is designed, according to specific application, an N value is properly selected, the range of the data code length TL is estimated, and a hardware circuit meeting the N value and the TL range is designed, so that self-adaptive data transmission can be realized.
The embodiment of the utility model provides a LED unit have 4 ways outputs. Each output is controlled by 8-bit data to control the output duty ratio. Data is sent by main control unit, and each LED unit decodes and obtains the data that belong to oneself according to self address, and data transmission between main control unit and each LED unit just adopts the embodiment of the utility model provides a self-adaptation data decoding circuit.
The plurality of LED units are used in parallel, the hardware connection is as shown in figures 1 and 2, and each LED unit decodes own data from the data sent by the main controller according to own address. The LED unit first converts the data loaded on the power line (VDD) into a standard digital signal DI, and this part of the operation is performed by a special circuit, which is not described in detail herein. In the following description, the data refers to DI.
The operation of the adaptive data decoding circuit provided by the present invention is described in detail with a specific embodiment.
The embodiment of the present invention provides a data frame definition as shown in fig. 8.
A high level lasting more than 120us (us is a time unit: microseconds, the same applies hereinafter) is a reset code.
Preferably, in the embodiment of the present invention, the length of the reference code is 8 times the length of one data code in the data packet.
The multiple N of the reference code length and one data code length is 8.
One data code length TL ranges from 3us to 30 us. The high and low level lengths of the data code satisfy the requirements shown in fig. 5 and table 1.
The data packet includes command bytes CMD and data D0-Dn. All the LED unit circuits receive a command byte CMD; the data D0-Dn are data for controlling 4-way output of the LED unit circuit corresponding to the addresses 0-n, and the LED unit circuit receives the corresponding data according to the address.
The embodiment of the utility model provides an adaptive data decoding principle is as shown in FIG. 6, and a clock signal CK1 frequency design for decoding circuit is 10MHz, and its cycle is 0.1 us. It is known from the data frame definition that the reference code has a maximum length of 240us, so the counter for detecting the length of the reference code in the reference code decoding circuit 300 is designed to be 12 bits, and the division of the 12-bit counter result by 2N is the output Q of the reference code decoding circuit, because N is 8, Q is the division of the 12-bit counter by 16, and thus Q is 8 bits of data. The range that the counter circuit 500 needs to be able to measure in actual operation is half of the data code, i.e. 1.5us to 15us, and is designed as an 8-bit counter, and the maximum measurable range is 0.1us × 256 ═ 25.6us, which completely meets the requirements of the present embodiment. The data comparator circuit 600 is therefore also designed for 8 bits.
The signal edge detection processing circuit 100 operates in real time and generates a DIPL signal for other circuits when the DI signal falls, as shown in FIG. 7.
It should be noted that, as shown in fig. 10, a schematic circuit diagram of an embodiment of the signal edge detection processing circuit 100 is specifically composed of three D flip-flops, a not gate, an and gate, and a nor gate. It should be understood that the circuit structure shown in fig. 10 is merely an example, and the signal edge detection processing circuit 100 in the embodiment of the present invention is not limited to the structure of fig. 10.
The reset code detection circuit 200 recognizes the reset code and then generates a reset signal reset, and knows that the reference code is generated after the reset according to the definition of the data frame, and the reset enables the reference code decoding circuit 300 to enter a working state, firstly, the output ED is set to 0, then, under the action of the DIPL signal, the calculation of the length of the reference code is completed, the final output result Q is obtained, and meanwhile, the output signal ED is set to 1. The specific working process is as follows, the first DIPL signal after the reset signal represents the start of the reference code, at this time, the counter inside the reference code decoding circuit starts to work, namely, CK1 is used as a clock for counting, when the next DIPL signal appears, the reference code represents the end, at this time, the circuit needs to do the following two works, the first is to pause the work of the counter, divide the result by 16 and then store the result in the output register Q and output the result in real time; the second is to set the circuit output signal ED to 1. The reference code decoding is finished, and the above operation is repeated again when the next frame data comes.
And after the reference code is decoded, the data code decoding work is carried out. The data code decoding process is as follows: when the ED signal is 1, all the data code decoding related circuits start to operate, the data code starts at the DI falling edge, a DIPL signal is generated, the DIPL signal sets the output Q of the RS flip-flop 700 to 1, when the input end EN of the counter circuit 500 receives that the output Q of the RS flip-flop 700 becomes 1, the operation is started, that is, the counter result Q is output in real time by taking the clock signal CK thereof as a clock, when the counting result Q is equal to the output Q of the reference code decoding circuit 300, the output Y of the data comparator circuit 600 becomes 1, the output Y of the data comparator circuit 600 is connected with the input end D of the D flip-flop 800, and when the D flip-flop 800 detects that the input D becomes 1, the output Q thereof is changed to 1 by the first clock signal CK 1. The output Q of the D flip-flop 800 drives the second clock signal CK 2. When the second clock signal CK2 changes to 1, it acts on the RS flip-flop 700 and changes its output Q to 0, and when the EN terminal of the counter circuit 500 changes to 0, it changes its output Q to 0, and after passing through the data comparator circuit 600 and the D flip-flop 800, the second clock signal CK2 changes to 0 again by the first clock signal CK 1. The result of the above process is that the second clock signal CK2 is generated at half the data code length, and the timing waveform thereof is shown in fig. 7. The data decoding circuit 400 stores and outputs DI data to the DO signal for use by other module circuits, clocked by the second clock signal CK2, until decoding of one-bit data codes is completed.
As shown in fig. 9, which is a schematic circuit diagram of the reference code decoding circuit 300 according to the embodiment of the present invention, the circuit is specifically composed of three RS flip-flops, nand gates, or gates and a counter 310, wherein the upper 8 bits Q [11:4] represent the output Q of the reference code decoding circuit 300.
It should be noted that the schematic diagrams of the specific implementation circuits of the reset code detection circuit 200, the packet decoding circuit 400, the counter circuit 500 and the data comparator circuit 600 are well known to those skilled in the art and will not be described herein.
The LED unit circuit will decode all data codes in turn in the manner described above.
The other module circuits of the LED units use the second clock signal CK2 and the DO data signal to use the data in groups of 8 bits, the first 8 bits in one frame of data are the command byte CMD, and all the LED units receive the CMD byte. And then receiving data belonging to the LED unit according to the CMD requirement and the current circuit address of the LED unit and storing the data for standby. And when the next reset code flag signal reset is received, the received data is acted on the output module, so that the task of controlling 4 paths of output of each LED unit circuit by sending data by the main controller is completed.
From the aspect of the adaptive decoding process of the embodiment, as long as the requirements that the reset code is greater than 120us, the data code length is 3 us-30 us, and the reference code length is 8 times of the data code are met for one frame of data sent by the main controller, the LED unit circuit can normally decode to obtain the instruction and the data.
To sum up, the utility model provides a self-adaptation data decoding circuit and LED unit circuit can accept sending end data code length and select at will in certain extent, for the LED unit that can only accept fixed data code length, and the range of application is wider, and is stronger to application environment adaptability. Since the transmitting end can change the data code length freely within the required range, in practical engineering, the transmitting rate can be changed as required to obtain more excellent effects, for example, the data transmitting rate can be increased to increase the display frame rate of the LED unit, and the transmitting rate can be decreased to enable normal operation under the condition of a particularly large number of points.
It is to be understood that the above embodiments are merely exemplary embodiments that have been employed to illustrate the principles of the present invention, and that the present invention is not limited thereto. It will be apparent to those skilled in the art that various modifications and improvements can be made without departing from the spirit and substance of the invention, and these modifications and improvements are also considered to be within the scope of the invention.
Claims (9)
1. An adaptive data decoding circuit, comprising: the device comprises a signal edge detection processing circuit, a reset code detection circuit, a reference code decoding circuit and a data packet decoding circuit, wherein the output end of the signal edge detection processing circuit and the output end of the reset code detection circuit are connected with the input end of the reference code decoding circuit, and the output end of the reference code decoding circuit is connected with the data packet decoding circuit;
the signal edge detection processing circuit is used for detecting the rising edge or the falling edge of a data code in each frame of data and outputting a mark signal when the rising edge or the falling edge of the data code is detected, wherein each frame of data comprises a reset code, a reference code and a data packet which are sequentially connected, the data packet comprises a plurality of data codes, the length of the reference code is N times of the length of one data code in the data packet, and N is a natural number greater than 1;
the reset code detection circuit is used for generating a reset signal after the reset code in each frame of data is identified;
the reference code decoding circuit is used for decoding a reference code in each frame of data according to the mark signal and the reset signal to obtain a reference code decoding result;
and the data code decoding circuit is used for generating the decoding rate of a data packet according to the reference code decoding result and decoding the data packet according to the decoding rate of the data code.
2. The adaptive data decoding circuit according to claim 1, wherein the adaptive data decoding circuit includes a first clock signal, and the input terminal of the signal edge detection processing circuit and the input terminal of the reference code decoding circuit each input the first clock signal.
3. The adaptive data decoding circuit of claim 2, wherein the adaptive data decoding circuit comprises a counter circuit and a data comparator circuit, an output of the reference code decoding circuit is connected to a first input of the data comparator circuit, an output of the counter circuit is connected to a second input of the data comparator circuit, an output of the data comparator circuit is connected to the data packet decoding circuit, the counter circuit is configured to input an enable signal and a first clock signal and output a counter result, and the data comparator circuit is configured to generate a second clock signal according to the counter result and the reference code decoding result, and the second clock signal is configured to be input to the data packet decoding circuit.
4. The adaptive data decoding circuit of claim 3, wherein the adaptive data decoding circuit comprises an RS flip-flop, an R terminal of the RS flip-flop is connected to the second clock signal, an S terminal of the RS flip-flop is connected to the flag signal, an output terminal Q of the RS flip-flop is connected to an enable signal terminal of the counter circuit, and the RS flip-flop is configured to output the enable signal according to the flag signal and the second clock signal.
5. The adaptive data decoding circuit of claim 3, wherein the adaptive data decoding circuit comprises a D flip-flop, a D terminal of the D flip-flop is connected to the output terminal of the data comparator circuit, a clock signal terminal of the D flip-flop is connected to the first clock signal, and an output terminal Q of the D flip-flop outputs a second clock signal.
6. The adaptive data decoding circuit of claim 1, wherein the reference code has a length that is 8 times a length of one data code in the data packet.
7. An LED unit circuit, comprising: a controller and a plurality of LED units, each LED unit being communicatively connected to the controller and each LED unit comprising the adaptive data decoding circuit of any one of claims 1 to 6, the controller being capable of sending a plurality of frames of data to each LED unit, the adaptive data decoding circuit in each LED unit being capable of decoding each frame of data received at a corresponding decoding rate.
8. The LED unit circuit of claim 7, wherein each LED unit is connected to the controller by a data line.
9. The LED unit circuit of claim 7, wherein each LED unit is communicatively coupled to the controller via a power line carrier.
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