CN111918454A - LED control chip for power line data transmission - Google Patents

LED control chip for power line data transmission Download PDF

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CN111918454A
CN111918454A CN201911163476.6A CN201911163476A CN111918454A CN 111918454 A CN111918454 A CN 111918454A CN 201911163476 A CN201911163476 A CN 201911163476A CN 111918454 A CN111918454 A CN 111918454A
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data
module
data frame
chip
luminance
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CN111918454B (en
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邹云根
陈孟邦
卢玉玲
张丹丹
乔世成
蔡荣怀
曹进伟
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Zongren Technology Pingtan Co ltd
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Abstract

The invention discloses an LED control chip for power line data transmission, which carries out data identification on the voltage of a composite power supply through a voltage detection module, wherein a decoding module samples a data signal to obtain carrier data, a data frame identification module counts the carrier data decoded on a power supply line, a logic control module is used for comparing an address in a chip address setting module with the data frame count, when the logic control module judges that the chip address matches the current data frame count value, luminance display data in the current data frame are captured and sent to a luminance generation module, the luminance generation module generates a luminance signal according to the luminance display data, and an output driving module drives a light emitting diode according to the luminance signal. The method and the device can automatically match the self address according to the sending sequence of the display data, reduce the data size of code sending in principle and improve the refreshing speed of the display frame. The transmitted data is reduced, the error rate of the chip receiving data is reduced, and the requirements of software and hardware of a control system are reduced, so that the cost of the product is saved, and the market competitiveness is improved.

Description

LED control chip for power line data transmission
Technical Field
The invention relates to the technical field of LED lighting, in particular to an LED control chip with a power line for transmitting data.
Background
At present, a plurality of power supply carrier LED control chips are applied to occasions such as a 3D lamp, a Christmas lamp and a curtain lamp on the market, compared with a four-wire transmission system in the prior art, the installation process is simplified, the cost of a cable is greatly saved, the failure rate of a product is reduced, and the trouble of maintenance is avoided. However, because the series of products adopt the power line to transmit data, the transmission rate cannot reach a high speed on the premise that the power line is greatly interfered by the product, and in the application occasion of screen display, the requirement on screen refreshing is high, which is also a main reason that the chip is not applied to the screen. When the chips are cascaded in parallel, a data frame containing a chip address must be sent to control the corresponding chip in the system, which also causes a large amount of data to be sent by one display frame, so that reducing the amount of data sent is an urgent problem to be solved. Aiming at the problem, when the data frame is sent, the method does not need to contain a chip address and an end code, and the end code exists only when the display frame is ended, so that the data sending amount is reduced fundamentally, the number of control chips can be increased, the cost of a product and a control system is reduced, the chips are suitable for application occasions with more and larger scenes, and the market competitiveness of the product is improved.
Disclosure of Invention
The invention aims to overcome the defects and provides the LED control chip with the power line for transmitting data.
In order to achieve the purpose, the technical solution of the invention is as follows: an LED control chip for transmitting data by a power line comprises an oscillator, a reference voltage, a voltage detection module, a logic control module, a decoding module, a carrier data module, a chip address setting module, a data frame identification module, a data frame counting setting module, a luminance generation module and an output driving module, wherein the oscillator is connected with the decoding module, the reference voltage is connected with the voltage detection module, the voltage detection module is respectively connected with a composite power supply voltage and the input end of the decoding module, the output end of the decoding module is connected with the input end of the carrier data module, the carrier data module is connected with the data frame identification module, the data frame identification module is connected with the data frame counting setting module, the carrier data module, the data frame counting setting module and the chip address setting module are connected with the input end of the logic control module, the output end of the logic control module is connected with the input end of the luminance generation module and the input end of the chip address setting module, the output end of the luminance generation module is connected with the input end of the output driving module, and the output of the output driving module is connected with an output pin;
the voltage detection module receives a composite power supply voltage, the composite power supply voltage comprises a power supply voltage and a data signal, the voltage detection module performs data identification at the composite power supply voltage according to a received reference voltage, the decoding module samples the data signal according to a received system clock, the carrier data module converts the voltage detection result into carrier data, the data frame identification module counts the carrier data decoded on a power supply line, the data frame count setting module counts data frames, the logic control module is used for comparing an address in the chip address setting module with the data frame count, and when the logic control module judges that the chip address matches a current data frame count value, luminance display data in a current data frame are captured and sent to the luminance generation module, the luminance generation module generates one or more luminance signals with different duty ratios according to the luminance display data, and the output driving module drives one or more light-emitting diodes according to the one or more luminance signals with different duty ratios.
Preferably, the reference voltage is used for providing a voltage which is not changed along with the power supply voltage and the temperature, and the value of the reference voltage is 1-1.5V.
Preferably, the internal address of the chip address setting module comprises one or more of a laser fuse, a metal fuse, a poly fuse, an otp and an mtp.
Preferably, the voltage detection module includes a resistor and a comparator, and after the composite power supply voltage is divided by the resistor, the composite power supply voltage is compared with the reference voltage by the comparator to extract the data signal.
Preferably, the chip address setting module sends a control signal through a power line to burn the polysilicon fuse so as to set a chip address, and the address is set to 8 bits.
Preferably, the initial value of the data frame counting module is set by a control system sending a control instruction.
Preferably, the data frame signal of the composite power supply voltage is represented by a combination of high voltage and low voltage with different durations, and the data frame signal on the power supply line includes a control code, first data, second data and third data.
Preferably, the control code includes two working mode selection bits, and when the working mode control code selection bit is 11, the data frame identification module counts the carrier data and counts the carrier data; and when the selection bit of the working mode control code is 01, the logic control module compares the address in the chip address setting module with the data frame count.
Preferably, the first data, the second data and the third data are respectively set to 8 bits, the 8-bit data information represents 0-255 different values, the different values correspond to different luminances of the LED lamp, when the value is 0, the luminance of the LED lamp is minimum, the lamp is off, and when the data is 255, the luminance of the LED lamp is maximum.
Preferably, the storage space of the control chip of the LED is larger than 256 chip addresses.
The invention does not need to send the chip address when sending the display data, and the chip automatically matches the self address according to the sending sequence of the display data, thereby reducing the data amount of code sending in principle and improving the refreshing speed of the display frame. The transmitted data are reduced, the error rate of the data received by the chip is correspondingly reduced, and the requirements of software and hardware of a control system are reduced, so that the cost of the product is saved, and the market competitiveness is improved.
Drawings
The accompanying drawings, which are included to provide a further understanding of the invention and are incorporated in and constitute a part of this specification, illustrate embodiments of the invention and together with the description serve to explain the invention and not to limit the invention. In the drawings:
FIG. 1 is a schematic diagram of a control circuit according to the present invention;
FIG. 2 is a schematic diagram of data control signals according to the present invention;
FIG. 3 is a circuit diagram of an application of the control chip of the present invention;
FIG. 4 is a diagram illustrating luminance data information according to the present invention;
fig. 5 is an exemplary circuit structure of a voltage detection module in an LED control chip according to an embodiment of the present invention;
fig. 6 is an exemplary circuit structure of a decoding module in an LED control chip according to an embodiment of the present invention;
fig. 7 is an exemplary circuit structure of a data frame identification module in an LED control chip according to an embodiment of the present invention;
fig. 8 is an exemplary circuit structure of a data frame count setting module in an LED control chip according to an embodiment of the present invention;
FIG. 9 is a diagram of a display frame format according to the present invention.
In the figure: 1-a reference voltage; 2-an oscillator; 3-a voltage detection module; 4-a decoding module; 5-carrier data module; 6-data frame identification module; 7-data frame setting counting module; 8-chip address setting module; 9-a logic control module; 10-a luminance generation module; 11-output driving module.
Detailed Description
In order to more clearly explain the overall concept of the present invention, the following detailed description is given by way of example in conjunction with the accompanying drawings.
It should be noted that in the following description, numerous specific details are set forth in order to provide a thorough understanding of the present invention, however, the present invention may be practiced in other ways than those specifically described herein, and thus the scope of the present invention is not limited by the specific embodiments disclosed below.
As shown in fig. 1-8, an LED control chip for transmitting data via a power line includes an oscillator 2, a reference voltage 1, a voltage detection module 3, a logic control module 9, a decoding module 4, a carrier data module 5, a chip address setting module 8, a data frame identification module 6, a data frame count setting module 7, a luminance generation module 10, and an output driver module 11, where the oscillator 2 is connected to the decoding module 4, the reference voltage 1 is connected to the voltage detection module 3, the voltage detection module 3 is respectively connected to a composite power voltage and an input end of the decoding module 4, an output end of the decoding module 4 is connected to an input end of the carrier data module 5, the carrier data module 5 is connected to the data frame identification module 6, and the data frame identification module 6 is connected to the data frame count setting module 7, the carrier data module 5, the data frame count setting module 7 and the chip address setting module 8 are connected to the input end of the logic control module 9, the output end of the logic control module 9 is connected to the input end of the luminance generating module 10 and the input end of the chip address setting module 8, the output end of the luminance generating module 10 is connected to the input end of the output driving module 11, and the output driving module 11 is connected to an output pin, namely an external LED driving end, and is configured to drive the LED module to operate according to the luminance signal.
The voltage detection module 3 receives a composite power supply voltage, the composite power supply voltage comprises a power supply voltage and a data signal, the voltage detection module 3 performs data identification at the composite power supply voltage according to a received reference voltage, the decoding module 4 samples the data signal according to a received system clock to obtain carrier data, the data frame identification module 5 performs statistics on the carrier data decoded on a power line, the logic control module 9 is used for comparing an address in the chip address setting module 8 with the data frame count, when the logic control module 9 judges that the chip address matches the current data frame count value, luminance display data in the current data frame is captured and sent to the luminance generation module 10, and the luminance generation module generates one or more luminance signals according to the luminance display data, the output driving module 11 drives one or more light emitting diodes according to the one or more luminance signals. The chip drives at least one path of LED module, and the chip and the LED module can be packaged together.
The reference voltage 1 provides a voltage which does not change with the power voltage and the temperature, the reference voltage is 1-1.5V, in this embodiment, the value of the reference voltage 1 is 1.2V, the voltage detection module 3 includes a resistor and a comparator, the composite power voltage is divided by the resistor and then compared with the reference voltage 1 by the comparator to extract a data signal, the oscillator 2 is used for generating an oscillation frequency signal, and the decoding module 4 converts the data signal into control chip address data and luminance data of each LED lamp by using the oscillation frequency signal; the chip address setting module 8 is provided with 8-bit addresses for setting and controlling chip address data, and the chip address setting module 8 sets the addresses of the chips through the connection and disconnection of the polysilicon fuses inside the chips.
As shown in fig. 2, the binary code 1 is represented by a combination of high level lasting more than 0.2us and low level lasting more than 10us, the binary code 0 is represented by a combination of low level lasting 5us and high level lasting more than 0.2us, and the low level lasting 20us and high level lasting more than 0.2us represent RESET, which indicates that the sending of the display frame is finished and all chips on the cascade system refresh the display. The format of the display frame is shown in fig. 9.
The format of the data frame signal is control code + first data + second data + third data, and in this embodiment, the control code has 2 bits in total and is a working mode selection bit. The first data, the second data, and the third data are respectively set to 8 bits and indicate different luminances of the LEDs. And sending frame end information when one display frame is ended, wherein the frame end information is represented in a set time range by the duration of low voltage.
When the selection bit of the working mode control code is 11, the control chip enters the working mode set by the data frame counting setting module 7, the data frame identification module 6 counts each bit of carrier data, and when a data frame is judged to be completed, the counter value of the data frame counting setting module 7 is increased by one; when the selection bit of the working mode control code is 01, the address of the control chip address setting module 8 is compared with the data frame count, when the RESET code is received after the display frame is finished, all the selected control chips in the system respectively output luminance signals with different duty ratios according to the first data, the second data and the third data in the control signals to drive the LED module to work, at least one path of LED module is driven by the chips, and the chips and the LED module can be packaged together.
The first data, the second data and the third data respectively represent brightness data information of the LED lamp, the brightness data information shows that as shown in figure 4, the control module firstly sends low bits and then sends high bits when sending data. The control code is sent first, and then the first data, the second data and the third data are sent in sequence from low to high. The luminance generating module 10 converts the data information in the data control signal into luminance signals with different duty ratios, 8-bit data information represents 0-255 different values corresponding to different luminances of the LED lamp, when the value is 0, the luminance of the LED lamp is minimum, the lamp is off, when the value is 255, the luminance of the LED lamp is maximum, and when the data is a certain middle value, for example, 128, the duty ratio output luminance with PWM output of 128/256 is represented. The memory space of the control chip of the LED is greater than 256 chip addresses to ensure that there is sufficient memory space.
The data frames in the present invention are represented as follows:
Figure RE-GDA0002424739560000071
wherein C1C0 represents a 2-bit operation mode selection bit, and when C1C0 is equal to 11, the control chip enters the operation mode set by the data frame count setting module 7; when C1C0 is 01, the logic control module 9 is configured to compare the address in the chip address setting module 8 with the data frame count, when the logic control module 9 determines that the chip address matches the current data frame count value, the luminance display data in the current data frame is captured and sent to the luminance generation module 10, the luminance generation module 10 generates one or more luminance signals according to the luminance display data, and the output driving module 11 drives one or more light emitting diodes according to the one or more luminance signals.
When the control system refreshes a picture once, only a plurality of data frames and an end code need to be sent, and compared with the traditional DMX512 data frame two-bit start code + 8-bit data + one-bit end code and the complex display frame protocol, the control system has the advantages that less data are sent and the protocol is simpler.
As shown in fig. 5, the voltage detection module 3: POR1 provides an initial state for the chip for a power-on reset signal. VREF is the reference voltage 1.2V provided by the reference voltage, and NBIAS is the current source provided by the reference voltage as the tail current of the comparator. The power supply voltage is divided by a resistor and then input to the N end of the comparator, and is compared with VREF at the P end of the comparator. When the power supply voltage is greater than 3V, the output of the comparator is 0, and DOUT is 1 after passing through the inverter; when the power supply voltage is less than 3V, the comparator output is 1, and after passing through the inverter, DOUT is 0. The decoding module identifies the DOUT output of the voltage detection module according to the time of the signal and stores decoding data in a mode of a shift register.
As shown in fig. 6, the decoding module 4: c1 and C0 correspond to I56_ Q, I52_ Q in the shift register, and MD3M is a matching signal of chip addresses D0-D8 and data frame counts ADC1-ADC 9. I52_ Q, I56_ Q enters a matching mode of chip address and data frame count when C1C0 is 01 through the operation of the XNOR gates I486 and I487. The output of I486, I487 is AND-ed with MD3M, resulting in PDMATCH as the output enable signal. After the chip receives the end code RESET and PDMATCH is 1, the logic control circuit outputs the first data, the second data and the third data in the instruction to the luminance generation module and updates the output of the output driving module; otherwise, the output display is not refreshed.
As shown in fig. 7, the data frame identification module 6 counts each bit of data of the carrier data, counts from the first bit of the carrier data, and adds one to the data frame count setting module when the carrier data is identified as a complete data frame (two-bit control code + first data + second data + third data), and at the same time, the data frame identification module is reset to prepare to identify a new data frame again.
X68_ Y is carrier data, a pulse represents a bit of data, after the chip is electrified and reset, the carrier data is counted by I187, I185, I186, I182, I188 and I238 data frame identification registers, when the counting value is 26 bits of a complete data frame, a reset signal CNTRST is generated by a system clock CLK to reset the data frame identification registers, the CNTRST signal carries out module carry on the data frame counting, and the next data frame is waited to arrive. The chip generates POR2 signal when power is on, and generates X604_ Y signal to clear the data frame identification register when the display frame is over, ensuring that each display frame can be accurately identified.
As shown in fig. 8, the data frame count setting module 7: the operation of I996 is to ensure that the carry signal of the data frame identification module is only valid when the chip operates in the matching mode of the chip address of C1C0 being 01 and the data frame count, and when the chip operates in this mode, the data frame count setting module normally counts the carry signal of the data frame identification module. When C1C0 is 11, the chip works in the data frame counting setting mode, the logic control module takes out the setting data W7-W0, red7 in the signal flow and enables MD2CLK, and the output signals ADC1-ADC9 of the data frame counters I329-I337 are set or reset according to the setting data. The ADDRESET is a signal combination of a reset signal generated by the chip when the chip is powered on and a data frame school register cleared by an X604_ Y signal generated when a display frame is ended, and the idle state is 1.
Taking the I330 settable reset register as an example, the set terminal and the reset terminal are both enabled at low level, ADDRESET idle state is 1, MD2CLK is enabled at 0, and inverted to 1, when W6 is 1, the inputs at both ends of the I356 nand gate are both 1, the output is 0, the set terminal enable of I330 is triggered, ADC2 is 1, and the output of I446 is 1, and the reset terminal outputs from 1 to I330 after and ADDRESET and operation are invalid. Similarly, when W6 is 0, I448 is 0, I356 is 1, the reset terminal of I330 is enabled, and ADC2 is 0.
The above description is only a preferred embodiment of the present invention, and should not be taken as limiting the scope of the invention, and all equivalent changes and modifications made in the claims of the present invention should be included in the scope of the present invention.

Claims (10)

1. An LED control chip for transmitting data by a power line comprises an oscillator and a reference voltage, and is characterized by further comprising a voltage detection module, a logic control module, a decoding module, a carrier data module, a chip address setting module, a data frame identification module, a data frame counting setting module, a luminance generation module and an output driving module, wherein the oscillator is connected with the decoding module, the reference voltage is connected with the voltage detection module, the voltage detection module is respectively connected with a composite power supply voltage and the input end of the decoding module, the output end of the decoding module is connected with the input end of the carrier data module, the carrier data module is connected with the data frame identification module, the data frame identification module is connected with the data frame counting setting module, the carrier data module, the data frame counting setting module, the output end of the output driving module and the output driving module, The chip address setting module is connected with the input end of the logic control module, the output end of the logic control module is connected with the input end of the luminance generation module and the input end of the chip address setting module, the output end of the luminance generation module is connected with the input end of the output driving module, and the output of the output driving module is connected with the output pin;
the voltage detection module receives a composite power supply voltage, the composite power supply voltage comprises a power supply voltage and a data signal, the voltage detection module performs data identification at the composite power supply voltage according to a received reference voltage, the decoding module samples the data signal according to a received system clock, the carrier data module converts the voltage detection result into carrier data, the data frame identification module counts the carrier data decoded on a power supply line, the logic control module is used for comparing an address in the chip address setting module with the data frame count, the data frame count setting module counts data frames, and when the logic control module judges that the chip address matches a current data frame count value, luminance display data in the current data frame are captured and sent to the luminance generation module, the luminance generation module generates one or more luminance signals with different duty ratios according to the luminance display data, and the output driving module drives one or more light-emitting diodes according to the one or more luminance signals with different duty ratios.
2. The LED control chip for power line data transmission according to claim 1, wherein the reference voltage is used to provide a voltage that is invariant to power supply voltage and temperature, and the reference voltage value is 1-1.5V.
3. The LED control chip for transmitting data through the power line as claimed in claim 1, wherein the internal address of the chip address setting module comprises one or more of laser fuse, metal fuse, poly fuse, otp and mtp.
4. The LED control chip of claim 1, wherein the voltage detection module comprises a resistor and a comparator, and the composite power voltage is divided by the resistor and then compared with the reference voltage by the comparator to extract the data signal.
5. The LED control chip for transmitting data through the power line as claimed in claim 1, wherein the chip address setting module is configured to set the chip address by sending a control signal through the power line to burn the polysilicon fuse, and the address is set to 8 bits.
6. The LED control chip for transmitting data through the power line as claimed in claim 1, wherein an initial value of the data frame counting module is set by a control system issuing a control command.
7. The LED control chip of claim 1, wherein the data frame signal of the composite power supply voltage is represented by a combination of high voltage and low voltage with different durations, and the data frame signal on the power supply line comprises a control code, a first data, a second data, and a third data.
8. The LED control chip for transmitting data through the power line according to claim 7, wherein the control code comprises two operation mode selection bits, when the operation mode control code selection bit is 11, the data frame identification module counts each bit of carrier data, and when a data frame is determined to be completed, the data frame counter value is incremented by one; and when the selection bit of the working mode control code is 01, the logic control module compares the address in the chip address setting module with the data frame count.
9. The LED control chip for transmitting data through the power line as claimed in claim 7, wherein the first data, the second data and the third data are respectively set to 8 bits, the 8-bit data information represents 0-255 different values, the different values correspond to different luminances of the LED lamp, when the value is 0, the luminance of the LED lamp is minimum, the lamp is off, and when the data is 255, the luminance of the LED lamp is maximum.
10. The LED control chip for transmitting data through the power line as claimed in claim 1, wherein the storage space of the control chip of the LED is larger than 256 chip addresses.
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