CN107507561A - A kind of LED control chips and LED information display system - Google Patents
A kind of LED control chips and LED information display system Download PDFInfo
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- CN107507561A CN107507561A CN201710888476.7A CN201710888476A CN107507561A CN 107507561 A CN107507561 A CN 107507561A CN 201710888476 A CN201710888476 A CN 201710888476A CN 107507561 A CN107507561 A CN 107507561A
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- G—PHYSICS
- G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
- G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
- G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
- G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
- G09G3/22—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources
- G09G3/30—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels
- G09G3/32—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED]
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- G—PHYSICS
- G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
- G09F—DISPLAYING; ADVERTISING; SIGNS; LABELS OR NAME-PLATES; SEALS
- G09F9/00—Indicating arrangements for variable information in which the information is built-up on a support by selection or combination of individual elements
- G09F9/30—Indicating arrangements for variable information in which the information is built-up on a support by selection or combination of individual elements in which the desired character or characters are formed by combining individual elements
- G09F9/33—Indicating arrangements for variable information in which the information is built-up on a support by selection or combination of individual elements in which the desired character or characters are formed by combining individual elements being semiconductor devices, e.g. diodes
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- General Physics & Mathematics (AREA)
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Abstract
The invention belongs to LED control fields,Disclose a kind of LED control chips and LED information display system,The data-signal is extracted in composite power source voltage according to reference voltage by voltage detection module,Decoder module is sampled to obtain carrier data according to system clock to data-signal,Carrier data includes control data,Address date,Luminance data,Then chip address matching module judges whether the chip address is consistent with the address date,If,Then address matching signal is sent to Logic control module,Logic control module judges mode of operation according to control data,If the mode of operation is drive pattern,Then Logic control module generates trigger signal so that briliancy generation module generates one or more luminance signal according to the luminance data according to address matching signal and drive pattern,Drive module drives one or more light emitting diode according to one or more of luminance signals,Realize a cable while power supply and transmission data are provided,Simplify chip design.
Description
Technical field
The invention belongs to LED control fields, more particularly to a kind of LED control chips and LED information display system.
Background technology
Nowadays businessman's picture is launched by display screen and video ads is very popular, started control chip and use clock mostly
Line and data wire realize LED color and brightness in control display screen to transmit data, slowly develop into only with one
Data wire transmits control.But clock line and data wire are used, or individually existed by the way of data line transfer data
The problem of be the cable needed length it is very long, the proportion that the cost of cable accounts for totle drilling cost is high, while assembles complexity and need manpower
It is more.Except needing power line, it is also necessary to a single data input line and a single data output line, at least want three lines or four lines, together
When chip chamber two transmission lines production when easy connection error, cause finished product there is no function, difficulty brought to product repairing.Cause
It is urgent problem to be solved that this, which reduces number of wires,.
The content of the invention
The invention provides a kind of LED control chips and LED information display system, it is intended to solves existing LED control chips cable root
The problem of number is excessive.
The present invention is achieved in that a kind of LED control chips, and the LED control chips include voltage detection module, solution
Code module, carrier data memory module, chip address matching module, chip address memory module, Logic control module, briliancy life
Into module and drive module；
The voltage detection module is connected with supply voltage and the decoder module respectively, the decoder module with it is described
The input connection of carrier data memory module, control data input and the carrier data of the Logic control module are deposited
Store up the control data output end of module, the address date input of the Logic control module and the carrier data memory module
Address date output end, the address of the address date output end of the Logic control module and the chip address matching module
Data input pin, the output end of the chip address memory module and the chip address input of the chip address matching module
Connection, the first output end of the Logic control module are connected with the control terminal of the briliancy generation module, the carrier data
The luminance data output end of memory module is connected with the data input pin of the briliancy generation module, the briliancy generation module
Data output end is connected with the drive module；
The voltage detection module receives composite power source voltage, the composite power source voltage include supply voltage sum it is believed that
Number, the voltage detection module extracts the data-signal according to the reference voltage received in the composite power source voltage,
The decoder module is sampled according to the system clock received to the data-signal to obtain carrier data, and by described in
Carrier data is stored in the carrier data memory module, and the carrier data includes control data, address date, briliancy number
According to this and terminate frame information, the address date is forwarded to the chip address matching module by the Logic control module, is controlled
Make the chip address matching module judge chip address in the chip address memory module whether with the address date
Unanimously, if so, then sending address matching signal to the Logic control module, the Logic control module is according to the carrier number
Judge mode of operation according to the control data in memory module, if the mode of operation is drive pattern, the logic control
Module generates trigger signal according to the address matching signal and the drive pattern, and the briliancy generation module is according to being triggered
The luminance data in carrier data memory module described in signal-obtaining simultaneously generates one or more according to the luminance data
Individual luminance signal, the drive module drive one or more light-emitting diodes according to one or more of luminance signals
Pipe.
The present invention also provides a kind of LED information display system, and the LED information display system includes above-mentioned LED control chips.
The embodiment of the present invention in composite power source voltage extracts data-signal by voltage detection module according to reference voltage,
Decoder module is sampled according to system clock to data-signal to obtain carrier data, carrier data include control data,
Location data, luminance data and terminate frame information, then chip address matching module judge chip address whether with address date one
Cause, if so, then sending address matching signal to Logic control module, Logic control module judges Working mould according to control data
Formula, if mode of operation is drive pattern, Logic control module generates trigger signal according to address matching signal and drive pattern
So that briliancy generation module generates one or more luminance signal according to the luminance data, drive module according to one or
Multiple luminance signals drive one or more light emitting diode, realize a cable while provide power supply and transmission data,
Avoid because cable radical excessively causes cost higher and the problem of easy connection error, simplifies chip design, adds production
The market competitiveness of product.
Brief description of the drawings
Technological invention in order to illustrate the embodiments of the present invention more clearly, make required in being described below to embodiment
Accompanying drawing is briefly described, it should be apparent that, drawings in the following description are only some embodiments of the present invention, for
For those of ordinary skill in the art, on the premise of not paying creative work, other can also be obtained according to these accompanying drawings
Accompanying drawing.
Fig. 1 is a kind of circuit structure diagram of LED control chips provided in an embodiment of the present invention；
Fig. 2 is another circuit structure diagram of LED control chips provided in an embodiment of the present invention；
Fig. 3 is another circuit structure diagram of LED control chips provided in an embodiment of the present invention；
Fig. 4 is the exemplary circuit structure chart of the voltage detection module in LED control chips provided in an embodiment of the present invention；
Fig. 5 is the exemplary circuit structure of the chip address memory module in LED control chips provided in an embodiment of the present invention
Figure；
Fig. 6 is the chip address matching module and Logic control module in LED control chips provided in an embodiment of the present invention
Exemplary circuit structure chart.
Embodiment
To make the object, technical solutions and advantages of the present invention clearer, below in conjunction with accompanying drawing to embodiment party of the present invention
Formula is described in further detail.
Fig. 1 shows the modular structure of LED control chips provided in an embodiment of the present invention, for convenience of description, only shows
The part related to the embodiment of the present invention, details are as follows：
LED control chips include voltage detection module 02, decoder module 04, carrier data memory module 05, chip address
Matching module 06, chip address memory module 07, Logic control module 08, briliancy generation module 09 and drive module 10.
Wherein, voltage detection module 02 is connected with supply voltage and decoder module 04 respectively, decoder module 04 and carrier wave
The input connection of data memory module 05, control data input and the carrier data memory module 05 of Logic control module 08
Control data output end, the address date input of Logic control module 08 and the address date of carrier data memory module 05
Output end, the address date output end of Logic control module 08 while the address date input with chip address matching module 06
With the connection of the input of chip address memory module 07, the output end of chip address memory module 07 matches mould with chip address
The chip address input connection of block 06, the first output end of Logic control module 08 connect with the control terminal of briliancy generation module 09
Connect, the luminance data output end of carrier data memory module 05 is connected with the data input pin of briliancy generation module 09, briliancy life
Data output end into module 09 is connected with drive module 10.
In above-mentioned LED control chips, voltage detection module 02 receives composite power source voltage, and composite power source voltage includes electricity
Source voltage and data-signal, voltage detection module 02 extract data letter according to the reference voltage received in composite power source voltage
Number, decoder module 04 is sampled according to the system clock received to data-signal to obtain carrier data, and by carrier number
According to being stored in carrier data memory module 05, carrier data includes control data, address date, luminance data and end frame
Address date is forwarded to chip address matching module 06, control chip address matching module 06 by information, Logic control module 08
Judge whether the chip address in chip address memory module is consistent with address date, if so, then being sent out to Logic control module 08
Address matching signal is sent, if control data of the Logic control module 08 in carrier data memory module 05 judges mode of operation
Mode of operation is drive pattern, and Logic control module 08 generates trigger signal, briliancy according to address matching signal and drive pattern
Generation module 09 reads the luminance data in carrier data memory module 05 according to institute's trigger signal and generated according to luminance data
One or more luminance signal, drive module 10 according to one or more luminance signal drive one or more luminous two
Pole pipe.
Voltage detecting circuit 02 can include resistance and comparator, after composite power source voltage is by electric resistance partial pressure, pass through ratio
Compared with device to extract data-signal compared with reference voltage.
Briliancy generation module 09 according to institute's trigger signal by luminance data be converted into different duty one or more
Luminance signal.
Carrier data memory module 05 can be shift register.
Wherein, the drive end of drive circuit connection external LED, for driving external LED work according to luminance signal.LED
Control chip at least drives external LED all the way, and LED control chips can be packaged together with external LED.
Frame end information can be using the duration as the scheduled time low-voltage represent.
When developer designs LED display, the generally existing data wire of LED control chips has a power line again, assembling and
Maintenance personal is difficult to be distinguish between, and the application multiplexing of transmission on a cable by supply voltage and data-signal, realizes letter
Change the pin of LED control chips and reduce cost, and in favor of the assembling and maintenance of LED display.
In specific implementation, as shown in Fig. 2 the address date output end of Logic control module 08 matches with chip address simultaneously
The connection of the address date input of module 06 and the input of chip address memory module 07；Logic control module 08 is according to control
Data processed judge mode of operation, if mode of operation is write address pattern, address date is write to chip address memory module
07。
Logic control module 08 judges whether the control data in carrier data memory module is the first data, if
It is then to judge mode of operation for drive pattern, if it is not, then Logic control module 08 is judged in the carrier data memory module 05
Control data whether be the second data, if so, then judging mode of operation for write address pattern.
Specifically, when control data is the second data 10, mode of operation is write address pattern.When control data is first
During data 11, mode of operation is drive pattern.
Logic control circuit can be by blowing the polysilicon fuse in chip address memory module 07 with setting chip
Location.
Control data can be two, and address date can be eight, and luminance data can include the first luminance data, the
Two luminance datas and the 3rd luminance data, the first luminance data, the second luminance data and the 3rd luminance data can be eight.
First luminance data, the second luminance data and the 3rd luminance data represent the briliancy of different external LEDs respectively.8
Luminance data represents 0-255 different numerical value, and different numerical value correspond to the different brightness of external LED, when numerical value is 0, external LED
Brightness it is minimum, lamp goes out, and when data are 255, the brightness of external LED is maximum, when data are middle a certain numerical value, such as 128
When, represent output brightness corresponding to 128/256 dutycycle voltage of output.
Due to there is a 8 bit address positions, therefore chip address totally 256.
In specific implementation, the combination that 0.2us and the lasting 10us of low level can be persistently more than with high level represents 1, with low electricity
The flat combination for continuing 5us and high level persistently more than 0.2us represents 0, and high level is persistently more than 0.2us and low level continues
20us, represent and terminate frame signal, illustrate that data are sent and terminate.
As shown in figure 3, LED control chips also include reference voltage generation module 01 and oscillation module 03；
Reference voltage generation module 01 is connected with voltage detection module 02, and oscillation module 03 is connected with decoder module 04；
Oscillation module 03 generates and sends system clock；Reference voltage generation module 01 generates and sends reference voltage.Base
Quasi- voltage generation module 01 generates and sends reference voltage and is specially：One is provided not with supply voltage and the benchmark of temperature change
Voltage.Reference voltage value can be 1.2V.Fig. 4 shows the voltage detecting mould of LED control chips provided in an embodiment of the present invention
The exemplary circuit structure of block 02, for convenience of description, the part related to the embodiment of the present invention is illustrate only, details are as follows：
Voltage detection module 02 includes the first phase inverter U1, the second phase inverter U2, the first FET M1, the second field-effect
Pipe M2, the 3rd FET M3, the 4th FET M4, the 5th FET M5, the 6th FET M6, the 7th FET
M7 and the 8th FET M8.
First resistor R1 first end, the first FET M1 source electrode, the second FET M2 source electrode and the 5th
FET M5 source electrode is connected with supply voltage, the first FET M1 grid while the grid with the second FET M2
The drain electrode of pole and the 3rd FET M3 connects, the second FET M2 drain electrode simultaneously with the 4th FET M4 drain electrode and
5th FET M5 grid connection, the 3rd FET M3 grid and first resistor R1 the second end and second resistance R2
First end connection, the 3rd FET M3 source electrode simultaneously with the 4th FET M4 source electrode and the 6th FET M6
Drain electrode connection, the 4th FET M4 grid are the first input end of voltage detection module 02, the 5th FET M5 leakage
Pole connects with the input of the 7th FET M7 drain electrode, the 8th FET M8 drain electrode and the first phase inverter U1 simultaneously
Connect, the 6th FET M6 grid and the second input that the 7th FET M7 grid is voltage detection module 02, the
Eight FET M8 grid is connected with the second phase inverter U2 output end, and the second phase inverter U2 input is voltage detecting mould
3rd input of block 02, the first phase inverter U1 output end are the output end of voltage detection module 02, the of second resistance R2
Two ends, the 6th FET M6 source electrode, the 7th FET M7 source electrode and the 8th FET M8 source electrode are connected to altogether
Power supply.
Fig. 5 shows the exemplary circuit of the chip address memory module 07 of LED control chips provided in an embodiment of the present invention
Structure, for convenience of description, the part related to the embodiment of the present invention is illustrate only, details are as follows：
Chip address memory module 07 includes multiple chip address memory cell, and chip address memory cell includes polysilicon
Fuse R0, the 9th FET M9, the tenth FET M10, the 11st FET M11 and the 12nd FET M12.
Polysilicon fuse R0 first end, the tenth FET M10 grid, the 11st FET M11 source electrode are equal
It is connected with the first power supply VAA, polysilicon fuse R0 the second end while the drain electrode with the 9th FET M9, the tenth FET
The grid connection of M10 drain electrode, the 11st FET M11 grid and the 12nd FET M12, the 9th FET
M9 grid is the input of chip address memory cell, the 11st FET M11 drain electrode and the 12nd FET M12
Drain electrode for chip address memory cell output end, the 9th FET M9 source electrode, the tenth FET M10 source electrode with
And the 12nd FET M12 source electrode with being connected to power supply altogether.
The output end of multiple chip address memory cell collectively forms the output end of chip address memory module 07, Duo Gexin
The input of piece address storaging unit collectively forms the input of chip address memory module 07.
Fig. 6 shows chip address matching module 06 and the logic control of LED control chips provided in an embodiment of the present invention
The exemplary circuit structure of module 08, for convenience of description, the part related to the embodiment of the present invention is illustrate only, details are as follows：
Chip address matching module 06 include first with OR gate U3, second with OR gate U4, the 3rd with OR gate U5, the 4th with or
Door U6, the 5th with OR gate U7, the 6th with OR gate U8, the 7th with OR gate U9, the 8th with OR gate U10, the first NAND gate U11, the 3rd
Phase inverter U12, the second NAND gate U13, the 4th phase inverter U14, the 3rd NAND gate U15 and the 5th phase inverter U16.
First with OR gate U3 first input end, second with OR gate U4 first input end, the 3rd with the first of OR gate U5
Input, the 4th with OR gate U6 first input end, the 5th with OR gate U7 first input end, the 6th with the first defeated of OR gate U8
Enter end, the 7th collectively form chip address with OR gate U10 first input end with OR gate U9 first input end and the 8th
Address date input with module 06, first with OR gate U3 the second input, second with OR gate U4 the second input,
Three with OR gate U5 the second input, the 4th with OR gate U6 the second input, the 5th with OR gate U7 the second input, the 6th
The second input with OR gate U8, the 7th are total to OR gate U9 the second input and the 8th with OR gate U10 the second input
With the chip address input for forming chip address matching module 06, first with OR gate U3 output end and the first NAND gate U11
First input end connection, second is connected with OR gate U4 output end with the first NAND gate U11 the second input, the 3rd together or
Door U5 output end be connected with the first NAND gate U11 the 3rd input, the 4th with OR gate U6 output end and the first NAND gate
U11 the 4th input connection, the 5th is connected with OR gate U7 output end with the second NAND gate U13 first input end, and the 6th
Output end with OR gate U8 is connected with the second NAND gate U13 the second input, the 7th with OR gate U9 output end with second with
NOT gate U13 the 3rd input connection, the 8th is connected with OR gate U10 output end with the second NAND gate U13 the 4th input,
First NAND gate U11 output end is connected with the 3rd phase inverter U12 input, the second NAND gate U13 output end and the 4th
Phase inverter U14 input connection, the 3rd phase inverter U12 output end are connected with the 3rd NAND gate U15 first input end, the
Four phase inverter U14 output end is connected with the 3rd NAND gate U15 the second input, the 3rd NAND gate U15 output end and the
Five phase inverter U16 input connection, the 5th phase inverter U16 output end are the output end of chip address matching module 06.
Logic control module 08 includes the 9th with OR gate U17, the tenth with OR gate U18, the tenth together OR gate U19, the 12nd
With OR gate U20, the 4th NAND gate U21, the 5th NAND gate U23, the first nor gate U25, the second nor gate U27, hex inverter
U22, the 7th phase inverter U24, the 8th phase inverter U26 and the 9th phase inverter U28.
9th collectively forms logic control with the first input end of OR gate U17 first input end and the tenth together OR gate U19
First control data end of molding block 08, the tenth inputs with OR gate U18 first input end and the 12nd with the first of OR gate U20
End collectively forms the second control data end of Logic control module 08, the 9th with OR gate U17 the second input and 3rd resistor
R3 connections, the tenth together OR gate U19 the second input are connected with the 5th resistance R5 first end, and the tenth the same as the of OR gate U18
Two inputs are connected with the 4th resistance R4 first end, the 12nd with OR gate U20 first input end and the 6th resistance R6
One end connect, the 4th NAND gate U21 first input end, 3rd resistor R3 the second end, the 5th resistance R5 the second end and
6th resistance R6 the second end is connected with second source VBB, and the 9th the same as OR gate U17 output end and the 4th NAND gate U21
Second input connects, and the tenth is connected with OR gate U18 output end with the 4th NAND gate U21 the 3rd input, the 5th with it is non-
Door U23 first input end be Logic control module 08 first input end, the 5th NAND gate U23 the second input and the tenth
Together OR gate U19 output end connection, the 5th NAND gate U23 the 3rd input with the 12nd with OR gate U20 output end company
Connect, the 4th NAND gate U21 output end connects with hex inverter U22 input and the second nor gate U27 first input end
Connect, the 5th NAND gate U23 output end is connected with the 7th phase inverter U24 input, hex inverter U22 output end and the
One nor gate U25 first input end connection, the first nor gate U25 the second input and the 4th resistance R4 the second end connect altogether
In power supply, the 7th phase inverter U24 output end is connected with the first nor gate U25 the 3rd input, the second nor gate U27's
Second input is the second input of Logic control module 08, and the first nor gate U25 output end is with the 8th phase inverter U26's
Input connects, and the 8th phase inverter U26 output end is the first output end of Logic control module 08, the second nor gate U27's
Output end is connected with the 9th phase inverter U28 input, and the 9th phase inverter U28 output end is the second of Logic control module 08
Output end.
First control data end of Logic control module 08 and the second common structure in control data end of Logic control module 08
Into the control data input of Logic control module 08.
In addition, the present invention also provides a kind of LED information display system, LED information display system includes above-mentioned LED control chips.
Below in conjunction with operation principle to being described further shown in Fig. 4 to Fig. 6：
In specific implementation process, reference voltage generation module 01 generates and sends reference voltage to the 4th FET M4
Grid, composite power source voltage is added on divider resistance (first resistor R1 and second resistance R2), when composite power source voltage is more than
During predeterminated voltage (such as 3V), the 5th FET M5 drain electrode output is 0, and after inverted device, voltage detection module 02 exports
1；When supply voltage is less than predeterminated voltage, the 5th FET M5 drain electrode output is 1, after inverted device, voltage detecting
The output of module 02 is 0, data-signal is extracted in composite power source voltage according to the reference voltage received, oscillation module 03 generates
And system clock is sent, decoder module 04 is sampled according to system clock to data-signal to obtain carrier data, and will be carried
For wave number according to being stored in carrier data memory module 05, carrier data includes control data, address date, luminance data and knot
Beam frame information, Logic control module 08 by address date be forwarded in chip address matching module 06 first with OR gate U3 to
Eight with OR gate U10, and first in chip address matching module 06 stores mould with OR gate U10 with OR gate U3 to the 8th from chip address
Chip address is read in block 07, chip address matching module 06 judges whether chip address is consistent with address date, if chip
Location is consistent with address date, and address matching signal (high level) is sent to Logic control module from the 5th phase inverter U16 output ends
The first input end of the 5th NAND gate U23 in 08, the 9th reads carrier data with OR gate U17 to the 12nd with OR gate U20 deposits
The control data in module 05 is stored up, and Logic control module 08 judges mode of operation according to control data, if mode of operation is
Drive pattern (when such as control data is 11, hex inverter U22 outputs low level signal), then the in Logic control module 08
One nor gate U25 and the 8th phase inverter U26 generation trigger signal (low level) and the output end from the 8th phase inverter U26 export to
Briliancy generation module 09, luminance data of the briliancy generation module 09 in trigger signal reading carrier data memory module 05 is simultaneously
One or more luminance signal is generated according to luminance data, drive module 10 drives one according to one or more luminance signal
Individual or multiple light emitting diodes.
Logic control module 08 judges mode of operation according to control data, (is such as controlled if mode of operation is write address pattern
When data are 01, the 9th phase inverter U28 output end output high level signal), then it is defeated according to the 9th phase inverter U28 output end
The high level signal gone out writes address date to chip address memory module 07.Specifically, high level signal can be exported
To the 9th FET M9 grid, with the polysilicon fuse R0 that fuses；When polysilicon fuse R0 is unblown, chip address because
VDD is connected to for polysilicon fuse R0, the output of chip address memory module 07 is 0 after reversely, so chip default address
For 0；After polysilicon fuse R0 fuses, disconnection is connected with VDD, due to the tenth FET M10 grid lengths are big and width is small,
Therefore under the effect of the tenth FET M10 pull down resistors, the output of chip address memory module 07 is 1.
The embodiment of the present invention extracts the data according to reference voltage by voltage detection module in composite power source voltage
Signal, decoder module are sampled according to the system clock to data-signal to obtain carrier data, and carrier data includes control
Data processed, address date, luminance data and terminate frame information, then chip address matching module judge chip address whether with institute
It is consistent to state address date, if so, then sending address matching signal to Logic control module, Logic control module is according to control data
Judge mode of operation, if the mode of operation is drive pattern, Logic control module is according to address matching signal and driving mould
Formula generates trigger signal so that briliancy generation module generates one or more luminance signal, driving mould according to the luminance data
Root tuber drives one or more light emitting diode according to one or more luminance signal, realizes a cable while provides electricity
Source and transmission data, avoid because cable radical excessively causes cost higher and the problem of easy connection error, simplifies chip
Design, adds the competitiveness of product in market.Meanwhile Logic control module judges mode of operation according to control data, if work
Pattern is write address pattern, then writes address date to chip address memory module, can be in the finishing operation of finished product
Burning address, it is very big convenient to be brought to manufacture processing.
The foregoing is only presently preferred embodiments of the present invention, be not intended to limit the invention, it is all the present invention spirit and
Within principle, any modification, equivalent substitution and improvements made etc., it should be included in the scope of the protection.
Claims (10)
1. a kind of LED control chips, it is characterised in that the LED control chips include voltage detection module, decoder module, load
Ripple data memory module, chip address matching module, chip address memory module, Logic control module, briliancy generation module with
And drive module；
The voltage detection module is connected with supply voltage and the decoder module respectively, the decoder module and the carrier wave
The input connection of data memory module, control data input and the carrier data storage mould of the Logic control module
The control data output end of block, the address date input of the Logic control module and the ground of the carrier data memory module
Location data output end, the address date output end of the Logic control module and the address date of the chip address matching module
Input, the output end of the chip address memory module and the chip address input of the chip address matching module connect
Connect, the first output end of the Logic control module is connected with the control terminal of the briliancy generation module, and the carrier data is deposited
The luminance data output end of storage module is connected with the data input pin of the briliancy generation module, the number of the briliancy generation module
It is connected according to output end with the drive module；
The voltage detection module receives composite power source voltage, and the composite power source voltage includes supply voltage and data-signal,
The voltage detection module extracts the data-signal according to the reference voltage received in the composite power source voltage, described
Decoder module is sampled according to the system clock received to the data-signal to obtain carrier data, and by the carrier wave
Data storage in the carrier data memory module, the carrier data include control data, address date, luminance data with
And terminating frame information, the address date is forwarded to the chip address matching module by the Logic control module, controls institute
State chip address matching module and judge whether the chip address in the chip address memory module is consistent with the address date,
If so, then sending address matching signal to the Logic control module, the Logic control module is deposited according to the carrier data
The control data in storage module judges mode of operation, if the mode of operation is drive pattern, the Logic control module
According to the address matching signal and drive pattern generation trigger signal, the briliancy generation module is according to institute's trigger signal
Read the luminance data in the carrier data memory module and one or more brightness is generated according to the luminance data
Signal is spent, the drive module drives one or more light emitting diode according to one or more of luminance signals.
2. LED control chips as claimed in claim 1, it is characterised in that the address date output of the Logic control module
End simultaneously with the address date input of the chip address matching module and the input of the chip address memory module
Connection；
The Logic control module judges mode of operation according to the control data, if the mode of operation is write address pattern,
Then the address date is write to the chip address memory module.
3. LED control chips as claimed in claim 1, it is characterised in that the voltage detecting circuit includes resistance and compared
Device, after the composite power source voltage is by electric resistance partial pressure, by the comparator to extract compared with the reference voltage
Data-signal.
4. LED control chips as claimed in claim 2, it is characterised in that the Logic control module judges the carrier number
Whether it is the first data according to the control data in memory module, if so, mode of operation is then judged for drive pattern, if it is not,
Then the Logic control module judges whether the control data in the carrier data memory module is the second data, if
It is then to judge mode of operation for write address pattern.
5. LED control chips as claimed in claim 1, it is characterised in that the control data is two, the address date
For eight, the luminance data includes the first luminance data, the second luminance data and the 3rd luminance data, the first briliancy number
It it is eight according to, second luminance data and the 3rd luminance data.
6. LED control chips as claimed in claim 1, it is characterised in that the voltage detection module include the first phase inverter,
Second phase inverter, the first FET, the second FET, the 3rd FET, the 4th FET, the 5th FET,
6th FET, the 7th FET and the 8th FET；
The first end of the first resistor, the source electrode of first FET, the source electrode of the second FET and the 5th
The source electrode of effect pipe is connected with supply voltage, the grid of first FET while the grid with second FET
The drain electrode of pole and the 3rd FET connects, second FET drain electrode simultaneously with the 4th FET
Drain electrode connects with the grid of the 5th FET, the grid of the 3rd FET and the second end of the first resistor
Connected with the first end of the second resistance, the source electrode of the 3rd FET while the source electrode with the 4th FET
Drain electrode with the 6th FET connects, and the grid of the 4th FET is first defeated for the voltage detection module
Enter end, the drain electrode of the 5th FET simultaneously with the draining of the 7th FET, the leakage of the 8th FET
The input of pole and the first phase inverter connects, and the grid of the 6th FET and the grid of the 7th FET are
Second input of the voltage detection module, the grid of the 8th FET connect with the output end of second phase inverter
Connect, the input of second phase inverter is the 3rd input of the voltage detection module, the output of first phase inverter
Hold as the output end of the voltage detection module, the second end of the second resistance, the source electrode, described of the 6th FET
The source electrode of 7th FET and the source electrode of the 8th FET with being connected to power supply altogether.
7. LED control chips as claimed in claim 2, it is characterised in that the chip address memory module includes multiple cores
Piece address storaging unit, chip address memory cell include polysilicon fuse, the 9th FET, the tenth FET, the tenth
One FET and the 12nd FET；
The first end of the polysilicon fuse, the grid of the tenth FET, the source electrode of the 11st FET are equal
Be connected with the first power supply, the second end of the polysilicon fuse simultaneously with the draining of the 9th FET, the described ten
The grid connection of the draining of effect pipe, the grid of the 11st FET and the 12nd FET, described the
The grid of nine FETs is the input of the chip address memory cell, the drain electrode of the 11st FET and described
12nd FET drains as the output end of the chip address memory cell, the source electrode of the 9th FET, institute
State the tenth FET source electrode and the 12nd FET source electrode with being connected to power supply altogether；
The output end of the multiple chip address memory cell collectively forms the output end of the chip address memory module, described
The input of multiple chip address memory cell collectively forms the input of the chip address memory module.
8. LED control chips as claimed in claim 1, it is characterised in that it is same that the chip address matching module includes first
It is OR gate, the second same OR gate, the 3rd same OR gate, the 4th same OR gate, the 5th same OR gate, the 6th same OR gate, the 7th same OR gate, the 8th same
OR gate, the first NAND gate, the 3rd phase inverter, the second NAND gate, the 4th phase inverter, the 3rd NAND gate and the 5th phase inverter；
Described first with the first input end of OR gate, described second with the first input end of OR gate, the described 3rd with the of OR gate
First input end, the described 5th first input end, the 6th same OR gate with OR gate of one input, the described 4th with OR gate
First input end, the described 7th collectively formed with the first input end of OR gate and the described 8th with the first input end of OR gate
The address date input of the chip address matching module, described first with OR gate the second input, it is described second with or
Door the second input, the described 3rd with OR gate the second input, the described 4th with OR gate the second input, the described 5th
The second input with OR gate, the described 6th with OR gate the second input, the described 7th with OR gate the second input and
Described 8th collectively forms the chip address input of the chip address matching module with the second input of OR gate, and described
Together the output end of OR gate is connected with the first input end of first NAND gate, described second with OR gate output end with it is described
The second input connection of first NAND gate, the described 3rd the same as the output end of OR gate and the 3rd input of first NAND gate
Connection, the described 4th is connected with the output end of OR gate with the 4th input of first NAND gate, and the described 5th the same as OR gate
Output end is connected with the first input end of second NAND gate, the described 6th output end with OR gate and second NAND gate
The connection of the second input, the described 7th is connected with the output end of OR gate with the 3rd input of second NAND gate, described
8th is connected with the output end of OR gate with the 4th input of second NAND gate, the output end of first NAND gate and institute
The input connection of the 3rd phase inverter is stated, the output end of second NAND gate is connected with the input of the 4th phase inverter,
The output end of 3rd phase inverter is connected with the first input end of the 3rd NAND gate, the output end of the 4th phase inverter
It is connected with the second input of the 3rd NAND gate, the output end of the 3rd NAND gate and the input of the 5th phase inverter
End connection, the output end of the 5th phase inverter are the output end of the chip address matching module.
9. LED control chips as claimed in claim 1, it is characterised in that the Logic control module include the 9th same OR gate,
Tenth same OR gate, the tenth together OR gate, the 12nd same OR gate, the 4th NAND gate, the 5th NAND gate, the first nor gate, second or
NOT gate, hex inverter, the 7th phase inverter, the 8th phase inverter and the 9th phase inverter；
Described 9th collectively forms the logic with the first input end of the first input end of OR gate and the described tenth together OR gate
First control data end of control module, the described tenth with the first input end of OR gate and the described 12nd with the first defeated of OR gate
Enter end and collectively form the second control data end of the Logic control module, the described 9th with OR gate the second input with it is described
3rd resistor connect, the described tenth together the second input of OR gate be connected with the first end of the 5th resistance, the described tenth
The second input with OR gate is connected with the first end of the 4th resistance, the described 12nd first input end and institute with OR gate
State the first end connection of the 6th resistance, the first input end of the 4th NAND gate, the second end of the 3rd resistor, described the
Second end of five resistance and the second end of the 6th resistance are connected with second source, the described 9th with OR gate output end
It is connected with the second input of the 4th NAND gate, the described tenth the same as the 3rd of output end and the 4th NAND gate of OR gate
Input connects, and the first input end of the 5th NAND gate is the first input end of the Logic control module, and the described 5th
Second input of NAND gate is connected with the output end of the described tenth together OR gate, the 3rd input of the 5th NAND gate with
Described 12nd connects with the output end of OR gate, the output end of the 4th NAND gate and the input of the hex inverter and
The first input end connection of second nor gate, the output end of the 5th NAND gate and the input of the 7th phase inverter
Connection, the output end of the hex inverter are connected with the first input end of first nor gate, first nor gate
Second end of the second input and the 4th resistance with being connected to power supply altogether, the output end and described first of the 7th phase inverter
The 3rd input connection of nor gate, the second input of second nor gate input for the second of the Logic control module
End, the output end of first nor gate are connected with the input of the 8th phase inverter, the output end of the 8th phase inverter
For the first output end of the Logic control module, the output end of second nor gate and the input of the 9th phase inverter
Connection, the output end of the 9th phase inverter are the second output end of the Logic control module.
First control data end of the Logic control module and the second common structure in control data end of the Logic control module
Into the control data input of the Logic control module.
10. a kind of LED information display system, it is characterised in that the LED information display system includes the LED controls as described in any one of claim 1 to 9
Coremaking piece.
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