CN211209989U - L ED control chip for power line data transmission - Google Patents
L ED control chip for power line data transmission Download PDFInfo
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- CN211209989U CN211209989U CN201922047625.4U CN201922047625U CN211209989U CN 211209989 U CN211209989 U CN 211209989U CN 201922047625 U CN201922047625 U CN 201922047625U CN 211209989 U CN211209989 U CN 211209989U
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Abstract
The utility model discloses a L ED control chip of power cord transmission data carries out data identification to the combined power source voltage height through voltage detection module, the decoding module is right data signal samples in order to acquire carrier data, and data frame identification module makes statistics of the carrier data after decoding on the power cord, logic control module is used for with address in the chip address setting module with the data frame count compares, when logic control module judges that the chip address matches current data frame count value, catches the brilliance display data in the current data frame and sends brilliance generation module, brilliance generation module basis brilliance display data generates the brilliance signal, output drive module is according to brilliance signal drive emitting diode.
Description
Technical Field
The utility model relates to an L ED lighting technology field especially relates to a L ED control chip of power cord transmission data.
Background
The system is characterized in that a plurality of power supply carrier L ED control chips are applied to occasions such as a 3D lamp, a Christmas lamp, a curtain lamp and the like, compared with the prior four-wire transmission system, the system simplifies the installation process and greatly saves the cable cost, and simultaneously reduces the fault rate of products without maintenance troubles.
SUMMERY OF THE UTILITY MODEL
An object of the utility model is to overcome above-mentioned not enough, provide an L ED control chip of power cord transmission data.
In order to achieve the purpose, the utility model adopts the technical scheme that the power line transmits data through the L ED control chip, the L ED control chip comprises an oscillator, a reference voltage, a voltage detection module, a logic control module, a decoding module, a carrier data module, a chip address setting module, a data frame identification module, a data frame counting setting module, a luminance generation module and an output driving module, wherein the oscillator is connected with the decoding module, the reference voltage is connected with the voltage detection module, the voltage detection module is respectively connected with a composite power voltage and the input end of the decoding module, the output end of the decoding module is connected with the input end of the carrier data module, the carrier data module is connected with the data frame identification module, the data frame identification module is connected with the data frame counting setting module, the carrier data module, the data frame counting setting module and the chip address setting module are connected with the input end of the logic control module, the output end of the logic control module is connected with the input end of the luminance generation module and the input end of the chip address setting module, and the output end of the luminance generation module is connected with the input end of the output driving module and the output pin of the luminance output driving module;
the voltage detection module receives a composite power supply voltage, the composite power supply voltage comprises a power supply voltage and a data signal, the voltage detection module performs data identification at the composite power supply voltage according to a received reference voltage, the decoding module samples the data signal according to a received system clock, the carrier data module converts the voltage detection result into carrier data, the data frame identification module counts the carrier data decoded on a power supply line, the data frame count setting module counts data frames, the logic control module is used for comparing an address in the chip address setting module with the data frame count, and when the logic control module judges that the chip address matches a current data frame count value, luminance display data in a current data frame are captured and sent to the luminance generation module, the luminance generation module generates one or more luminance signals with different duty ratios according to the luminance display data, and the output driving module drives one or more light-emitting diodes according to the one or more luminance signals with different duty ratios.
Preferably, the reference voltage is used for providing a voltage which is not changed along with the power supply voltage and the temperature, and the value of the reference voltage is 1-1.5V.
Preferably, the internal address of the chip address setting module comprises one or more of a laser fuse, a metal fuse, a polyfuse, an otp and an mtp.
Preferably, the voltage detection module includes a resistor and a comparator, and after the composite power supply voltage is divided by the resistor, the composite power supply voltage is compared with the reference voltage by the comparator to extract the data signal.
Preferably, the chip address setting module sends a control signal through a power line to burn the polysilicon fuse so as to set a chip address, and the address is set to 8 bits.
Preferably, the initial value of the data frame counting module is set by a control system sending a control instruction.
Preferably, the data frame signal of the composite power supply voltage is represented by a combination of high voltage and low voltage with different durations, and the data frame signal on the power supply line includes a control code, first data, second data and third data.
Preferably, the control code includes two working mode selection bits, and when the working mode control code selection bit is 11, the data frame identification module counts the carrier data and counts the carrier data; and when the selection bit of the working mode control code is 01, the logic control module compares the address in the chip address setting module with the data frame count.
Preferably, the first data, the second data and the third data are respectively set to 8 bits, the 8-bit data information represents 0-255 different values, the different values correspond to different luminances of L ED lamps, when the value is 0, the luminance of L ED lamp is minimum, the lamp is off, and when the data is 255, the luminance of L ED lamp is maximum.
Preferably, the memory space of the L ED control chip is larger than 256 chip addresses.
The utility model discloses need not to send the chip address when sending the display data, the chip matches self address according to the sending order of display data automatically, has reduced the data volume of sending out the sign indicating number from the principle, improves the refresh speed that shows the frame. The transmitted data are reduced, the error rate of the data received by the chip is correspondingly reduced, and the requirements of software and hardware of a control system are reduced, so that the cost of the product is saved, and the market competitiveness is improved.
Drawings
The accompanying drawings, which are described herein, serve to provide a further understanding of the invention and constitute a part of this specification, and the exemplary embodiments and descriptions thereof are provided for explaining the invention without unduly limiting it. In the drawings:
FIG. 1 is a schematic diagram of the control circuit structure of the present invention;
FIG. 2 is a schematic diagram of the data control signal of the present invention;
fig. 3 is an applied circuit diagram of the control chip of the present invention;
fig. 4 is a schematic diagram of luminance data information according to the present invention;
fig. 5 is an exemplary circuit structure of a voltage detection module in an L ED control chip according to an embodiment of the present invention;
fig. 6 is an exemplary circuit structure of a decoding module in an L ED control chip according to an embodiment of the present invention;
fig. 7 is an exemplary circuit structure of a data frame identification module in an L ED control chip according to an embodiment of the present invention;
fig. 8 is an exemplary circuit structure of a data frame count setting module in an L ED control chip according to an embodiment of the present invention.
In the figure: 1-a reference voltage; 2-an oscillator; 3-a voltage detection module; 4-a decoding module; 5-carrier data module; 6-data frame identification module; 7-data frame setting counting module; 8-chip address setting module; 9-a logic control module; 10-a luminance generation module; 11-output driving module.
Detailed Description
In order to more clearly explain the overall concept of the present invention, the following detailed description is given by way of example in conjunction with the accompanying drawings.
It should be noted that in the following description, numerous specific details are set forth in order to provide a thorough understanding of the present invention, however, the present invention may be practiced in other ways than those specifically described herein, and thus the scope of the present invention is not limited by the specific embodiments disclosed below.
As shown in fig. 1-8, a L ED control chip for transmitting data via a power line includes an oscillator 2, a reference voltage 1, a voltage detection module 3, a logic control module 9, a decoding module 4, a carrier data module 5, a chip address setting module 8, a data frame identification module 6, a data frame count setting module 7, a luminance generation module 10, and an output driving module 11, where the oscillator 2 is connected to the decoding module 4, the reference voltage 1 is connected to the voltage detection module 3, the voltage detection module 3 is connected to a composite power supply voltage and an input end of the decoding module 4, an output end of the decoding module 4 is connected to an input end of the carrier data module 5, the carrier data module 5 is connected to the data frame identification module 6, the data frame identification module 6 is connected to the data frame count setting module 7, the carrier data module 5, the data frame count setting module 7, the chip address setting module 8 is connected to an input end of the logic control module 9, an output end of the logic control module 9 is connected to an input end of the data frame identification module 6, the data frame identification module 6 is connected to a data frame count setting module 7, and a chip address setting module 638 is connected to an output pin of the led control module, and an output pin 3611 is connected to an output pin of the luminance driving module 35.
The voltage detection module 3 receives a composite power supply voltage, the composite power supply voltage includes a power supply voltage and a data signal, the voltage detection module 3 performs data identification at the composite power supply voltage according to a received reference voltage, the decoding module 4 samples the data signal according to a received system clock to obtain carrier data, the data frame identification module 5 performs statistics on the carrier data decoded on a power supply line, the logic control module 9 is configured to compare an address in the chip address setting module 8 with the data frame count, when the logic control module 9 determines that the chip address matches a current data frame count value, luminance display data in a current data frame is captured and sent to the luminance generation module 10, the luminance generation module generates one or more luminance signals according to the luminance display data, the output driving module 11 drives one or more light emitting diodes according to the one or more luminance signals, at least one channel of the chip drives L ED module, and the chip and the L ED module can be packaged together.
The reference voltage 1 provides a voltage which does not change along with power supply voltage and temperature, the reference voltage is 1-1.5V, the value of the reference voltage 1 is 1.2V in the embodiment, the voltage detection module 3 comprises a resistor and a comparator, the composite power supply voltage is divided by the resistor and then is compared with the reference voltage 1 through the comparator to extract a data signal, the oscillator 2 is used for generating an oscillation frequency signal, the decoding module 4 converts the data signal into control chip address data and luminance data of L ED lamps by using the oscillation frequency signal, the chip address setting module 8 is provided with an 8-bit address used for setting the control chip address data, and the chip address setting module 8 sets the address of the chip through the on-off of a polysilicon fuse inside the chip.
As shown in fig. 2, the binary code 1 is represented by a combination of high level lasting more than 0.2us and low level lasting more than 10us, the binary code 0 is represented by a combination of low level lasting 5us and high level lasting more than 0.2us, and the low level lasting 20us and high level lasting more than 0.2us represent RESET, which indicates that the sending of the display frame is finished and all chips on the cascade system refresh the display. The format of the display frame is as follows:
the format of the data frame signal is control code + first data + second data + third data, in this embodiment, the control code has 2 bits in total, which is a selection bit of the working mode, the first data, the second data, and the third data are respectively set to 8 bits, which represent L different luminances, and frame end information is sent when one display frame ends, and the frame end information is represented in a set time range by a low voltage duration.
When the selection bit of the working mode control code is 11, the control chip enters the working mode set by the data frame counting setting module 7, the data frame identification module 6 counts carrier data of each bit, when a data frame is judged to be completed, the counter value of the data frame counting setting module 7 is increased by one, when the selection bit of the working mode control code is 01, the address of the control chip address setting module 8 is compared with the data frame counting, when a display frame finishes receiving a RESET code, all the selected control chips in the system respectively output luminance signals with different duty ratios to drive L ED modules to work according to the first data, the second data and the third data in the control signals, at least one channel of the chips drives L ED modules, and the chips and the L ED modules can be packaged together.
The first data, the second data and the third data respectively represent L ED lamp brightness data information, the brightness data information represents as shown in FIG. 4, when the control module sends data, the control module sends low bits first and then high bits first, the control code is sent first, and then the first data, the second data and the third data are sent in sequence from low to high bits, the brightness generation module 10 converts the data information in the data control signal into brightness signals with different duty ratios, 8-bit data information represents 0-255 different values, the different values correspond to different brightness of L ED lamps, when the value is 0, the brightness of L ED lamps is minimum, the lamps are off, when the data is 255, the brightness of L ED lamps is maximum, when the data is a middle value, such as 128, PWM output is 128/256, and the storage space of L ED control chips is larger than 256 chip addresses to ensure enough storage space.
The utility model discloses well data frame represents as follows:
wherein C1C0 represents a 2-bit operation mode selection bit, and when C1C0 is equal to 11, the control chip enters the operation mode set by the data frame count setting module 7; when C1C0 is 01, the logic control module 9 is configured to compare the address in the chip address setting module 8 with the data frame count, when the logic control module 9 determines that the chip address matches the current data frame count value, the luminance display data in the current data frame is captured and sent to the luminance generation module 10, the luminance generation module 10 generates one or more luminance signals according to the luminance display data, and the output driving module 11 drives one or more light emitting diodes according to the one or more luminance signals.
When the control system refreshes a picture once, only a plurality of data frames and an end code need to be sent, and compared with the traditional DMX512 data frame two-bit start code + 8-bit data + one-bit end code and the complex display frame protocol, the control system has the advantages that less data are sent and the protocol is simpler.
As shown in fig. 5, the voltage detection module 3: POR1 provides an initial state for the chip for a power-on reset signal. VREF is the reference voltage 1.2V provided by the reference voltage, and NBIAS is the current source provided by the reference voltage as the tail current of the comparator. The power supply voltage is divided by a resistor and then input to the N end of the comparator, and is compared with VREF at the P end of the comparator. When the power supply voltage is greater than 3V, the output of the comparator is 0, and DOUT is 1 after passing through the inverter; when the power supply voltage is less than 3V, the comparator output is 1, and after passing through the inverter, DOUT is 0. The decoding module identifies the DOUT output of the voltage detection module according to the time of the signal and stores decoding data in a mode of a shift register.
As shown in fig. 6, the decoding module 4: c1 and C0 correspond to I56_ Q, I52_ Q in the shift register, and MD3M is a matching signal of chip addresses D0-D8 and data frame counts ADC1-ADC 9. I52_ Q, I56_ Q enters a matching mode of chip address and data frame count when C1C0 is 01 through the operation of the XNOR gates I486 and I487. The output of I486, I487 is AND-ed with MD3M, resulting in PDMATCH as the output enable signal. After the chip receives the end code RESET and PDMATCH is 1, the logic control circuit outputs the first data, the second data and the third data in the instruction to the luminance generation module and updates the output of the output driving module; otherwise, the output display is not refreshed.
As shown in fig. 7, the data frame identification module 6 counts each bit of data of the carrier data, counts from the first bit of the carrier data, and adds one to the data frame count setting module when the carrier data is identified as a complete data frame (two-bit control code + first data + second data + third data), and at the same time, the data frame identification module is reset to prepare to identify a new data frame again.
X68_ Y is carrier data, one pulse represents one bit of data, after the chip is electrified and reset, the carrier data is counted by I187, I185, I186, I182, I188 and I238 data frame identification registers, when the counting value is 26 bits of a complete data frame, a reset signal CNTRST is generated by a system clock C L K to reset the data frame identification registers, the CNTRST signal carries out module carry on the data frame counting, and the next data frame is waited to arrive.
As shown in FIG. 8, the operation of the I996 data frame count setting module 7 is to ensure that the carry signal of the data frame identification module is only valid when the chip works in the matching mode of the chip address and the data frame count of 01 at C1C0, and when the chip works in this mode, the data frame count setting module normally counts the carry signal of the data frame identification module, when C1C0 is 11, the chip works in the data frame count setting mode, the logic control module fetches the setting data W7-W0, red7 in the signal stream, and simultaneously enables MD2C L K, the output signals ADC1-ADC9 of the data frame counters I329-I337 are set or reset according to the difference of the setting data, ADDRESET is the signal generated when the chip is powered on, and the signal combination of the X604_ Y signal generated when the display frame ends to the data frame Schedule register is cleared, and the idle state is 1.
Taking the I330 settable reset register as an example, the set terminal and the reset terminal are both enabled at low level, the ADDRESET idle state is 1, the MD2C L K is enabled at 0, and is 1 after inversion, when W6 is 1, the inputs of both ends of the I356 nand gate are both 1, the output is 0, the set terminal enable of I330 is triggered, the ADC2 is 1, the output of I446 is 1, and the outputs are from 1 to the reset terminal of I330 after the ADDRESET and operation, and the reset is invalid.
The above-mentioned, only preferred embodiments of the present invention are described, the scope of the present invention cannot be limited, and all the equivalent changes and decorations made according to the claims of the present invention should still fall within the scope covered by the present invention.
Claims (10)
1. An L ED control chip for power line data transmission comprises an oscillator and a reference voltage, and is characterized in that the L ED control chip further comprises a voltage detection module, a logic control module, a decoding module, a carrier data module, a chip address setting module, a data frame identification module, a data frame count setting module, a luminance generation module and an output driving module, wherein the oscillator is connected with the decoding module, the reference voltage is connected with the voltage detection module, the voltage detection module is respectively connected with a composite power supply voltage and the input end of the decoding module, the output end of the decoding module is connected with the input end of the carrier data module, the carrier data module is connected with the data frame identification module, the data frame identification module is connected with the data frame count setting module, the carrier data module, the data frame count setting module and the chip address setting module are connected with the input end of the logic control module, the output end of the logic control module is connected with the input end of the luminance generation module and the input end of the chip address setting module, the output end of the luminance generation module is connected with the input end of the output driving module, and the output pin of the output driving module is connected with the output pin of the output pin;
the voltage detection module receives a composite power supply voltage, the composite power supply voltage comprises a power supply voltage and a data signal, the voltage detection module performs data identification at the composite power supply voltage according to a received reference voltage, the decoding module samples the data signal according to a received system clock, the carrier data module converts the voltage detection result into carrier data, the data frame identification module counts the carrier data decoded on a power supply line, the logic control module is used for comparing an address in the chip address setting module with the data frame count, the data frame count setting module counts data frames, and when the logic control module judges that the chip address matches a current data frame count value, luminance display data in the current data frame are captured and sent to the luminance generation module, the luminance generation module generates one or more luminance signals with different duty ratios according to the luminance display data, and the output driving module drives one or more light-emitting diodes according to the one or more luminance signals with different duty ratios.
2. The L ED control chip for transmitting data through power line according to claim 1, wherein the reference voltage is used to provide a voltage that is invariant to power supply voltage and temperature, and the reference voltage is 1-1.5V.
3. The L ED control chip for transmitting data through power line as claimed in claim 1, wherein the internal address of the chip address setting module includes one or more of laser fuse, metal fuse, poly fuse, otp, mtp.
4. The L ED control chip for transmitting data through power line according to claim 1, wherein the voltage detection module comprises a resistor and a comparator, and the composite power voltage is divided by the resistor and then compared with the reference voltage by the comparator to extract the data signal.
5. The L ED control chip for transmitting data through a power line of claim 1, wherein the chip address setting module sets the chip address by sending a control signal through the power line to burn a polysilicon fuse, and the address is set to 8 bits.
6. The L ED control chip for transmitting data through power line according to claim 1, wherein the initial value of the data frame counting module is set by a control system issuing a control command.
7. The L ED control chip for transmitting data on power line according to claim 1, wherein the data frame signal of the composite power voltage is represented by a combination of high voltage and low voltage with different durations, and the data frame signal on the power line includes control code, first data, second data, and third data.
8. The L ED control chip for transmitting data via power line according to claim 7, wherein the control code includes two operation mode selection bits, the data frame identification module counts each bit of carrier data when the operation mode control code selection bit is 11, the data frame counter value is incremented when a data frame is determined to be completed, and the logic control module compares the address in the chip address setting module with the data frame count when the operation mode control code selection bit is 01.
9. The L ED control chip for transmitting data through power line of claim 7, wherein the first data, the second data and the third data are respectively set to 8 bits, the 8 bits of data information represents 0-255 different values, the different values correspond to different brightnesses of L ED lamps, when the value is 0, the brightness of L ED lamp is the minimum, the lamp is turned off, and when the value is 255, the brightness of L ED lamp is the maximum.
10. The L ED control chip for transmitting data over power lines of claim 1, wherein the L ED control chip has a memory space larger than 256 chip addresses.
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| CN201922047625.4U CN211209989U (en) | 2019-11-25 | 2019-11-25 | L ED control chip for power line data transmission |
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Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN111918454A (en) * | 2019-11-25 | 2020-11-10 | 宗仁科技(平潭)有限公司 | LED control chip for power line data transmission |
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Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN111918454A (en) * | 2019-11-25 | 2020-11-10 | 宗仁科技(平潭)有限公司 | LED control chip for power line data transmission |
| CN111918454B (en) * | 2019-11-25 | 2024-04-16 | 宗仁科技(平潭)股份有限公司 | LED control chip for transmitting data through power line |
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Address after: 350000 2 / F, building 9, Taiwan Pioneer Park, jinjingwan 2nd Road, beicuo Town, Pingtan County, Fuzhou City, Fujian Province Patentee after: Zongren Technology (Pingtan) Co.,Ltd. Address before: 350000 2 / F, building 9, Taiwan Pioneer Park, jinjingwan 2nd Road, beicuo Town, Pingtan County, Fuzhou City, Fujian Province Patentee before: ZONGREN TECHNOLOGY (PINGTAN) Co.,Ltd. |