CN116133184A - LED driving circuit - Google Patents
LED driving circuit Download PDFInfo
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- CN116133184A CN116133184A CN202211407315.9A CN202211407315A CN116133184A CN 116133184 A CN116133184 A CN 116133184A CN 202211407315 A CN202211407315 A CN 202211407315A CN 116133184 A CN116133184 A CN 116133184A
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- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05B—ELECTRIC HEATING; ELECTRIC LIGHT SOURCES NOT OTHERWISE PROVIDED FOR; CIRCUIT ARRANGEMENTS FOR ELECTRIC LIGHT SOURCES, IN GENERAL
- H05B45/00—Circuit arrangements for operating light-emitting diodes [LED]
- H05B45/30—Driver circuits
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- G—PHYSICS
- G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
- G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
- G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
- G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
- G09G3/22—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources
- G09G3/30—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels
- G09G3/32—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED]
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- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05B—ELECTRIC HEATING; ELECTRIC LIGHT SOURCES NOT OTHERWISE PROVIDED FOR; CIRCUIT ARRANGEMENTS FOR ELECTRIC LIGHT SOURCES, IN GENERAL
- H05B45/00—Circuit arrangements for operating light-emitting diodes [LED]
- H05B45/30—Driver circuits
- H05B45/37—Converter circuits
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- G—PHYSICS
- G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
- G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
- G09G2310/00—Command of the display device
- G09G2310/02—Addressing, scanning or driving the display screen or processing steps related thereto
- G09G2310/0264—Details of driving circuits
- G09G2310/0286—Details of a shift registers arranged for use in a driving circuit
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- Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
- Y02B—CLIMATE CHANGE MITIGATION TECHNOLOGIES RELATED TO BUILDINGS, e.g. HOUSING, HOUSE APPLIANCES OR RELATED END-USER APPLICATIONS
- Y02B20/00—Energy efficient lighting technologies, e.g. halogen lamps or gas discharge lamps
- Y02B20/40—Control techniques providing energy savings, e.g. smart controller or presence detection
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- Engineering & Computer Science (AREA)
- Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- General Physics & Mathematics (AREA)
- Theoretical Computer Science (AREA)
- Control Of El Displays (AREA)
- Led Devices (AREA)
Abstract
The invention provides an LED driving circuit which comprises a voltage stabilizing source, a reference circuit, an address module, an oscillator circuit, a signal identification circuit, a data decoding circuit, a level conversion circuit, a mode control circuit and an output driving circuit, wherein the voltage stabilizing source is connected with the reference circuit; the invention can realize the scheme that a plurality of LED units are controlled independently.
Description
Technical Field
The invention relates to the field of LED display screen driving, in particular to an LED driving circuit.
Background
At present, a plurality of LED units are connected in parallel on a data line, a controller sends control data through the data line, and the LED units receive data belonging to the LED units according to own inherent addresses. And transmitting the data of other units back through the data output end, and receiving the data of all the LED units according to the designed data protocol.
The method can realize independent control of the controller on each LED unit, but needs a plurality of wires to enable each LED unit to work normally, and has the advantages of larger wire usage amount, higher cost, slow debugging and low reliability.
Disclosure of Invention
The invention aims to overcome the defects in the prior art, and provides the LED driving circuit which is only used for realizing the scheme that a plurality of LED units are independently controlled, so that the production cost is greatly reduced, meanwhile, the reliability of a system is improved due to the reduction of the number of wires, and the engineering debugging is simpler. The technical scheme adopted by the invention is as follows:
an LED driving circuit comprises a voltage stabilizing source, a reference circuit, an address module, an oscillator circuit, a signal identification circuit, a data decoding circuit, a level conversion circuit, a mode control circuit and an output driving circuit;
the voltage stabilizing source is used for converting the voltage on the power line into an internal power supply and supplying the internal power supply to the data decoding circuit, the signal identification circuit and the oscillator circuit;
the reference circuit is used for generating a reference voltage VREF and outputting the reference voltage VREF to the signal identification circuit;
the address module is used for storing the inherent address of the LED driving circuit and providing the inherent address to the data decoding circuit;
the oscillator circuit is used for generating a first clock CLK and outputting the first clock CLK to the data decoding circuit;
the signal identification circuit generates an internal standard digital signal VDA according to the reference voltage VREF and the voltage signal on the power line and sends the internal standard digital signal VDA to the data decoding circuit; the internal standard digital signal VDA comprises address data and control data;
the data decoding circuit analyzes the internal standard digital signal VDA to obtain control data belonging to the LED driving circuit, and after digital level conversion is carried out by the level conversion circuit, a mode operation speed signal and an operation mode signal in the control data enter the mode control circuit, and a current control signal in the control data enter the output driving circuit; the mode control circuit controls the output driving circuit through the three primary colors enabling signal end; the three primary color output ends of the output driving circuit are used for being connected with the LEDs.
Further, the signal identification circuit comprises resistors R1, R2 and R3, a comparator U1, an inverter U2 and an NMOS tube Q1;
one end of the resistor R1 is used for being connected with the voltage VDD on the power line, the other end of the resistor R1 is connected with one end of the resistor R2 and the non-inverting input end of the comparator U1, the other end of the resistor R2 is connected with one end of the resistor R3 and the drain electrode of the NMOS tube Q1, the inverting input end of the comparator U1 is connected with the reference voltage VREF, the output end of the comparator U1 is connected with the grid electrode of the NMOS tube Q1 through the inverter U2, and the resistor R3 and the source electrode of the NMOS tube Q1 are used for grounding wires; the comparator output outputs an internal standard digital signal VDA.
Further, the method comprises the steps of,
the data decoding circuit comprises a multi-bit latch, a multi-bit shift register, an accurate clock circuit, an edge detection circuit, a start-stop detection circuit, an OR gate U3, an NOT gate U4, an RS trigger U5, a bit counter, a data counter, an address detection circuit and a data latch circuit;
the input end and the clock end of the edge detection circuit are respectively connected with an internal standard digital signal VDA and a first clock CLK to generate a DPL signal corresponding to the rising edge of the VDA;
the clock end and the reset end of the accurate clock circuit are respectively connected with the first clock CLK and the DPL signals; and generates a second clock CK190US;
the digital input END of the start-stop detection circuit is connected with an internal standard digital signal VDA, the clock is connected with a second clock CK190US, one output signal RSTB of the start-stop detection circuit is connected with one input END of an RS trigger U5 through a NOT gate U4, the other output signal END is connected with the other input END of the RS trigger U5, and the output END of the RS trigger U5 outputs an ENOM signal to the input END of an OR gate U3 and the enabling END of the mode control circuit;
one input end of the OR gate U3 is connected with a DPL signal, and the other output end is connected with a reset end of the bit counter;
the clock end of the bit counter is connected with the second clock CK190US, the output end outputs a DCK signal and sends the DCK signal to the clock end of the data counter, the clock end of the address detection circuit and the clock end of the multi-bit shift register respectively;
the reset end of the data counter is connected with an output signal RSTB of the start-stop detection circuit, and two output enabling signals D7BIT and D19BIT of the data counter are respectively connected with a data enabling end of the address detection circuit and a data enabling end of the data latch circuit; the output enable signal D19BIT is also connected with the input end of the OR gate U3;
the digital input end and the clock end of the multi-bit shift register are respectively connected with an internal standard digital signal VDA and a DCK signal, and the output is connected with the input end of the multi-bit latch and the verification bit and address input multiplexing end of the address detection circuit;
the address input end of the address detection circuit is connected with the output of the address module, the reset end of the address detection circuit is connected with an output signal RSTB of the start-stop detection circuit, and the output end of the address detection circuit is connected with the data input end of the data latch circuit and sends a DAOK signal;
the clock end of the data latch circuit is connected with the first clock CLK, and the output end of the data latch circuit is connected with the data latch signal end of the multi-bit latch;
the output of the multi-bit latch outputs control data.
The invention has the advantages that: according to the invention, the LED controllable light string in the field is changed from the current mainstream three-wire application to the two-wire application through the improved LED driving circuit, so that the engineering cost and the system debugging difficulty are reduced, the wire resources are saved, and the system reliability is improved.
Drawings
FIG. 1 is a schematic diagram of an application of a two-wire parallel LED string light of the present invention;
FIG. 2 is an electrical schematic of the present invention;
FIG. 3 is a schematic diagram of a signal recognition circuit according to the present invention;
FIG. 4 is a schematic diagram of a data decoding circuit according to the present invention;
fig. 5 is a schematic diagram of a driving circuit for a chip according to the present invention.
Detailed Description
The invention will be further described with reference to the following specific drawings and examples.
The invention is suitable for a system which needs a plurality of groups of LED lamps to be connected in parallel and can be controlled independently; the LED driving circuit and the three primary colors LED lamp form an LED unit together; the LED unit is widely used in the fields of indoor and outdoor decoration, holiday decoration lamps and the like. In fig. 3, IC represents an LED driving circuit.
The invention provides a scheme for realizing independent control of a plurality of LED units, so that the production cost is greatly reduced, meanwhile, the reliability of a system is improved due to the reduction of the number of wires, and engineering debugging is simpler;
because the LED light string is composed of the power line and the ground line, and no special data line is used for transmitting data for each LED unit, the invention designs a scheme for transmitting data by using the power line, thereby realizing the purpose of transmitting data on the power line; the scheme only needs a few elements to be added to the controller, and data is loaded on the power line according to the scheme requirement, so that the implementation method is very simple.
When the LED lamp is applied, the anodes and the cathodes of the LED units are only required to be respectively connected to a power line and a ground line driven by the controller, as shown in fig. 3; because each LED unit is provided with the LED driving circuit disclosed by the invention, the LED driving circuit can complete the task of acquiring data belonging to the LED driving circuit from a power line;
the LED driving circuit provided by the invention, as shown in figure 2, comprises a voltage stabilizing source, a reference circuit, an address module, an oscillator circuit, a signal identification circuit, a data decoding circuit, a level conversion circuit, a mode control circuit and an output driving circuit;
the voltage stabilizing source is used for converting the voltage on the power line into an internal power V2D1 and supplying the internal power V2D1 to the data decoding circuit, the signal identification circuit and the oscillator circuit;
the reference circuit is used for generating a reference voltage VREF and outputting the reference voltage VREF to the signal identification circuit;
the address module is used for storing the inherent address AD [2:0] of the LED driving circuit and providing the inherent address AD to the data decoding circuit;
the oscillator circuit is used for generating a first clock CLK and outputting the first clock CLK to the data decoding circuit;
the signal identification circuit generates an internal standard digital signal VDA according to the reference voltage VREF and the voltage signal VDD on the power line and sends the internal standard digital signal VDA to the data decoding circuit; the internal standard digital signal VDA comprises verification bits, address data and control data;
the data decoding circuit analyzes the internal standard digital signal VDA to obtain control data DA [11:0] belonging to the LED driving circuit, and after digital level conversion is carried out by the level conversion circuit, mode operation speed signals DA [11:10] and operation mode signals DA [3:0] in the control data DA [11:0] enter the mode control circuit, and current control signals DA [9:4] in the control data enter the output driving circuit; the mode control circuit controls the output driving circuit through the three primary color enabling signal terminal ENR, ENG, ENB; the three primary color output end OUTR, OUTG, OUTB of the output driving circuit is used for connecting with the LEDs;
as shown in fig. 3, the signal identifying circuit includes resistors R1, R2, R3, a comparator U1, an inverter U2, and an NMOS transistor Q1;
one end of the resistor R1 is used for being connected with the voltage VDD on the power line, the other end of the resistor R1 is connected with one end of the resistor R2 and the non-inverting input end of the comparator U1, the other end of the resistor R2 is connected with one end of the resistor R3 and the drain electrode of the NMOS tube Q1, the inverting input end of the comparator U1 is connected with the reference voltage VREF, the output end of the comparator U1 is connected with the grid electrode of the NMOS tube Q1 through the inverter U2, and the resistor R3 and the source electrode of the NMOS tube Q1 are used for grounding wires; the output end of the comparator outputs an internal standard digital signal VDA;
the data transmission scheme is used for the LED units to acquire control data belonging to the LED units, and the controller can realize effective control of each LED unit by using the data transmission scheme to transmit data; the data transmission is completed by taking a power line as a carrier, and the signal identification circuit converts voltage signals with the amplitudes of 2.5V and 5V on the power line into internal standard digital signals VDA with the internal amplitudes of 0V and 2.1V respectively;
the key to the present invention is the data decoding circuit, see FIG. 4;
the data decoding circuit comprises a 12-bit latch, a 12-bit shift register, an accurate clock circuit, an edge detection circuit, a start-stop detection circuit, an OR gate U3, an NOT gate U4, an RS trigger U5, a bit counter, a data counter, an address detection circuit and a data latch circuit;
the input end and the clock end of the edge detection circuit are respectively connected with an internal standard digital signal VDA and a first clock CLK to generate a DPL signal corresponding to the rising edge of the VDA;
the clock end and the reset end of the accurate clock circuit are respectively connected with the first clock CLK and the DPL signals; and generates a second clock CK190US; the period of the second clock CK190US is 190 μs;
the digital input END of the start-stop detection circuit is connected with an internal standard digital signal VDA, the clock END is connected with a second clock CK190US, one output signal RSTB of the start-stop detection circuit is connected with one input END of an RS trigger U5 through a NOT gate U4, the other output signal END is connected with the other input END of the RS trigger U5, the output END of the RS trigger U5 outputs an ENOM signal to the input END of an OR gate U3, and the enabling END of the mode control circuit (in FIG. 2);
one input end of the OR gate U3 is connected with a DPL signal, and the other output end is connected with a reset end of the bit counter;
the clock end of the bit counter is connected with the second clock CK190US, the output end outputs a DCK signal and sends the DCK signal to the clock end of the data counter, the clock end of the address detection circuit and the clock end of the 12-bit shift register respectively;
the reset end of the data counter is connected with one output signal RSTB of the start-stop detection circuit, and two output enabling signals D7BIT and D19BIT of the data counter are respectively connected with the data enabling end (D7 BIT in fig. 4) of the address detection circuit and the data enabling end (D19 BIT in fig. 4) of the data latch circuit; the output enable signal D19BIT is also connected with the input end of the OR gate U3;
the digital input end and the clock end of the 12-bit shift register are respectively connected with an internal standard digital signal VDA and a DCK signal, and the output is connected with the input end of the 12-bit latch and the verification bit and address input multiplexing end (DAT [6:0] in FIG. 4) of the address detection circuit;
the address input end of the address detection circuit is connected with the output end of the address module, namely AD [2:0], the reset end of the address detection circuit is connected with an output signal RSTB of the start-stop detection circuit, and the output end of the address detection circuit is connected with the data input end of the data latch circuit and sends a DAOK signal;
the clock end of the data latch circuit is connected with the first clock CLK, and the output end of the data latch circuit is connected with the data latch signal end of the 12-bit latch, namely the LCH end in FIG. 4;
the output end of the 12-bit latch outputs control data DA [11:0];
the working principle of the invention is described as follows:
the LED driving circuit (IC in figure 3) and the red, green and blue LED lamps are packaged together to form an LED unit, wherein the LED unit has two leading-out ends, a positive electrode and a negative electrode; according to the connection mode of the figure 3, the LED units are connected in parallel, and the anodes of all the LED units are connected with a power line driven by a controller and the cathodes are connected with a ground line; the number of LED units is determined according to specific needs and driving capability of the controller.
All the LED units work under the unified control of the controller, in this embodiment, the data packet sent by the controller includes a start code and 19 bits of data, where the 19 bits of data are respectively:
C3:0+AD 2:0+DA 11:0, where C3:0 is the verification bit, fixed at 1010, AD 2:0 is the address data in the packet and DA 11:0 is the control data; DA [11:10] is used for controlling the running speed of the LED mode, DA [9:8] controls the output current of the red light R, DA [7:6] controls the output current of the green light G, DA [5:4] controls the output current of the blue light B, and DA [3:0] controls the running mode of the LED. The high order first sends out when the data is sent.
Each LED unit has its own inherent address, which can be any one of 0-5, and the address is solidified in the LED driving circuit, and the specific address is determined when the circuit is time-measuring, and at the same time, each LED unit is preset with a public address 7. When the LED driving circuit receives the data packet, checking the verification bit and the address in the data packet, if the verification bit is correct and the address is the same as the intrinsic address of the LED driving circuit or the address is the public address 7, the current LED driving circuit latches the data in the data packet, and when the end code is received, the data is validated, otherwise, the data packet is ignored.
The signal recognition circuit converts the data at VDD into an internal standard digital signal VDA, and then the decoding of the data packet is completed by the data decoding circuit. The decoding circuit schematic diagram is shown in fig. 4. The start-stop detection circuit is responsible for identifying the start code and stop code, and when the duration of the low level of the VDA exceeds 20ms, the start-stop detection circuit generates an RSTB signal indicating that the start code is successfully identified and representing the start of transmission of a data packet, and at this time, the address detection module and the data counter are restored to the initial state by the RSTB signal. The ENOM signal is set to a low level, causing the LED drive circuit to stop outputting while turning on a bit counter for identifying each bit of data. The data is started by the rising edge of the VDA, the edge detection circuit outputs a DPL pulse signal at the rising edge of the VDA, resets the bit counter and the DCK signal to be low level, and simultaneously resets the accurate clock circuit, and the period of the accurate clock circuit for outputting the second clock CK190US is 190US; the bit counter counts the second clock CK190US 8 times to generate the DCK signal to become high level, at which time the bit counter stops operating, and maintains the existing state until it is reset next time and resumes operating. The value of the VDA is latched and pushed into the 12-bit shift register using the rising edge of DCK. When the data amount reaches 7 bits, the address detection circuit determines whether the current circuit requirement is satisfied, and DAT [6:3] should be a fixed value 1010, and DAT [2:0] should be the same as the internal inherent address AD [2:0] or 7. If this requirement is met, the DAOK signal goes high and the state locks, and if this requirement is not met, the DAOK signal remains low. However, the address detection circuit remains in the existing output state regardless of the state, and can not be restarted until the start code is recognized again by the start-stop detection circuit, and the RSTB signal is generated to reset the start code. When the data is decoded to 19 bits, a latch signal LDDT is generated if the DAOK signal is high, 12-bit data is latched from the 12-bit shift register to the 12-bit latch for standby, otherwise, the LDDT latch signal is not generated. But this time represents the end of a packet decoding, whether or not the latch signal LDDT is finally generated. Typically, a frame of data contains one or more packets of data. The circuit decodes each packet and determines whether it is valid. When the VDA high level continues for 20ms, the start-stop detection circuit recognizes the stop code, generates an END signal, the ENOM signal is set to a high level, which represents the END of data decoding, and the LED driving circuit starts to output normally and uses the latest received data.
The lamp string composed of a plurality of LED units can realize the integral synchronous change effect of the lamp string under the unified control of the controller, and can also enable each single-point installation to require to operate a specified mode. In addition, if the partial modes are associated with the inherent addresses of the LED units, if the light strings are arranged according to the address sequence, the whole color drifting effect such as colorful dazzling, meteor tailing, colorful brushing and the like can be achieved.
When the light string is applied, the light strings can be arranged according to the address sequence of the light string, and also can be arranged according to the self design mode of a user.
One LED unit may constitute one point of the string of lights, or a group of LED units of the same address may constitute one point of the string of lights.
Finally, it should be noted that the above-mentioned embodiments are only for illustrating the technical solution of the present invention, and not for limiting the same, and although the present invention has been described in detail with reference to examples, it should be understood by those skilled in the art that modifications and equivalents may be made to the technical solution of the present invention without departing from the spirit and scope of the technical solution of the present invention, and all such modifications and equivalents are intended to be encompassed in the scope of the claims of the present invention.
Claims (7)
1. The LED driving circuit is characterized by comprising a voltage stabilizing source, a reference circuit, an address module, an oscillator circuit, a signal identification circuit, a data decoding circuit, a level conversion circuit, a mode control circuit and an output driving circuit.
2. The LED driving circuit of claim 1, wherein,
the voltage stabilizing source is used for converting the voltage on the power line into an internal power supply and supplying the internal power supply to the data decoding circuit, the signal identification circuit and the oscillator circuit;
the reference circuit is used for generating a reference voltage VREF and outputting the reference voltage VREF to the signal identification circuit;
the address module is used for storing the inherent address of the LED driving circuit and providing the inherent address to the data decoding circuit;
the oscillator circuit is used for generating a first clock CLK and outputting the first clock CLK to the data decoding circuit;
the signal identification circuit generates an internal standard digital signal VDA according to the reference voltage VREF and the voltage signal on the power line and sends the internal standard digital signal VDA to the data decoding circuit; the internal standard digital signal VDA includes address data and control data.
3. The LED driving circuit of claim 1, wherein,
the data decoding circuit analyzes the internal standard digital signal VDA to obtain control data belonging to the LED driving circuit, and after digital level conversion is carried out by the level conversion circuit, a mode operation speed signal and an operation mode signal in the control data enter the mode control circuit, and a current control signal in the control data enter the output driving circuit; the mode control circuit controls the output driving circuit through the three primary colors enabling signal end; the three primary color output ends of the output driving circuit are used for being connected with the LEDs.
4. The LED driving circuit of claim 1, wherein,
the signal identification circuit comprises resistors R1, R2 and R3, a comparator U1, an inverter U2 and an NMOS tube Q1;
one end of the resistor R1 is used for being connected with the voltage VDD on the power line, the other end of the resistor R1 is connected with one end of the resistor R2 and the non-inverting input end of the comparator U1, the other end of the resistor R2 is connected with one end of the resistor R3 and the drain electrode of the NMOS tube Q1, the inverting input end of the comparator U1 is connected with the reference voltage VREF, the output end of the comparator U1 is connected with the grid electrode of the NMOS tube Q1 through the inverter U2, and the resistor R3 and the source electrode of the NMOS tube Q1 are used for grounding wires; the comparator output outputs an internal standard digital signal VDA.
5. An LED driving circuit according to claim 1 or 2, wherein,
the data decoding circuit comprises a multi-bit latch, a multi-bit shift register, an accurate clock circuit, an edge detection circuit, a start-stop detection circuit, an OR gate U3, an NOT gate U4, an RS trigger U5, a bit counter, a data counter, an address detection circuit and a data latch circuit;
the input end and the clock end of the edge detection circuit are respectively connected with an internal standard digital signal VDA and a first clock CLK to generate a DPL signal corresponding to the rising edge of the VDA.
6. The LED driving circuit of claim 5, wherein,
the clock end and the reset end of the accurate clock circuit are respectively connected with a first clock CLK signal and a DPL signal; and generates a second clock CK190US;
the digital input END of the start-stop detection circuit is connected with an internal standard digital signal VDA, the clock is connected with a second clock CK190US, one output signal RSTB of the start-stop detection circuit is connected with one input END of an RS trigger U5 through a NOT gate U4, the other output signal END is connected with the other input END of the RS trigger U5, and the output END of the RS trigger U5 outputs an ENOM signal to the input END of an OR gate U3 and the enabling END of the mode control circuit;
one input end of the OR gate U3 is connected with a DPL signal, and the other output end is connected with a reset end of the bit counter;
the clock end of the bit counter is connected with the second clock CK190US, the output end outputs a DCK signal and sends the DCK signal to the clock end of the data counter, the clock end of the address detection circuit and the clock end of the multi-bit shift register respectively;
the reset end of the data counter is connected with an output signal RSTB of the start-stop detection circuit, and two output enabling signals D7BIT and D19BIT of the data counter are respectively connected with a data enabling end of the address detection circuit and a data enabling end of the data latch circuit; the output enable signal D19BIT is also connected with the input end of the OR gate U3;
the digital input end and the clock end of the multi-bit shift register are respectively connected with an internal standard digital signal VDA and a DCK signal, and the output is connected with the input end of the multi-bit latch and the verification bit and address input multiplexing end of the address detection circuit;
the address input end of the address detection circuit is connected with the output of the address module, the reset end of the address detection circuit is connected with an output signal RSTB of the start-stop detection circuit, and the output end of the address detection circuit is connected with the data input end of the data latch circuit and sends a DAOK signal;
the clock end of the data latch circuit is connected with the first clock CLK, and the output end of the data latch circuit is connected with the data latch signal end of the multi-bit latch;
the output of the multi-bit latch outputs control data.
7. The LED driving circuit of claim 2, wherein,
also included in the internal standard digital signal VDA is a verification bit.
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| CN202211407315.9A CN116133184A (en) | 2022-11-10 | 2022-11-10 | LED driving circuit |
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| CN202211407315.9A CN116133184A (en) | 2022-11-10 | 2022-11-10 | LED driving circuit |
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| Publication number | Priority date | Publication date | Assignee | Title |
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| CN117542310A (en) * | 2023-11-24 | 2024-02-09 | 深圳御光新材料有限公司 | Online address writing method and device, electronic equipment and storage medium |
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| Publication number | Priority date | Publication date | Assignee | Title |
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| CN117542310A (en) * | 2023-11-24 | 2024-02-09 | 深圳御光新材料有限公司 | Online address writing method and device, electronic equipment and storage medium |
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