CN112954845A

CN112954845A - LED dimming control circuit, method, chip and lighting device

Info

Publication number: CN112954845A
Application number: CN202110166327.6A
Authority: CN
Inventors: 孙顺根
Original assignee: Shanghai Bright Power Semiconductor Co Ltd
Current assignee: Shanghai Bright Power Semiconductor Co Ltd
Priority date: 2021-02-04
Filing date: 2021-02-04
Publication date: 2021-06-11

Abstract

The invention discloses an LED dimming control circuit, a method, a chip and a lighting device. The circuit comprises: a reference current module configured to provide five reference currents; the I2C communication controller is configured to receive a clock signal and a data signal, generate five paths of I2C control information and output the control information so as to select an output channel needing to be output and provide the current and the gray scale of the selected output channel; and each constant current driving module is configured to receive corresponding reference current and corresponding I2C control information, so as to output driving signals through corresponding output channels, adjust the current and gray scale of corresponding LED lamp strings, and realize dimming control of the five LED lamp strings. The invention integrates multiple channels, can adjust light with high precision, can realize current control and can eliminate the flicker phenomenon in the light adjusting process.

Description

LED dimming control circuit, method, chip and lighting device

Technical Field

The invention relates to the technical field of electronic circuits, in particular to an integrated multi-channel LED dimming control circuit and method capable of dimming with high precision and a lighting device.

Background

Because a Light Emitting Diode (LED) Light source has the advantages of high efficiency and energy saving compared with a traditional Light source, the LED Light source is increasingly replacing the traditional Light source under the large background of energy saving and emission reduction in the global scope at present. Meanwhile, as the demand of people for life increases, Dimming (Dimming) applications are also in use. Dimming is to adjust the brightness of light emitted from an LED lamp by means of a light switch or the like according to the needs of a user.

At present, a plurality of LED lighting products based on LED dimming technology appear on the market, and are mainly used for landscape decoration lighting, architectural decoration lighting and the like. The LED linear driving dimming scheme is a simpler and direct driving application mode, has a simple circuit and small volume, and can meet more application occasions. However, the existing LED dimming control mode has the problems of poor dimming precision, flickering in the dimming process and single dimming effect mainly in a single mode.

Disclosure of Invention

The invention aims to provide an LED dimming control circuit, an LED dimming control method, an LED dimming control chip and a lighting device, aiming at the technical problems in the prior art, integrating multiple channels, realizing high-precision dimming, realizing current control and eliminating the flicker phenomenon in the dimming process.

In order to achieve the above object, the present invention provides an LED dimming control circuit, including: a reference current module configured to provide five reference currents; the I2C communication controller is configured to receive a clock signal and a data signal, generate five paths of I2C control information and output the control information so as to select an output channel needing to be output and provide the current and the gray scale of the selected output channel; the LED drive circuit comprises five constant current drive modules, wherein each constant current drive module is configured to receive corresponding reference current and corresponding I2C control information so as to output drive signals through corresponding output channels and adjust the current and gray scale of corresponding LED lamp strings, thereby realizing the dimming control of the five LED lamp strings; the I2C control information is realized by 17 bytes, wherein, the initial byte is used for configuring the circuit working mode and addressing information, the first byte is used for configuring the enabling information of each output channel, the second byte is used for configuring the range current information of the first output channel, the third byte is used for configuring the range current information of the second output channel, the fourth byte is used for configuring the range current information of the third output channel, the fifth byte is used for configuring the range current information of the fourth output channel, the sixth byte is used for configuring the range current information of the fifth output channel, the seventh byte and the eighth byte are combined for configuring the gray scale information of the first output channel, the ninth byte and the cross are combined for configuring the gray scale information of the second output channel, the eleventh byte and the twelfth byte are combined for configuring the gray scale information of the third output channel, and the thirteenth byte and the fourteenth byte are combined for configuring the gray scale information of the fourth output channel, the fifteenth byte is used in combination with the sixteenth byte to configure the grayscale information for the fifth output channel.

In order to achieve the above object, the present invention further provides an LED dimming control chip, which includes the LED dimming control circuit according to the present invention.

In order to achieve the purpose, the invention also provides a lighting device which comprises five paths of LED lamp strings and the LED dimming control chip.

In order to achieve the above object, the present invention further provides an LED dimming control method, which employs the LED dimming control circuit described in the present application; the method comprises the following steps: (1) providing five reference currents through a reference current module; (2) receiving a clock signal and a data signal through an I2C communication controller, generating five paths of I2C control information and outputting the control information so as to select an output channel needing to be output and provide the current and the gray scale of the selected output channel; (3) the five constant-current driving modules respectively receive corresponding reference current and corresponding I2C control information, so that driving signals are output through corresponding output channels, the current and the gray scale of corresponding LED lamp strings are adjusted, and dimming control of the five LED lamp strings is achieved; wherein, the I2C control information is implemented by 17 bytes, the initial byte is used for configuring the circuit working mode and addressing information, the first byte is used for configuring the enabling information of each output channel, the second byte is used for configuring the range current information of the first output channel, the third byte is used for configuring the range current information of the second output channel, the fourth byte is used for configuring the range current information of the third output channel, the fifth byte is used for configuring the range current information of the fourth output channel, the sixth byte is used for configuring the range current information of the fifth output channel, the seventh byte and the eighth byte are combined for configuring the gray scale information of the first output channel, the ninth byte and the cross are combined for configuring the gray scale information of the second output channel, the eleventh byte and the twelfth byte are combined for configuring the gray scale information of the third output channel, the thirteenth byte and the fourteenth byte are combined for configuring the gray scale information of the fourth output channel, the fifteenth byte is used in combination with the sixteenth byte to configure the grayscale information for the fifth output channel.

To achieve the above object, the present invention further provides a storage medium having a computer program stored thereon, wherein the computer program, when executed by a processor, implements the steps of the LED dimming control method according to the present invention.

In order to achieve the above object, the present invention further provides a computer device, which includes a processor and a memory, where the memory stores a computer program operable on the processor, and the processor executes the computer program to implement the steps of the LED dimming control method according to the present invention.

The invention has the advantages that: the I2C communication controller is adopted to provide 5 paths of I2C control information through an I2C protocol to accurately control the output currents of 5 output channels, so that the current control of 1024-level gray scale of each output channel can be realized, the flicker phenomenon in the dimming process can be eliminated, and intelligent dimming is realized. The maximum output current of each output channel is 90mA, and five paths of maximum output current are independently set and the maximum output current is set to be 1 mA/Step; and five paths of output current individual enabling control are supported. The ultra-low standby power consumption can be realized, and the working current of the sleep mode is less than 100 uA.

Drawings

In order to more clearly illustrate the technical solutions in the embodiments of the present invention, the drawings used in the description of the embodiments will be briefly introduced below. It is obvious that the drawings in the following description are only some embodiments of the invention, and that for a person skilled in the art, other drawings can be derived from them without inventive effort.

Fig. 1 is a schematic diagram of an LED dimming control circuit according to an embodiment of the present invention;

FIGS. 2A-2D are schematic diagrams of byte setup information according to the present invention;

FIG. 3 is a schematic diagram of an input signal waveform according to the present invention;

FIG. 4 is a schematic diagram of control waveforms for start and stop states according to the present invention;

FIG. 5 is a diagram illustrating control waveforms for data transmission according to the present invention;

FIG. 6 is a schematic diagram of an LED dimming control chip according to an embodiment of the present invention;

FIG. 7 is a schematic view of an embodiment of a lighting device of the present invention;

FIG. 8 is a flowchart illustrating an LED dimming control method according to an embodiment of the present invention;

FIG. 9 is a schematic diagram of the internal structure of the computer device of the present invention.

Detailed Description

The technical solution in the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings. It is to be understood that the described embodiments are merely exemplary of the invention, and not restrictive of the full scope of the invention. All other embodiments, which can be derived by a person skilled in the art from the embodiments given herein without making any creative effort, shall fall within the protection scope of the present invention. The terms "first," "second," "third," and the like in the description and in the claims, as well as in the drawings, if any, are used for distinguishing between similar elements and not necessarily for describing a particular sequential or chronological order. Furthermore, the terms "comprises," "comprising," and any variations thereof, are intended to cover a non-exclusive inclusion. In the description of the present invention, "a plurality" means two or more unless specifically defined otherwise.

In the description of the present invention, it is to be noted that the terms "connected" and "connected" are to be interpreted broadly unless explicitly defined or limited otherwise. For example, the components may be electrically connected or in communication with each other, directly or indirectly through intervening media, or may be in communication within or interacting with each other. It will be understood that when an element is referred to as being "coupled" to another element, there are intervening elements present. The specific meanings of the above terms in the present invention can be understood by those skilled in the art according to specific situations.

Please refer to fig. 1, which is a schematic diagram of an LED dimming control circuit according to an embodiment of the present invention. The circuit 10 comprises: a reference current module (current reference)11, an I2C communication controller 12, and five constant current driving modules 131-135.

The reference current module 11 is configured to provide five reference currents Iref 1-Iref 5. Specifically, each reference current is correspondingly provided to one path of constant current driving module.

The I2C communication controller 12 is configured to receive a clock signal SCL and a data signal SDA, generate five paths of I2C control information CDout 1-CDout 5 and output the same, to select output channels OUT 1-OUT 5 which need to be output, and to provide current and gray scale of the selected output channels.

Each of the constant current driving modules 131 to 135 is configured to receive corresponding reference currents Iref1 to Iref5 and corresponding I2C control information CDout1 to CDout5, so as to output driving signals through corresponding output channels OUT1 to OUT5, adjust currents and gray scales of corresponding LED strings LEDs 1 to LED5, and implement dimming control of five LED strings LEDs 1 to LED 5. For example, the first output channel OUT1 outputs a driving signal to adjust the blue LED string LED1, the second output channel OUT2 outputs a driving signal to adjust the green LED string LED2, the third output channel OUT3 outputs a driving signal to adjust the red LED string LED3, the fourth output channel OUT4 outputs a driving signal to adjust the warm white LED string LED4, and the fifth output channel OUT5 outputs a driving signal to adjust the cold white LED string LED 5.

The I2C control information CDout 1-CDout 5 are realized by 17 bytes: the initial Byte0 is used to configure the circuit operation mode (sleep mode or operation mode) and addressing information; the first Byte1 is used for configuring enable information of each output channel OUT 1-OUT 5, the second Byte2 is used for configuring range current information of the first output channel OUT1, the third Byte3 is used for configuring range current information of the second output channel OUT2, the fourth Byte4 is used for configuring range current information of the third output channel OUT3, the fifth Byte5 is used for configuring range current information of the fourth output channel OUT4, and the sixth Byte6 is used for configuring range current information of the fifth output channel OUT 5; the seventh Byte7 is combined with the eighth Byte8 to configure gray scale information of the first output channel OUT1, the ninth Byte9 is combined with the cross Byte10 to configure gray scale information of the second output channel OUT2, the eleventh Byte11 is combined with the twelfth Byte12 to configure gray scale information of the third output channel OUT3, the thirteenth Byte13 is combined with the fourteenth Byte14 to configure gray scale information of the fourth output channel OUT4, and the fifteenth Byte15 is combined with the sixteenth Byte16 to configure gray scale information of the fifth output channel OUT 5.

In a further embodiment, the initial Byte, Byte0, includes 8 bits (Bit) of data; among them, the 7 th to 8 th bits B0[7:6] are identification bits, the 5 th to 6 th bits B0[5:4] are circuit operation mode control bits, and the 1 st to 5 th bits B0[3:0] are addressing bits, as shown in FIG. 2A. Wherein, the 5 th to 6 th bits B0[5:4] of the initial Byte0 are configured to control the circuit to enter a sleep mode (when no dimming operation is performed) or to enter an operation mode.

Specifically, B0[7:6] ═ 10 is the identification bit of Byte 0. B0[5:4] ═ 01 indicates a Sleep Mode (Sleep Mode), and the other state values indicate an operation Mode. B0[3:0] ═ 0000: addressing selects the first Byte1 for enabling setting of each output channel OUT1 OUT5, other state values can be addressed directly to either the span current setting address or the gray level setting address of the corresponding output channel. For example, B0[3:0] ═ 0001: span set address addressed to the first output channel OUT1, B0[3:0] — 0010: span set address addressed to the second output channel OUT2, B0[3:0] — 0011: span set address addressed to the third output channel OUT3, B0[3:0] ═ 0100: the span setting address addressed to the fourth output channel OUT4, B0[3:0] ═ 0101: a span setting address addressed to the fifth output channel OUT 5; b0[3:0] ═ 0110: gray setting address addressed to the first output channel OUT1, B0[3:0] ═ 1000: the gray setting address addressed to the second output channel OUT2, B0[3:0] ═ 1010: gray setting address addressed to the third output channel OUT3, B0[3:0] ═ 1100: the gray setting address addressed to the fourth output channel OUT4, B0[3:0] ═ 1110: the gray scale setting address addressed to the fifth output channel OUT 5.

In a further embodiment, the first Byte Byte1 includes 8-Bit (Bit) data, where bits 1 through 5B 1[4:0] are used to configure whether each output channel is enabled, as shown in FIG. 2B. Wherein B1[7:5] is invalid Bit and can be input arbitrarily.

For example, B1[0] is used to make the first output channel OUT1 enable setting: b1[0] ═ 1 is Enable (Enable), which represents that the channel is allowed to operate; b1[0] is disabled (Disable), indicating that the channel is not working. B1[1] is used to make the second output channel OUT2 enable setting: b1[1] ═ 1 is enable, B1[1] ═ 0 is disable; b1[2] is used to make the third output channel OUT3 enable setting: b1[2] ═ 1 is enable, B1[2] ═ 0 is disable; b1[3] is used to make the fourth output channel OUT4 enable setting: b1[3] ═ 1 is enable, B1[3] ═ 0 is disable; b1[4] is used to make the fifth output channel OUT5 enable setting: b1[4] ═ 1 is enable, and B1[4] ═ 0 is disable. Alternatively, the default value is B1[4:0] ═ 00000, that is, all of the five output channels OUT1 to OUT5 are disabled.

In a further embodiment, the second Byte2 through the sixth Byte6 each include 8 bits (Bit) of data; the range current of each output channel OUT 1-OUT 5 is configured by configuring the 1 st to 7 th bits B [6:0] of the corresponding byte, and the configurable range of the range current of each output channel is 0-90 mA.

Taking the second Byte2 as an example, the range current (maximum outputable current) of the first output channel OUT1 is configured by configuring its 1 st to 7 th bits B2[6:0], as shown in FIG. 2C. For example, B2[6:0] ═ 0000000: the range current of the first output channel OUT1 is 0 mA; b2[6:0] ═ 0000001: the range current of the first output channel OUT1 is 1 mA; b2[6:0] ═ 0000010: the range current of the first output channel OUT1 is 2 mA; b2[6:0] ═ 0000011: the range current of the first output channel OUT1 is 3 mA; b2[6:0] ═ 0000100: the range current of the first output channel OUT1 is 4 mA; …, respectively; b2[6:0] ═ 0001000: the range current of the first output channel OUT1 is 8 mA; …, respectively; b2[6:0] ═ 0010000: the range current of the first output channel OUT1 is 16 mA; …, respectively; b2[6:0] ═ 0100000: the current of the first output channel OUT1 is the range of 32 mA; …, respectively; b2[6:0] ═ 0111111: the current of the first output channel OUT1 is the range 63 mA; b2[6:0] ═ 1100010: the current of the first output channel OUT1 is the range of 64 mA; b2[6:0] ═ 1100011: the current of the first output channel OUT1 is the range of 65 mA; …, respectively; b2[6:0] ═ 1111100: the span current of the first output channel OUT1 is 90 mA. Optionally, the default value is B2[6:0] ═ 0001010: the first output channel OUT1 has a span current of 10 mA. The setting of B2[7] does not affect the setting of the range current.

The third Byte3 through the sixth Byte6 correspond to the configurations of the span currents of the second output channel OUT2 through the fifth output channel OUT5, and the configuration method can refer to the configuration of the second Byte 2. The default values of the range currents of the second output channel OUT2 to the fifth output channel OUT5 are also 10 mA.

In a further embodiment, the seventh Byte7 through the sixteenth Byte16 each include 8-Bit (Bit) data, and two bytes are used to configure the gray scale information of the same output channel. In two bytes used for configuring the gray scale information of the same output channel, the 1 st to 5 th bits B [4:0] of the next byte and the 1 st to 5 th bits B [4:0] of the previous byte are combined for correspondingly configuring the gray scale of the corresponding output channel, and the gray scale configurable range of each output channel is 0-1023 levels.

Taking the seventh Byte7 through the eighth Byte8 for configuring the gray information of the first output channel OUT1 as an example, the gray information of the output channel OUT1 is configured by configuring the 1 st through 5 th bits B8[4:0] of the eighth Byte8 and the 1 st through 5 th bits B7[4:0] of the seventh Byte7, as shown in fig. 2D. For example, B8[4:0] B7[4:0] ═ 0000000000: the output gray scale of the first output channel OUT1 is 0 level (0/1024); b8[4:0] B7[4:0] ═ 0000000001: the output gray scale of the first output channel OUT1 is 1 level (1/1024); b8[4:0] B7[4:0] ═ 0000000010: the output gray scale of the first output channel OUT1 is 2 levels (2/1024); …, respectively; b8[4:0] B7[4:0] ═ 1111111110: the output gray scale of the first output channel OUT1 is 1022 levels (1022/1024); b8[4:0] B7[4:0] ═ 1111111111: the output gray scale of the first output channel OUT1 is 1023 levels (1023/1024). That is, the gray scale of the first output channel OUT1 may be adjustable at 1024 levels. Optionally, the default value is B8[4:0] B7[4:0] ═ 0000000000.

The ninth Byte9 and the cross Byte10 output gray level setting bytes for the second output channel OUT 2; the eleventh Byte11 and the twelfth Byte12 are used for outputting current gray level setting bytes for the third output channel OUT3, the Byte13-Byte14 are used for outputting current gray level setting bytes for the fourth output channel OUT4, and the Byte15-Byte16 are used for outputting current gray level setting bytes for the fifth output channel OUT 5. The configuration method can refer to the configuration of the output gray scale of the first output channel OUT 1. The output gray level default values of the second output channel OUT 2-the fifth output channel OUT5 are also 0 level.

With continued reference to fig. 1, the circuit 10 further includes a power supply module 14 configured to receive an external input voltage Vin to provide an operating voltage for the circuit 10. Wherein, when the external input voltage Vin is greater than a preset voltage threshold (for example, 10V), the I2C communication controller 12 enters an operating state; and when the clock signal SCL and the data signal SDA have no signal input, controlling the circuit 10 to enter a sleep mode. For example, the circuit has a pull-down current of about 1mA in the starting process, and when the external input voltage Vin is greater than 8V, the power supply module 14 starts to work; when the external input voltage Vin is greater than 9.8V, the circuit 10 starts to work formally, waiting for the clock signal SCL and the data signal SDA to be input. If there is no signal input of the clock signal SCL and the data signal SDA, the circuit 10 enters the sleep mode; at this time, the operating current of the circuit 10 is about 85uA, and the power consumption is low. When the clock signal SCL and the data signal SDA have signal inputs, the circuit 10 exits the sleep mode, and then performs the smart dimming control by controlling the clock signal SCL and the data signal SDA.

In a further embodiment, the I2C control information further includes start state control information, stop state control information, and data transmission control information.

Specifically, the start state control information is that the level of the data signal SDA changes from high to low when the clock signal SCL is high; the stop state control information is that the level of the data signal SDA is changed from low to high when the clock signal SCL is at high level; the data transmissionThe control information is that the level state of the data signal SDA remains unchanged when the clock signal SCL is high. The ports of the I2C communication controller 12 for receiving the clock signal SCL and the data signal SDA are respectively provided with a pull-up resistor R_SDA、R_SCL. Pull-up resistor R_SDA、R_SCLThe resistance value range of the resistor can be 12-18 kOhm.

Specifically, the data transmission control information further includes: when the level of the clock signal SCL changes from low to high, data reading is carried out on the data signal SDA and the data signal SDA is written into a register; generating a corresponding response signal ACK every time the data transmission of one byte is completed; the level of the data signal SDA is pulled down by the acknowledgement signal ACK. Preferably, after the level of the clock signal SCL changes from low to high, DATA reading is performed on the DATA signal SDA after a delay of a preset noise immunity time, and the read DATA is written into a register for latching according to a LATCH control signal DATA _ LATCH.

Referring to fig. 3 to 5, fig. 3 is a schematic diagram of an input signal waveform of the present invention, fig. 4 is a schematic diagram of a start/stop state control waveform of the present invention, and fig. 5 is a schematic diagram of a data transmission control waveform of the present invention.

As shown in fig. 3, every time the transmission of 8-Bit (Bit) data is completed, at the 9 th clock, the inside of the circuit generates an acknowledge signal ACK, which pulls the data signal SDA low. Namely, each time the data transmission of one byte (8Bit) is completed, a response signal is correspondingly generated; the transfer of one Byte (Byte) is completed by 9 clock cycles (8Bit +1ACK) of the clock signal SCL input.

As shown in fig. 4, the data signal SDA and the clock signal SCL are both high, which is called an idle state; when the clock signal SCL is high, when the data signal SDA is a falling edge (the level goes from high to low), this is the START condition (START) of the control; when the clock signal SCL is high, it is the STOP condition (STOP) of the control when the data signal SDA is a rising edge (the level goes from low to high). When the clock signal SCL is input for 9 clock cycles (8Bit +1ACK), the transmission of one Byte (Byte) is completed; if no addressing is performed, a total of 17 bytes (bytes) can be input. In the figure, tsu.sta represents the set-up time of the start condition, thd.sta represents the retention time of the start condition, tsu.sto represents the set-up time of the stop condition, and thd.sto represents the set-up time of the stop condition. Preferably tsu.sta, thd.sta, tsu.sto, thd.sto is greater than or equal to 250nS (nanoseconds).

As shown in fig. 5, the I2C communication protocol performs serial Bit transfers, with one Bit (Bit) of data being transferred per clock pulse. The data signal SDA must remain stable when the clock signal SCL is high, and the data signal SDA can change state only when the clock signal SCL is low. When the clock signal SCL changes from low to high (at a rising edge), data is written to the register. Every time the transmission of 8-Bit (Bit) data is completed, at the 9 th clock, the internal circuit generates an acknowledge signal ACK which pulls the data signal SDA low.

IN order to prevent signal interference, the read-IN control signal DATA _ IN is an effective DATA read-IN control signal when the DATA signal SDA is read IN; namely, after delaying a preset noise interference resisting time tsam.dat after the level of the clock signal SCL changes from low to high, DATA reading is performed on the DATA signal SDA according to the read-IN control signal DATA _ IN. The read-IN DATA signal is controlled to be latched by a LATCH control signal DATA _ LATCH delayed by a LATCH noise interference resistance time tlat with respect to the read-IN control signal DATA _ IN. In the figure, tsu.sta represents the set-up time of the start condition, Tlow represents the pulse width of the low level of the clock signal SCL, Thigh represents the pulse width of the high level of the clock signal SCL, thd.dat represents the holding time of the data input, Tr represents the rising time of the data input, Tf represents the falling time of the data input, tsu.sto represents the set-up time of the stop condition, thd.sta represents the holding time of the start condition, tsu.dat represents the set-up time of the data input, tsam.dat represents the anti-noise interference time, and tlat represents the latch anti-noise interference time. Preferably, thd.sta, tsu.dat are greater than or equal to 250nS (nanoseconds) and Tlow, Thigh are greater than or equal to 1.5uS (microseconds).

When data is transmitted, each 8-Bit (Bit) data is a byte, the control information corresponding to each byte is as shown in fig. 2A to 2D, and all input information can be completed by 17 bytes. The 18 th Byte (Byte17) is actually the setting information to jump to the aforementioned Byte 1; that is, the setting information behind the Byte17 is the aforementioned repeated setting of the Byte1-Byte 16. Therefore, when the stop control operation is not performed, the valid input byte is 17 bytes.

The circuit provided by the embodiment adopts an I2C communication controller to provide 5 paths of I2C control information through an I2C protocol to accurately control the output currents of 5 output channels, so that 1024-level gray scale current control of each output channel can be realized, the flicker phenomenon in the dimming process can be eliminated, and intelligent dimming is realized. The maximum output current of each output channel is 90mA, and five paths of maximum output current are independently set and the maximum output current is set to be 1 mA/Step; and five paths of output current individual enabling control are supported. The ultra-low standby power consumption can be realized, and the working current of the sleep mode is less than 100 uA. The circuit provided by the embodiment can be applied to intelligent dimming of LED intelligent bulbs, LED intelligent colored filament lamps and other LED intelligent lighting devices.

Based on the same invention concept, the invention also provides an LED dimming control chip, and the LED dimming control circuit is adopted.

Please refer to fig. 6, which is a schematic diagram of an LED dimming control chip according to an embodiment of the present invention. In the embodiment, the LED dimming control chip 60 is packaged in an ESOP-8 manner, and 8 pins 1 to 8 are sequentially a first constant current output port OUT1, a chip power input port HV, a data signal input port SDA, a clock signal input port SCL, a fifth constant current output port OUT5, a fourth constant current output port OUT4, a third constant current output port OUT3, and a second constant current output port OUT 2. And the substrate of the LED dimming control chip 60 serves as the chip ground GND. The LED dimming control chip 60 is internally provided with the LED dimming control circuit 10 of the present invention. For the connection manner and the operation principle of the components of the LED dimming control circuit 10, reference is made to the foregoing description, and details are not repeated here.

Wherein, power tubes are integrated in the LED dimming control chip 60 corresponding to each channel. The voltage range of the port OUT1/2/3/4/5 is-0.3-500V; the maximum current of the drain electrode of each power tube in the channel is 90mA (namely the maximum output current of each output channel is 90 mA); the voltage ranges of the data signal input port SDA and the clock signal input port SCL are-0.3-9V; the voltage range of the chip power supply input port HV is-0.3-500V; the working range of the LED dimming control chip 60 is-40-105 ℃.

The LED dimming control chip 60 has an over-temperature adjustment function, and when the driving power supply is overheated, the output current can be gradually reduced, so as to control the output power and the temperature rise, and keep the power supply temperature at a set value, thereby improving the reliability of the system.

In the LED dimming control chip 60, the area of the heat dissipation copper sheet of the substrate of the chip ground GND is as large as possible (larger than a preset area threshold) to reduce the thermal resistance and enhance the heat dissipation capability. A data signal input port SDA and a clock signal input port SCL in the LED dimming control chip 60 are wired into the MCU through pins to obtain corresponding signals; the pin trace is as short as possible (smaller than a preset length threshold) to avoid interference of noise signals to digital signals. Since the chip power input port HV in the LED dimming control chip 60 is a high-voltage port, the distance between the chip power input port HV and other low-voltage signal traces (such as SDA traces, SCL traces, etc.) needs to be as large as possible (larger than the preset distance threshold), so as to achieve electrical isolation and avoid high-voltage breakdown.

The chip provided by the embodiment of the invention adopts the LED dimming control circuit, 5 paths of I2C control information are provided through an I2C protocol to accurately control the output currents of 5 output channels, 1024-level gray scale current control of each output channel can be realized, and the flicker phenomenon in the dimming process can be eliminated. And intelligent dimming is realized. The maximum output current of each output channel is 90mA, and five paths of maximum output current are independently set and the maximum output current is set to be 1 mA/Step; and five paths of output current individual enabling control are supported. The ultra-low standby power consumption can be realized, and the working current of the sleep mode is less than 100 uA.

Based on the same inventive concept, the invention also provides a lighting device, which adopts the LED dimming control chip.

Please refer to fig. 7, which is a schematic diagram of an illumination device according to an embodiment of the invention. The lighting device 70 of the present embodiment includes five LED strings, LEDs 1-LEDs 5, and an LED dimming control chip 71. The LED dimming control chip 71 adopts the LED dimming control chip 60 shown in fig. 6 of the present invention, and the LED dimming control circuit 10 shown in fig. 1 of the present invention is disposed therein. For technical details which are not described in detail in this embodiment, reference may be made to the above-described embodiments.

The lighting device 70 further includes an MCU, which is connected (e.g. by pin wiring) with the data signal input port SDA and the clock signal input port SCL of the LED dimming control chip 71 to provide corresponding signals. The five LED lamp strings LED 1-LED 5 can be intelligent color filament lamps; for example: a blue LED string LED1, a green LED string LED2, a red LED string LED3, a warm white LED string LED4, and a cold white LED string LED 5.

The illumination device 70 of the present invention is further explained with reference to fig. 2A to 2D and fig. 7.

The first embodiment is as follows: the LED dimming control chip 71 enters a Sleep Mode (Sleep Mode) without dimming operation. Specifically, the input program of the MCU is as follows:

start: 10000000 (write Byte0, where B0[5:4] ═ 00 goes into sleep mode)

Stop。

Example two: 5 output channels OUT 1-OUT 5 are selected to be output simultaneously; the maximum currents of OUT 1-OUT 3 are 40mA, the gray scale of OUT1 is 2/1024, the gray scale of OUT2 is 512/1024, and the gray scale of OUT3 is 1022/1024; OUT 4-OUT 5 maximum current 60mA, OUT4 gray 512/1024, OUT5 gray 1022/1024. Specifically, the input program of the MCU is as follows:

start: 10110000 (write Byte0, Normal mode, select Byte1)

00011111 (write Byte1, set OUT1 OUT5 output Enable)

00101000 (write Byte2, set OUT1 Range Current 40mA)

00101000 (write Byte3, set OUT2 Range Current 40mA)

00101000 (write Byte4, set OUT3 Range Current 40mA)

00111100 (write Byte5, set OUT4 Range Current 60mA)

00111100 (write Byte6, set OUT5 Range Current 60mA)

10100010 (write Byte7)

10100000 (writing Byte8, Byte7 and Byte8 together set OUT1 grayscale 2/1024)

10100000 (write Byte9)

10110000 (writing Byte10, Byte9 and Byte10 together set OUT2 grayscale 512/1024)

10111110 (write Byte11)

10111111 (writing Byte12, Byte11 and Byte12 together set OUT3 grayscale 1022/1024)

10100000 (write Byte13)

10110000 (writing Byte14, Byte13 and Byte14 together set OUT4 grayscale 512/1024)

10111110 (write Byte15)

10111111 (writing Byte16, Byte15 and Byte16 together set OUT5 grayscale 1022/1024)

Stop。

Example three: the output of the selected output channels OUT 4-OUT 5 is realized at the same time; the maximum current of OUT 4-5 is 60mA, the gray scale of OUT4 is 2/1024, and the gray scale of OUT5 is 512/1024; after 1mS, OUT4 grayscale 512/1024, OUT5 grayscale 2/1024. Specifically, the input program of the MCU is as follows:

start 1: 10110000 (write Byte0, Normal mode, select Byte1)

00011000 (write Byte1, set OUT1 OUT3 output invalid, OUT4 OUT5 output valid)

00000000 (write Byte2, set OUT1 Range Current 0mA)

00000000 (write Byte3, set OUT2 Range Current 0mA)

00000000 (write Byte4, set OUT3 Range Current 0mA)

00111100 (write Byte5, set OUT4 Range Current 60mA)

00111100 (write Byte6, set OUT5 Range Current 60mA)

Stop1 (here indicating the separation between frames)

Start 2: 10111100 (write Byte0, Normal mode, select Byte13)

10100010 (write Byte13)

10100000 (writing Byte14, Byte13 and Byte14 together set OUT4 grayscale 2/1024)

10100000 (write Byte15)

10110000 (writing Byte16, Byte15 and Byte16 together set OUT5 grayscale 512/1024)

Stop2

Start 3: 10111100 (write Byte0, Normal mode, select Byte13)

10100000 (write Byte13)

10100010 (write Byte15)

10100000 (writing Byte16, Byte15 and Byte16 together set OUT5 grayscale 2/1024)

Stop3。

In the embodiment, 5 paths of I2C control information are provided through an I2C protocol to accurately control the output currents of 5 output channels, so that the current control of 1024-level gray scale of each output channel can be realized, and the flicker phenomenon in the dimming process can be eliminated. And intelligent dimming is realized. The maximum output current of each output channel is 90mA, and five paths of maximum output current are independently set and the maximum output current is set to be 1 mA/Step; and five paths of output current individual enabling control are supported. The ultra-low standby power consumption can be realized, and the working current of the sleep mode is less than 100 uA.

Based on the same invention concept, the invention also provides an LED dimming control method, and the LED dimming control circuit is adopted.

Please refer to fig. 8, which is a flowchart illustrating an LED dimming control method according to an embodiment of the present invention. The method of the embodiment comprises the following steps: s81, providing five reference currents through the reference current module; s82, receiving the clock signal and the data signal through the I2C communication controller, generating and outputting five paths of I2C control information to select an output channel needing to be output and provide the current and the gray scale of the selected output channel; and S83, receiving corresponding reference current and corresponding I2C control information through the five-path constant current driving module respectively, so as to output driving signals through corresponding output channels, adjust the current and gray scale of corresponding LED lamp strings and realize the dimming control of the five-path LED lamp strings.

Wherein the I2C control information is implemented using 17 bytes: the initial Byte0 is used to configure the circuit operation mode (sleep mode or operation mode) and addressing information; the first Byte1 is used for configuring enable information of each output channel OUT 1-OUT 5, the second Byte2 is used for configuring range current information of the first output channel OUT1, the third Byte3 is used for configuring range current information of the second output channel OUT2, the fourth Byte4 is used for configuring range current information of the third output channel OUT3, the fifth Byte5 is used for configuring range current information of the fourth output channel OUT4, and the sixth Byte6 is used for configuring range current information of the fifth output channel OUT 5; the seventh Byte7 is combined with the eighth Byte8 to configure gray scale information of the first output channel OUT1, the ninth Byte9 is combined with the cross Byte10 to configure gray scale information of the second output channel OUT2, the eleventh Byte11 is combined with the twelfth Byte12 to configure gray scale information of the third output channel OUT3, the thirteenth Byte13 is combined with the fourteenth Byte14 to configure gray scale information of the fourth output channel OUT4, and the fifteenth Byte15 is combined with the sixteenth Byte16 to configure gray scale information of the fifth output channel OUT 5. The specific arrangement of each byte can be referred to fig. 2A to fig. 2D, and is not described herein again.

In a further embodiment, the method further comprises: and S80, receiving an external input voltage, controlling the I2C communication controller to enter a working state when the external input voltage is larger than a preset voltage threshold, and controlling the circuit to enter a sleep mode when no signal is input in the clock signal and the data signal. For example, the circuit has a pull-down current of about 1mA in the starting process, and when the external input voltage Vin is greater than 8V, the power supply module of the circuit starts to work; when the external input voltage Vin is greater than 9.8V, the circuit starts to work formally, and waits for the signal input of the clock signal SCL and the data signal SDA. If no clock signal SCL and no data signal SDA are input, the circuit enters a sleep mode; at the moment, the working current of the circuit is about 85uA, and the power consumption is low. When the clock signal SCL and the data signal SDA have signal inputs, the circuit exits the sleep mode, and then performs the smart dimming control by controlling the clock signal SCL and the data signal SDA.

In a further embodiment, the step S82 further includes: 1) when the level of the clock signal changes from low to high, serial bit transmission is carried out, data reading is carried out on the data signal, and the data signal is written into a register; 2) generating a corresponding response signal every time a byte of data transmission is completed; 3) the level of the data signal is pulled down by the reply signal. Preferably, after the level of the clock signal changes from low to high, the data signal is read after a preset anti-noise interference time is delayed, and the read data is written into the register to be latched according to the latch control signal.

Specifically, every time the transmission of 8-Bit (Bit) data is completed, at the 9 th clock, the inside of the circuit generates an acknowledge signal ACK which pulls the data signal SDA low, as shown in fig. 3. Namely, each time the data transmission of one byte (8Bit) is completed, a response signal is correspondingly generated; the transfer of one Byte (Byte) is completed by 9 clock cycles (8Bit +1ACK) of the clock signal SCL input.

Specifically, the data signal SDA and the clock signal SCL are both high, which is called an idle state; when the clock signal SCL is high, when the data signal SDA is a falling edge (the level goes from high to low), this is the START condition (START) of the control; when the clock signal SCL is high, it is a STOP condition (STOP) for control when the data signal SDA is a rising edge (the level goes from low to high), as shown in fig. 4. When the clock signal SCL is input for 9 clock cycles (8Bit +1ACK), the transmission of one Byte (Byte) is completed; if no addressing is performed, a total of 17 bytes (bytes) can be input.

Specifically, the I2C communication protocol performs serial Bit transfers, with one Bit (Bit) of data being transferred per clock pulse. The data signal SDA must remain stable when the clock signal SCL is high, and the data signal SDA can change state only when the clock signal SCL is low. When the clock signal SCL changes from low to high (at a rising edge), data is written to the register. Every time the transmission of 8-Bit (Bit) data is completed, at the 9 th clock, the internal circuit generates an acknowledge signal ACK, which pulls the data signal SDA low, as shown in fig. 5.

IN order to prevent signal interference, after delaying a preset anti-noise interference time tsam.dat after the level of the clock signal SCL changes from low to high, DATA reading is performed on the DATA signal SDA according to the read-IN control signal DATA _ IN. The read-IN DATA signal is controlled to be latched by a LATCH control signal DATA _ LATCH delayed by a LATCH noise interference resistance time tlat with respect to the read-IN control signal DATA _ IN.

The method provided by the embodiment adopts the I2C communication controller to provide 5 paths of I2C control information through the I2C protocol to accurately control the output currents of 5 output channels, can realize the current control of 1024-level gray scale of each output channel, and can eliminate the flicker phenomenon in the dimming process. And intelligent dimming is realized. The maximum output current of each output channel is 90mA, and five paths of maximum output current are independently set and the maximum output current is set to be 1 mA/Step; and five paths of output current individual enabling control are supported. The ultra-low standby power consumption can be realized, and the working current of the sleep mode is less than 100 uA.

Based on the same inventive concept, the invention also provides computer equipment capable of realizing the LED dimming control method.

Please refer to fig. 9, which is a schematic diagram of an internal structure of a computer apparatus according to the present invention. As shown in fig. 9, the computer device 90 according to the present embodiment includes a processor, a memory, a network interface, a display screen, and an input device, which are connected via a system bus. Wherein the processor of the computer device 90 is configured to provide computing and control capabilities. The memory of the computer device 90 includes a nonvolatile storage medium, an internal memory. The non-volatile storage medium stores an operating system and a computer program. The internal memory provides an environment for the operation of an operating system and computer programs in the non-volatile storage medium. The network interface of the computer device 90 is used to communicate with an external computer device via a network connection. Which when executed by a processor may carry out the steps of the model component clicking method of the invention. The display screen of the computer device 90 may be a liquid crystal display screen or an OLED display screen, and the input device of the computer device 90 may be a touch layer covered on the display screen, a key, a trackball or a touch pad arranged on a housing of the computer device 90, or an external keyboard, a touch pad or a mouse.

It will be appreciated by those skilled in the art that the configuration shown in fig. 9 is a block diagram of only a portion of the configuration associated with the inventive arrangements and does not constitute a limitation of the computing device 90 to which the inventive arrangements may be applied, and that a particular computing device 90 may include more or less components than those shown, or may combine certain components, or have a different arrangement of components.

In one embodiment, the computer device 90 comprises a memory having a computer program stored therein and a processor implementing the steps of the LED dimming control method of the present invention when the processor executes the computer program.

In one embodiment, a storage medium is also provided. The storage medium has stored thereon a computer program which, when executed by a processor, implements the steps of the LED dimming control method of the present invention. It will be understood by those skilled in the art that all or part of the processes of the above-described method for controlling LED dimming can be implemented by a computer program, which can be stored in a non-volatile computer readable storage medium, and can include the processes of the above-described embodiments of the LED dimming control method.

Any reference to memory, storage, database or other medium used in embodiments provided herein may include non-volatile and/or volatile memory. Non-volatile memory can include read-only memory (ROM), Programmable ROM (PROM), Electrically Programmable ROM (EPROM), Electrically Erasable Programmable ROM (EEPROM), or flash memory. Volatile memory can include Random Access Memory (RAM) or external cache memory.

In the foregoing embodiments, the descriptions of the respective embodiments have respective emphasis, and for parts that are not described in detail in a certain embodiment, reference may be made to related descriptions of other embodiments.

The foregoing is only a preferred embodiment of the present invention, and it should be noted that, for those skilled in the art, various modifications and decorations can be made without departing from the principle of the present invention, and these modifications and decorations should also be regarded as the protection scope of the present invention.

Claims

1. An LED dimming control circuit, comprising:

a reference current module configured to provide five reference currents;

the I2C communication controller is configured to receive a clock signal and a data signal, generate five paths of I2C control information and output the control information so as to select an output channel needing to be output and provide the current and the gray scale of the selected output channel;

the LED drive circuit comprises five constant current drive modules, wherein each constant current drive module is configured to receive corresponding reference current and corresponding I2C control information so as to output drive signals through corresponding output channels and adjust the current and gray scale of corresponding LED lamp strings, thereby realizing the dimming control of the five LED lamp strings;

the I2C control information is realized by 17 bytes, wherein, the initial byte is used for configuring the circuit working mode and addressing information, the first byte is used for configuring the enabling information of each output channel, the second byte is used for configuring the range current information of the first output channel, the third byte is used for configuring the range current information of the second output channel, the fourth byte is used for configuring the range current information of the third output channel, the fifth byte is used for configuring the range current information of the fourth output channel, the sixth byte is used for configuring the range current information of the fifth output channel, the seventh byte and the eighth byte are combined for configuring the gray scale information of the first output channel, the ninth byte and the cross are combined for configuring the gray scale information of the second output channel, the eleventh byte and the twelfth byte are combined for configuring the gray scale information of the third output channel, and the thirteenth byte and the fourteenth byte are combined for configuring the gray scale information of the fourth output channel, the fifteenth byte is used in combination with the sixteenth byte to configure the grayscale information for the fifth output channel.

2. The circuit of claim 1, wherein the circuit further comprises a power supply module configured to receive an external input voltage to provide an operating voltage for the circuit; when the external input voltage is greater than a preset voltage threshold, the I2C communication controller enters a working state, and when no signal is input in the clock signal and the data signal, the circuit is controlled to enter a sleep mode.

3. The circuit of claim 1, wherein the I2C control information further includes start state control information, stop state control information, data transfer control information;

the initial state control information is that the level of the data signal is changed from high to low when the clock signal is at high level;

the stop state control information is that the level of the data signal is changed from low to high when the clock signal is at high level;

the data transmission control information is that the level state of the data signal is kept unchanged when the clock signal is at a high level.

4. The circuit of claim 1, wherein the data transmission control information further comprises: when the level of the clock signal changes from low to high, data reading is carried out on the data signal and the data signal is written into a register; generating a corresponding response signal every time a byte of data transmission is completed; the level of the data signal is pulled down by the reply signal.

5. The circuit of claim 4, wherein the data signal is read after delaying a preset noise immunity time after the level of the clock signal changes from low to high, and the read data is written into the register to be latched according to a latch control signal.

6. The circuit as claimed in claim 1, wherein the initial byte comprises 8 bits of data, wherein the 7 th to 8 th bits are identification bits, the 5 th to 6 th bits are circuit operation mode control bits, and the 1 st to 4 th bits are addressing bits; and configuring 5 th to 6 th bits of the initial byte to control the circuit to enter a sleep mode or control the circuit to enter an operating mode.

7. The circuit of claim 1, wherein the first byte comprises 8 bits of data, wherein bits 1 through 5 are used to configure whether each output channel is enabled.

8. The circuit of claim 1, wherein the second byte to the sixth byte each comprise 8-bit data, and wherein the range current of each output channel is configurable to be 0-90 mA by configuring the 1 st bit to the 7 th bit of the corresponding byte to configure the range current of each output channel.

9. The circuit according to claim 1, wherein the seventh byte to the sixteenth byte each include 8-bit data, and two bytes are used to configure the gray scale information of the same output channel; in two bytes used for configuring the gray scale information of the same output channel, the 1 st to 5 th bits of the next byte and the 1 st to 5 th bits of the previous byte are combined to be used for correspondingly configuring the gray scale of the corresponding output channel, and the gray scale configurable range of each output channel is 0-1023 levels.

10. An LED dimming control chip, comprising the LED dimming control circuit according to any one of claims 1 to 9.

11. An illumination device, characterized in that the illumination device comprises a five-way LED string and the LED dimming control chip of claim 10.

12. An LED dimming control method, which adopts the LED dimming control circuit of claim 1; the method is characterized by comprising the following steps:

(1) providing five reference currents through a reference current module;

(2) receiving a clock signal and a data signal through an I2C communication controller, generating five paths of I2C control information and outputting the control information so as to select an output channel needing to be output and provide the current and the gray scale of the selected output channel;

(3) the five constant-current driving modules respectively receive corresponding reference current and corresponding I2C control information, so that driving signals are output through corresponding output channels, the current and the gray scale of corresponding LED lamp strings are adjusted, and dimming control of the five LED lamp strings is achieved;

wherein, the I2C control information is implemented by 17 bytes, the initial byte is used for configuring the circuit working mode and addressing information, the first byte is used for configuring the enabling information of each output channel, the second byte is used for configuring the range current information of the first output channel, the third byte is used for configuring the range current information of the second output channel, the fourth byte is used for configuring the range current information of the third output channel, the fifth byte is used for configuring the range current information of the fourth output channel, the sixth byte is used for configuring the range current information of the fifth output channel, the seventh byte and the eighth byte are combined for configuring the gray scale information of the first output channel, the ninth byte and the cross are combined for configuring the gray scale information of the second output channel, the eleventh byte and the twelfth byte are combined for configuring the gray scale information of the third output channel, the thirteenth byte and the fourteenth byte are combined for configuring the gray scale information of the fourth output channel, the fifteenth byte is used in combination with the sixteenth byte to configure the grayscale information for the fifth output channel.

13. The method of claim 12, wherein the method further comprises:

(10) receiving an external input voltage, controlling the I2C communication controller to enter a working state when the external input voltage is greater than a preset voltage threshold, and controlling the circuit to enter a sleep mode when no signal is input in the clock signal and the data signal.

14. The method of claim 12, wherein step (2) further comprises:

(21) after the level of the clock signal changes from low to high, serial bit transmission is carried out, data reading is carried out on the data signal, and the data signal is written into a register;

(22) generating a corresponding response signal every time a byte of data transmission is completed;

(23) the level of the data signal is pulled down by the reply signal.

15. The method of claim 14, wherein said step (21) further comprises:

and after the level of the clock signal changes from low to high, delaying for a preset anti-noise interference time, reading data of the data signal, and writing the read data into a register according to a latch control signal for latching.

16. A storage medium, characterized in that the storage medium has stored thereon a computer program which, when being executed by a processor, realizes the steps of the LED dimming control method according to any one of claims 12 to 15.

17. Computer device, characterized in that it comprises a processor and a memory, said memory having stored thereon a computer program being executable on the processor, said processor, when executing said computer program, implementing the steps of the LED dimming control method according to any of the claims 12-15.