CN207531133U - Utilize the LED drive circuit of power cord transmission data - Google Patents
Utilize the LED drive circuit of power cord transmission data Download PDFInfo
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- CN207531133U CN207531133U CN201721722636.2U CN201721722636U CN207531133U CN 207531133 U CN207531133 U CN 207531133U CN 201721722636 U CN201721722636 U CN 201721722636U CN 207531133 U CN207531133 U CN 207531133U
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Abstract
The utility model provides a kind of LED drive circuit using power cord transmission data, including source of stable pressure, reference circuit, address module, pierce circuit, signal recognition circuit, data decoding circuit, level shifting circuit, mode control circuit, output driving circuit；The source of stable pressure is used to the voltage on power cord being converted to internal electric source, supplies to data decoding circuit, signal recognition circuit and pierce circuit；Reference circuit is used to generate reference voltage V REF and export to signal recognition circuit；Address module is used to store the inherent address of LED drive circuit；Pierce circuit is for the first clock CLK of generation and exports to data decoding circuit；Signal recognition circuit generates internal standard digital signal VDA and is sent to data decoding circuit；Internal standard digital signal VDA includes address date and control data；The utility model only realizes multiple LED units respectively the independently-controlled scheme with two electric wires.
Description
Technical field
The utility model is related to low current LED constant current drive area, especially a kind of LED using power cord transmission data
Driving circuit.
Background technology
The LED unit largely used in the field at present, there are mainly two types of schemes：The first be by multiple LED units simultaneously
It is associated in a data lines, controller sends control data by data line, and LED unit is received according to the inherent address of oneself to be belonged to
In the data of oneself, application schematic diagram such as Fig. 1.Another kind be multiple LED units by being cascaded before and after data line, each LED is mono-
Member has data input pin and data output end, and the data output end of prime LED unit and the data input pin of rear class LED unit connect
It connecing, controller sends control data to first LED unit by data line, after first LED unit receives the data of oneself,
The data of other units are transmitted backward by data output end, all LED units according to designed data protocol received from
Oneself data, application schematic diagram such as Fig. 2.
Both the above method can realize independent control of the controller to each LED unit, but need three electric wires
Each LED unit can just worked normally, larger using electric wire amount, cost is higher, and debugging is slow, and reliability is low.
Invention content
The purpose of the utility model is to overcome the deficiencies in the prior art, provide a kind of utilization power cord and transmit number
According to LED drive circuit and corresponding data transmission method, only realize that multiple LED units are respectively independent with two electric wires
Controlled scheme, will so substantially reduce production cost, while improve system reliability, work when electric wire radical is used to reduce
Journey debugging is also simpler.The technical solution adopted in the utility model is：
A kind of LED drive circuit using power cord transmission data, including source of stable pressure, reference circuit, address module, oscillation
Device circuit, signal recognition circuit, data decoding circuit, level shifting circuit, mode control circuit, output driving circuit；
The source of stable pressure is used to the voltage on power cord being converted to internal electric source, supplies to data decoding circuit, signal
Identification circuit and pierce circuit；
Reference circuit is used to generate reference voltage V REF and export to signal recognition circuit；
Address module is used to store the inherent address of LED drive circuit, and is supplied to data decoding circuit；
Pierce circuit is for the first clock CLK of generation and exports to data decoding circuit；
Signal recognition circuit generates internal standard digital signal according to the voltage signal on reference voltage V REF and power cord
VDA is simultaneously sent to data decoding circuit；Internal standard digital signal VDA includes address date and control data；
Data decoding circuit parses from internal standard digital signal VDA and obtains the control number for belonging to this LED drive circuit
According to, and by level shifting circuit carry out digital level conversion after, control data in mode operation speed signal, operational mode
Signal Dietary behavior control circuit controls the current controling signal in data to enter output driving circuit；Mode control circuit leads to
Cross three primary colours enable signal end control output driving circuit；The three primary colours output terminal of output driving circuit is used to connect LED.
Further, signal recognition circuit includes resistance R1, R2, R3, comparator U1, phase inverter U2, NMOS tube Q1；
One end of resistance R1 is used to connecing voltage VDD on power cord, and another terminating resistor R2 one end and comparator U1's is same
Phase input terminal, one end of another terminating resistor R3 of resistance R2 and the drain electrode of NMOS tube Q1, the anti-phase input of comparator U1 connect base
Quasi- voltage VREF, output terminal connect the grid of NMOS tube Q1 by phase inverter U2, and the source electrode of resistance R3 and NMOS tube Q1 is for being grounded
Line；Comparator output terminal output internal standard digital signal VDA.
Further,
Data decoding circuit include multibit latch, multibit shift register, accurate clock circuit, edge sense circuit,
Play stopping detecting circuit or door U3, NOT gate U4, rest-set flip-flop U5, digit counter, data counter, address detection circuit, data lock
Deposit circuit；
The input terminal and clock end of edge sense circuit meet internal standard digital signal VDA and the first clock CLK respectively, production
The raw DPL signals corresponding to VDA rising edges；
The clock end and reset terminal of accurate clock circuit connect the first clock CLK and DPL signal respectively；And generate second clock
CK190US；
The numeral input termination internal standard digital signal VDA of start and stop detection circuit, clock termination second clock
CK190US, an output signal RSTB of start and stop detection circuit connect an input terminal of rest-set flip-flop U5 by NOT gate U4, another
A output signal END connects another input terminal of rest-set flip-flop U5, the output terminal output ENOM signals of rest-set flip-flop U5 to or door U3
Input terminal and mode control circuit Enable Pin；
Or an input termination DPL signal of door U3, the reset terminal of output termination digit counter；
The clock termination second clock CK190US of digit counter, output terminal output DCK signals, and it is respectively sent to data
The clock end of counter and the clock end of address detection circuit and multibit shift register clock end；
One output signal RSTB of the reset termination start and stop detection circuit of data counter, two of data counter are defeated
Go out that enable signal D7BIT and D19BIT connect the data Enable Pin of address detection circuit respectively and the data of data-latching circuit enable
End；Wherein output enable signal D19BIT also connects or the input terminal of door U3；
The digital input end and clock end of multibit shift register connect internal standard digital signal VDA and DCK signal respectively,
Output connects the input terminal of multibit latch and the verification position of address detection circuit and address input multiplexing end；
The address input end of address detection circuit connects the output of address module, the reset termination start and stop inspection of address detection circuit
One output signal RSTB of slowdown monitoring circuit, the data input pin of the output termination data-latching circuit of address detection circuit and transmission
DAOK signals；
The clock of data-latching circuit terminates the first clock CLK, the data latch signal end of output termination multibit latch；
The output terminal output control data of multibit latch.
The utility model also proposes a kind of data transmission scheme, including：
Voltage on sender, power cord is controlled as supply voltage and less than supply voltage but higher than recipient's work
Make the second voltage of voltage；Sender is based on the control of above-mentioned voltage and passes through power cord transmission data；
Voltage on recipient, power cord is correspondingly converted to an internal standard digital signal VDA；
The low duration of internal standard digital signal VDA is defined as initial code more than setting time Tstart,
The high level lasting time of internal standard digital signal VDA is defined as end code more than setting time Tend；Internal standard number
Then word signal VDA high level persistence lengths T1h is changed into low level persistence length T1l and is defined as data 1, internal standard number
Then word signal VDA high level persistence lengths T0h is changed into low level persistence length T0l and is defined as data 0；
Wherein, the time span T1h+T1l of data 1 is equal to the time span T0h+T0l of data 0；T1h>T1l；T0h<
T0l；Tstart and Tend is more than the three times of T1h+T1l；
The frame data that sender sends include one or more data packets, are finally end codes；Recipient receives effectively
Data and data is made to come into force after receiving end code；
One data packet includes initial code and long numeric data, and long numeric data includes verification position, address date and control data；
When recipient recognizes the decoding that initial code starts a data packet immediately, and will decode each obtained data
Shift register is sequentially stored into, when data bulk reaches setting value, judges verification position and address date in data packet, if
Verify that position is correct and the address is identical with the inherent address of recipient or address is preset public address, then it is assumed that data have
It imitates and latches, if verification bit-errors or the address are different with the inherent address of recipient, nor preset public address, then
Current data is ignored；No matter whether current data packet is effective, all continue to decode next data packet；Recipient receives end code
Valid data are used afterwards.
Further, the decoding of a data：The identification for starting each data after initial code is recognized, from each digit
According to rising edge start, generate DPL signals in the rising edge of internal standard digital signal VDA, DPL signals reset digit counter
And start to work, the DCK signals of digit counter output are arranged to low level, digit counter meter full multiple second clock periods
It is equal to or just just beyond the half of 1 or 0 time span of data, DCK signals becomes high level, digit counter stops work at this time
Make, until DPL signals arrival next time restarts work；By the use of the rising edges of DCK signals latch the value of VDA as currently this
Position data are simultaneously stored in multibit shift register.
Further, half of the second voltage for supply voltage on power cord.
Further, T1h is two times of T1l, and T0h is the half of T0l.
The utility model has the advantage of：The utility model is passed by improved LED drive circuit and corresponding data
Transmission method so that the controllable lamp strings of the LED in the field become two line applications from current three line application of mainstream, reduces engineering
Cost and system debug difficulty, have saved electric wire resource, while also improve system reliability.
Description of the drawings
Fig. 1 is three line parallel connection LED lamp string application schematic diagram in the prior art.
Fig. 2 is three line series LED lamp string application schematic diagram in the prior art.
Fig. 3 is the two line parallel connection LED lamp string application schematic diagrams of the utility model.
Fig. 4 is the electrical schematic diagram of the utility model.
Fig. 5 is the signal recognition circuit schematic diagram of the utility model.
Fig. 6 is the data decoding circuit schematic diagram of the utility model.
Fig. 7 is each numeric data code waveform diagram and its time parameter of the data transmission scheme of the utility model.
Fig. 8 is the waveform diagram of a frame data of the data transmission scheme of the utility model.
Fig. 9 is 1 yard of the data of the data transmission scheme of the utility model and the decoding time diagram of 0 yard of data.
Specific embodiment
With reference to specific drawings and examples, the utility model is described in further detail.
It is in parallel and can be respectively in the independently-controlled system that the utility model is applicable to multigroup LED light；This LED drives
Circuit will form a LED unit together with three-primary color LED lamp；The LED unit indoors decorate by external decoration, decoration
The fields such as lamp largely use.In figure 3, IC represents LED drive circuit.
The utility model provides a kind of with two electric wires to realize multiple LED units respectively the independently-controlled scheme, such as
This will substantially reduce production cost, while improve system reliability when electric wire radical is used to reduce, and engineering debugging is also simpler
It is single；This two electric wires are exactly controlled power and ground；Its application schematic diagram such as Fig. 3.
Since LED light string only has power and ground composition, come to transmit number for each LED unit without special data line
According to so the utility model devises a kind of scheme using power cord transmission data, it is achieved thereby that transmitting on the power line
The purpose of data；This scheme only needs controller to increase a little element, and data are required to be loaded on power cord i.e. according to scheme
Can, implementation method is very simple.
Using when the anode of multiple LED units and cathode need to be only connected to controller driving power and ground
It is upper, such as Fig. 3；It to be driven because there are one LED drive circuits disclosed in the utility model, the LED in each LED unit
Completion is obtained the task of one's own data by dynamic circuit from power cord；
Data transmission scheme is described below：
Common digital data transmission represents logic 1, usually supply voltage with the ceiling voltage in system, and use is minimum
Voltage 0V represents logical zero；LED drive circuit disclosed in the utility model is because using system power supply line transmission data, no
Can logical zero be represented using 0V voltages, because power cord other than transmitting data, will also undertake powering to LED unit for task, and
0V voltages can not power to LED unit；Therefore the utility model represents logical zero using supply voltage 5V is reduced to 2.5V
Way, supply voltage 2.5V can work normally LED drive circuit internal circuit, while relative to ceiling voltage, generally
It is 5V, and has certain voltage difference, after signal recognition circuit is handled, becomes the number letter of LED drive circuit internal standard
Number logical zero；And it is simultaneously internal standard signal logic 1 by power cord ceiling voltage 5V processing；It is achieved thereby that on power cord
Amplitude is the purpose that the voltage of 2.5V and 5V is converted to internal standardized digital signal respectively.Because power cord is when transmitting data
Scope range of the fluctuation of voltage is 2.5V~5V, devises voltage stabilizing source module here and obtains stable 2.1V power supply V2D1, is dedicated for data
Decoding circuit, signal recognition circuit and pierce circuit power supply；Referring to Fig. 4.
LED drive circuit provided by the utility model, as shown in figure 4, including source of stable pressure, reference circuit, address module, shaking
Swing device circuit, signal recognition circuit, data decoding circuit, level shifting circuit, mode control circuit, output driving circuit；
The source of stable pressure is used to the voltage on power cord being converted to internal electric source V2D1, supply to data decoding circuit,
Signal recognition circuit and pierce circuit；
Reference circuit is used to generate reference voltage V REF and export to signal recognition circuit；
Address module is used to store the inherent address AD [2 of LED drive circuit:0], and it is supplied to data decoding circuit；
Pierce circuit is for the first clock CLK of generation and exports to data decoding circuit；
Signal recognition circuit generates internal standard number according to the voltage signal VDD on reference voltage V REF and power cord
Signal VDA is simultaneously sent to data decoding circuit；Internal standard digital signal VDA includes verifying position, address date and control number
According to；
Data decoding circuit parses from internal standard digital signal VDA and obtains the control number for belonging to this LED drive circuit
According to DA [11:0], after and carrying out digital level conversion by level shifting circuit so that control data DA [11:0] pattern in
Running speed signal DA [11:10], operational mode signal DA [3:0] Dietary behavior control circuit so that the electricity in control data
Flow control signals DA [9:4] into output driving circuit；Mode control circuit passes through three primary colours enable signal end ENR, ENG, ENB
Control output driving circuit；Three primary colours output terminal OUTR, OUTG, OUTB of output driving circuit are used to connect LED；
As shown in figure 5, signal recognition circuit includes resistance R1, R2, R3, comparator U1, phase inverter U2, NMOS tube Q1；
One end of resistance R1 is used to connecing voltage VDD on power cord, and another terminating resistor R2 one end and comparator U1's is same
Phase input terminal, one end of another terminating resistor R3 of resistance R2 and the drain electrode of NMOS tube Q1, the anti-phase input of comparator U1 connect base
Quasi- voltage VREF, output terminal connect the grid of NMOS tube Q1 by phase inverter U2, and the source electrode of resistance R3 and NMOS tube Q1 is for being grounded
Line；Comparator output terminal output internal standard digital signal VDA；
The data transmission scheme of the utility model obtains one's own control data for LED unit, and controller uses
Notebook data transmission plan transmission data, you can realize effective control to each LED unit；Data transmission is to be by power cord
For carrier come what is completed, the amplitude on power cord can be the voltage signal of 2.5V and 5V respectively by signal recognition circuit, be converted respectively
For internal amplitude it is 0V and the internal standard digital signal VDA of 2.1V；
The utility model proposes a kind of data transmission schemes；
LED drive circuit is to be worked by detecting the initial code on VDA come log-on data decoding circuit, and detecting
Data is allowed to come into force after the end code of VDA.Here is initial code, end code and 1 yard of data, the definition of 0 yard of data.
The low duration of internal standard digital signal VDA is determined more than setting time Tstart (such as 20ms)
Justice is initial code, and the high level lasting time of internal standard digital signal VDA is determined more than setting time Tend (such as 20ms)
Justice is end code；Internal standard digital signal VDA high level persistence length T1h (2ms) and then it is changed into low level persistence length
T1l (1ms) is defined as data 1, internal standard digital signal VDA high level persistence length T0h (1ms) and then is changed into low electricity
Flat persistence length T0l (2ms) is defined as data 0；The high level length deviation of data 1 and data 0 needs wanting for satisfaction ± 10%
It asks, low level length requirement is relatively low, as long as initial code will not be mistakenly identified as by circuit；Initial code, end code, data 1, number
According to 0 waveform and time parameter such as Fig. 7；
The frame data that controller is sent include one or more data packets, are finally end codes；LED drive circuit receives
Effective data and data is made to come into force after receiving end code, Fig. 8 is the schematic diagram that controller sends a frame data；
One data packet includes initial code and long numeric data, and long numeric data includes verification position, address date and control data,
Address size needs to set according to actual product, data volume number also according to actual product need specific design, data are sent
Shi Gaowei is first sent out；
When LED drive circuit recognizes the decoding that initial code starts a data packet immediately, and will decoding obtain it is each
Position data are sequentially stored into shift register, and when data bulk reaches setting value, LED drive circuit judges the verification in data packet
Position and address date, if verification position is correct and the address is identical with LED drive circuit inherent address or address is preset
Public address, then LED drive circuit is thought data effectively and is latched, if verification bit-errors or the address and LED driving electricity
Road inherent address is different, nor preset public address, then current data is ignored；No matter whether current data packet is effective,
It may continue to decode next data packet；LED drive circuit uses valid data after receiving end code.
It allows all LED units that can receive the data packet of public address, is because when all LED units is needed to run simultaneously
When model identical, it can only send a data packet and all LED units can be received, and without being each by address
Independent one data packet of hair of LED unit, can so improve the efficiency of controller transmission data, using also becoming very simple.
The decoding principle of a data：Data are decoded and are latched and completed by data decoding circuit, when LED drive circuit identifies
Start the identification of each data after to initial code, since the rising edge of each data, edge sense circuit is marked in inside
The rising edge of quasi- digital signal VDA generates DPL signals, and DPL signals make digit counter reset and start to work, digit counter output
DCK signals be arranged to low level, digit counter meter expires 8 second clocks（CK190US）DCK signals become high electricity after period
Flat, digit counter is stopped at this time, until DPL signals arrival next time restarts work；The second of digit counter input
Clock CK190US is accurate clock, and the period is 190 μ s, therefore is 1.52mS from VDA rising edges to DCK rising times Tdk,
It is substantially equal to the half of 1 or 0 time span of data.The value that VDA is latched with the rising edge of DCK signals is this current one digit number
According to.If the high level that the data that controller is sent are 1, VDA will continue 2mS, then the data latched in DCK rising edges
It is exactly 1, if the high level lasting time that the data that controller is sent are 0, VDA is 1mS, then locked in DCK rising edges
The data deposited are 0.Each data is stored into shift register after latching, until data volume reaches preset requirement.One
Position data decoding sequence diagram such as Fig. 9.
Compare crucially data decoding circuit in the utility model, referring to Fig. 6；
Data decoding circuit include 12 latch, 12 bit shift registers, accurate clock circuit, edge sense circuit,
Play stopping detecting circuit or door U3, NOT gate U4, rest-set flip-flop U5, digit counter, data counter, address detection circuit, data lock
Deposit circuit；
The input terminal and clock end of edge sense circuit meet internal standard digital signal VDA and the first clock CLK respectively, production
The raw DPL signals corresponding to VDA rising edges；
The clock end and reset terminal of accurate clock circuit connect the first clock CLK and DPL signal respectively；And generate second clock
CK190US；The period of second clock CK190US is 190 μ s；
The numeral input termination internal standard digital signal VDA of start and stop detection circuit, clock termination second clock
CK190US, an output signal RSTB of start and stop detection circuit connect an input terminal of rest-set flip-flop U5 by NOT gate U4, another
A output signal END connects another input terminal of rest-set flip-flop U5, the output terminal output ENOM signals of rest-set flip-flop U5 to or door U3
Input terminal and mode control circuit Enable Pin（In Fig. 4）；
Or an input termination DPL signal of door U3, the reset terminal of output termination digit counter；
The clock termination second clock CK190US of digit counter, output terminal output DCK signals, and it is respectively sent to data
The clock end of counter and the clock end of address detection circuit and 12 bit shift register clock ends；
One output signal RSTB of the reset termination start and stop detection circuit of data counter, two of data counter are defeated
Go out the data Enable Pin that enable signal D7BIT and D19BIT connect address detection circuit respectively（D7BIT in Fig. 6) and data latch
The data Enable Pin of circuit（D19BIT in Fig. 6)；Wherein output enable signal D19BIT also connects or the input terminal of door U3；
The digital input end and clock end of 12 bit shift registers connect internal standard digital signal VDA and DCK signal respectively,
Output connects the input terminal of 12 latch and the verification position of address detection circuit and address input multiplexing end（DAT in Fig. 6
[6:0]）;
The address input end of address detection circuit connects the output of address module, i.e. AD [2:0], the reset of address detection circuit
An output signal RSTB of start and stop detection circuit is terminated, the data of the output termination data-latching circuit of address detection circuit are defeated
Enter end and send DAOK signals；
The clock of data-latching circuit terminates the first clock CLK, and output terminates the data latch signal end of 12 latch,
That is the LCH ends in Fig. 6；
The output terminal output control data DA [11 of 12 latch:0]；
The operation principle of the utility model is described below：
LED drive circuit（IC in Fig. 3）It is packaged together with red, green, blue three-color LED light and forms a LED unit, institute
The LED unit stated only has two exits, anode and cathode；According to the connection mode of attached drawing 3, LED unit is connected in parallel,
All LED unit anodes connect the power cord of controller driving, cathode ground wire；According to specific needs with the driving energy of controller
Power determines the quantity of LED unit.
The work under being uniformly controlled of controller of all LED units, in the present embodiment, the data packet that controller is sent includes
Initial code and 19 data, wherein 19 data are respectively：C[3:0]+AD[2:0]+DA[11:0], wherein C [3:0] it is verification
Position, is fixed as 1010, AD [2:0] it is address date in data packet, DA [11:0] it is control data；DA[11:10] for controlling
The LED mode speed of service processed, DA [9:8] output current of control red light R, DA [7:6] output current of control green light G, DA [5:
4] output current of control blue lamp B, DA [3:0] operational mode of LED is controlled.A high position is first sent out when data are sent.
There is the inherent address of oneself inside each LED unit, can be any one of 0~5, address is solidificated in institute
In the LED drive circuit stated, specific address is determined when surveying in circuit, while each LED unit also presets a public address
7.LED drive circuit checks verification position and address in data packet when receiving data packet, if verification position is correct and the address
Or the address identical with itself inherent address is public address 7, then current LED drive circuit can lock the data in data packet
It deposits, and data is allowed to come into force when receiving end code, otherwise data packet is ignored.
Signal recognition circuit the data conversion on VDD into internal standard digital signal VDA, then by data decoding circuit
To complete the decoding of data packet.Decoding circuit schematic diagram such as Fig. 6, which play stopping detecting circuit, to be responsible for identifying initial code and stop code, when
When VDA low durations are more than 20ms, play stopping detecting circuit and generate RSTB signals, represent successfully to recognize initial code, generation
The transmission of one data packet of table starts, and at this moment, address detected module and data counter are returned to original state by RSTB signals.
ENOM signals are arranged to low level, and LED drive circuit is made to stop output, open simultaneously digit counter, and digit counter is used to know
Each other data.Data are by the rising edge of VDA, and edge sense circuit is in the rising edge output DPL pulse letters of VDA
Number, digit counter is resetted, DCK signals become low level, while reset accurate clock circuit, accurate clock circuit output second clock
The period of CK190US is 190us；Digit counter generates DCK signals after being counted 8 times to second clock CK190US and becomes high level,
Digit counter is stopped at this time, and standing state is kept to restart work again until next time is reset.Utilize the rising edge of DCK
The value of VDA is latched and is pushed into 12 bit shift registers.When data volume reaches 7, address detection circuit judges whether to meet
The requirement of current circuit, at this time DAT [6:3] should be fixed value 1010, DAT [2:It 0] should be with internal inherent address AD [2:0]
It is identical or 7.If meeting this requirement, DAOK signals can become high level and state locks, if being unsatisfactory for this requirement,
DAOK signals keep low level constant.But regardless of state, address detection circuit can all keep existing output state, Zhi Daoqi
Stopping detecting circuit re-recognizes initial code, generates RSTB signals and is resetted, can just be reworked.When data are decoded to 19
During position, latch signal LDDT is generated if DAOK signals are high level, 12-bit data are latched into from 12 bit shift registers
It is spare in 12 latch, it otherwise will not generate LDDT latch signals.But no matter latch signal LDDT whether is finally generated, at this time
A decoded packet data is all represented to terminate.Under normal circumstances, a frame data include one or more data packets.Circuit can be to each
Data packet is decoded and judges whether effectively.Stopping detecting circuit recognizes stop code from when VDA high level continues 20ms, produces
Raw END signals, ENOM signals are set to high level, represent data decoding and terminate, LED drive circuit starts normally to export and use
The newest data received.
The lamp string being made of multiple LED units under being uniformly controlled of controller, can realize that the Integral synchronous of lamp string becomes
Change effect, each single-point peace requirement operation designated mode can also be made.In addition, it is the inherent address with LED unit to have partial mode
It is associated, if lamp string is arranged according to sequence of addresses, whole color can be completed and waved effect, it is such as colorful to dazzle changes, it flows
Star trails, colorful swabbing etc..
Above-mentioned lamp string, can also be according to the self-designed side of user in use, can arrange according to lamp string sequence of addresses
Formula is arranged.
One LED unit may be constructed a point of lamp string or the LED unit of one group of identical address forms lamp string
A point.
It should be noted last that more than specific embodiment is only to illustrate the technical solution of the utility model rather than limit
System, although the utility model is described in detail with reference to example, it will be understood by those of ordinary skill in the art that, it can be right
The technical solution of the utility model is modified or replaced equivalently, without departing from the spirit and model of technical solutions of the utility model
It encloses, should all cover in the right of the utility model.
Claims (4)
1. a kind of LED drive circuit using power cord transmission data, which is characterized in that including source of stable pressure, reference circuit, address
Module, pierce circuit, signal recognition circuit, data decoding circuit, level shifting circuit, mode control circuit, output driving
Circuit；
The source of stable pressure is used to the voltage on power cord being converted to internal electric source, supplies to data decoding circuit, signal identification
Circuit and pierce circuit；
Reference circuit is used to generate reference voltage V REF and export to signal recognition circuit；
Address module is used to store the inherent address of LED drive circuit, and is supplied to data decoding circuit；
Pierce circuit is for the first clock CLK of generation and exports to data decoding circuit；
Signal recognition circuit generates internal standard digital signal VDA according to the voltage signal on reference voltage V REF and power cord
And it is sent to data decoding circuit；Internal standard digital signal VDA includes address date and control data；
Data decoding circuit parses from internal standard digital signal VDA and obtains the control data for belonging to this LED drive circuit, and
After carrying out digital level conversion by level shifting circuit, mode operation speed signal, operational mode signal in data are controlled
Dietary behavior control circuit controls the current controling signal in data to enter output driving circuit；Mode control circuit passes through three
Primary colours enable signal end controls output driving circuit；The three primary colours output terminal of output driving circuit is used to connect LED.
2. the LED drive circuit of power cord transmission data is utilized as described in claim 1, which is characterized in that
Signal recognition circuit includes resistance R1, R2, R3, comparator U1, phase inverter U2, NMOS tube Q1；
One end of resistance R1 is used to meet the voltage VDD on power cord, and another terminating resistor R2 one end is same mutually defeated with comparator U1's
Enter end, one end of another terminating resistor R3 of resistance R2 and the drain electrode of NMOS tube Q1, the anti-phase input of comparator U1 connects benchmark electricity
VREF is pressed, output terminal connects the grid of NMOS tube Q1 by phase inverter U2, and the source electrode of resistance R3 and NMOS tube Q1 is for being grounded；Than
Compared with device output terminal output internal standard digital signal VDA.
3. the LED drive circuit of power cord transmission data is utilized as claimed in claim 1 or 2, which is characterized in that
Data decoding circuit includes multibit latch, multibit shift register, accurate clock circuit, edge sense circuit, start-stop
Detection circuit or door U3, NOT gate U4, rest-set flip-flop U5, digit counter, data counter, address detection circuit, data latch electricity
Road；
The input terminal and clock end of edge sense circuit connect internal standard digital signal VDA and the first clock CLK, generation pair respectively
It should be in the DPL signals of VDA rising edges；
The clock end and reset terminal of accurate clock circuit connect the first clock CLK and DPL signal respectively；And generate second clock
CK190US；
The numeral input termination internal standard digital signal VDA of start and stop detection circuit, clock termination second clock CK190US are opened
One output signal RSTB of stopping detecting circuit connects an input terminal of rest-set flip-flop U5, another output signal by NOT gate U4
END connects another input terminal of rest-set flip-flop U5, the output terminal output ENOM signals of rest-set flip-flop U5 to or door U3 input terminal, with
And the Enable Pin of mode control circuit；
Or an input termination DPL signal of door U3, the reset terminal of output termination digit counter；
The clock termination second clock CK190US of digit counter, output terminal output DCK signals, and it is respectively sent to data counts
The clock end of device and the clock end of address detection circuit and the clock end of multibit shift register；
One output signal RSTB of the reset termination start and stop detection circuit of data counter, two outputs of data counter make
Energy signal D7BIT and D19BIT connect the data Enable Pin of address detection circuit and the data Enable Pin of data-latching circuit respectively；
Wherein output enable signal D19BIT also connects or the input terminal of door U3；
The digital input end and clock end of multibit shift register connect internal standard digital signal VDA and DCK signal respectively, output
Connect the input terminal of multibit latch and the verification position of address detection circuit and address input multiplexing end；
The address input end of address detection circuit connects the output of address module, the reset termination start and stop detection electricity of address detection circuit
One output signal RSTB on road, the data input pin of the output termination data-latching circuit of address detection circuit simultaneously send DAOK
Signal；
The clock of data-latching circuit terminates the first clock CLK, the data latch signal end of output termination multibit latch；
The output terminal output control data of multibit latch.
4. the LED drive circuit of power cord transmission data is utilized as claimed in claim 1 or 2, which is characterized in that
Verification position is further included in internal standard digital signal VDA.
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| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201721722636.2U CN207531133U (en) | 2017-12-12 | 2017-12-12 | Utilize the LED drive circuit of power cord transmission data |
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| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201721722636.2U CN207531133U (en) | 2017-12-12 | 2017-12-12 | Utilize the LED drive circuit of power cord transmission data |
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| CN207531133U true CN207531133U (en) | 2018-06-22 |
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Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN107896400A (en) * | 2017-12-12 | 2018-04-10 | 无锡德芯微电子有限公司 | Utilize the LED drive circuit and data transmission method of power line transmission data |
| CN109041332A (en) * | 2018-07-17 | 2018-12-18 | 宗仁科技(平潭)有限公司 | A kind of LED light string and its control chip |
-
2017
- 2017-12-12 CN CN201721722636.2U patent/CN207531133U/en active Active
Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN107896400A (en) * | 2017-12-12 | 2018-04-10 | 无锡德芯微电子有限公司 | Utilize the LED drive circuit and data transmission method of power line transmission data |
| CN109041332A (en) * | 2018-07-17 | 2018-12-18 | 宗仁科技(平潭)有限公司 | A kind of LED light string and its control chip |
| CN109041332B (en) * | 2018-07-17 | 2021-06-01 | 宗仁科技(平潭)有限公司 | LED lamp string and control chip thereof |
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