CN109637438A - A kind of update method of display control parameter, driving chip - Google Patents
A kind of update method of display control parameter, driving chip Download PDFInfo
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- G09G3/30—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels
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Abstract
This application discloses a kind of update methods of display control parameter, driving chip, when carrying out the update of display control parameter using the update method of display control parameter, to the pixel array with a variety of display control pixels, either update single display control parameter, still multiple display control parameters are updated, primary completion can be operated by the write the two or more syllables of a word together of interface module, greatly facilitate the operation that display content is quickly updated by pixel dot sequency.And improve ratio shared by display control parameter in the data of the transmission of the interface module in driving chip, improve the valid data of interface module transmission ratio shared in always transmission data, namely when transmitting the display control parameter of identical quantity, the quantity for the total transmission data transmitted needed for interface module reduces, the requirement in the renewal process of multiple display control parameters to the transmission data capability of interface module is reduced, the transmission data capability for reducing interface module is difficult to the probability that the case where meeting the requirements occurs.
Description
Technical Field
The present disclosure relates to the field of pixel array driving technologies, and in particular, to a method for updating display control parameters and a driving chip.
Background
A Light Emitting Diode (LED) is used as a display pixel, and a structure in which a plurality of display pixels are arranged in an array is called a pixel array or an LED array.
The display driving of the pixel array is usually performed by means of a driving chip, and the brightness of each display pixel in the pixel array is usually controlled by a plurality of display control parameters. In order to update the display control parameters in the pixel array, one type of display control parameters is usually stored in an address page of a register in the driver chip, and when a certain type of display control parameters needs to be updated, the update of the type of display control parameters stored in the driver chip is quickly completed by using a write-through function of an interface module (usually, an I2C interface) of the driver chip.
However, in the practical application process, the driving chip is usually required to control the pixel array to complete the display of a plurality of images or animations, which requires that various types of display control parameters stored in the driving chip are continuously updated, so that the driving chip drives the pixel array to complete the continuous display of different images. However, for a pixel array with many display pixels, updating the display control parameters stored in the driver chip by using the existing method for updating the display control parameters requires transmission of a large amount of data by the interface module, which not only increases the requirement for the data transmission capability of the interface module, but also is prone to cause abnormal display of the pixel array due to the fact that the data transmission capability of the interface module is difficult to meet the requirement.
Disclosure of Invention
In order to solve the foregoing technical problems, embodiments of the present application provide an updating method for display control parameters and a driver chip, so as to achieve the purpose of reducing the requirement on the data transmission capability of an interface module in the process of updating a plurality of display control parameters, and avoid the situation that the data transmission capability of the interface module is difficult to meet the requirement.
In order to achieve the technical purpose, the embodiment of the application provides the following technical scheme:
a method for updating display control parameters is applied to a driving chip, the driving chip is used for driving a pixel array comprising a plurality of display pixels to display, the driving chip comprises a display control storage unit which stores A display control parameters, P is more than 1, and the method for updating the display control parameters comprises the following steps:
acquiring a display updating instruction, wherein the display updating instruction comprises display control parameters and a parameter logic address, the parameter logic address comprises a control parameter group arranged according to the arrangement sequence of the display pixels of the pixel array, and the control parameter group comprises at least one display control parameter;
caching display control parameters of Q preset units, wherein Q is P-1;
determining the sequence of the physical addresses to be updated in the display control storage unit according to the parameter logical address;
and updating the display control parameters stored in the display control storage unit according to the sequence of the physical addresses to be updated by using the cached display control parameters and the display control parameters in the display updating instruction.
Optionally, the updating, by using the cached display control parameters and the display control parameters in the display update instruction, the display control parameters stored in the display control storage unit according to the sequence of the physical addresses to be updated includes:
writing the display control parameters of the Q cached preset units and the display control parameters of a preset unit after the cached display control parameters into the display control storage unit according to the sequence of the physical addresses to be updated by using the cached display control parameters of the Q cached preset units and the cached display control parameters of a preset unit after the display control parameters;
and judging whether the display control parameters in the display updating instruction are all written into the display control storage unit, if not, caching the display control parameters of the last Q preset units written with the display control parameters of the display control storage unit in the display updating instruction, returning the display control parameters of the last Q preset units cached with the display control parameters of the last preset units, and writing the display control parameters of the last preset units cached with the display control parameters of the last preset units into the display control storage unit according to the sequence of the physical addresses to be updated.
Optionally, the preset unit is a byte.
A driver chip for driving a pixel array display including a plurality of display pixels, the driver chip comprising: the interface module, the time sequence signal output module and the data signal output module are connected with the interface module; wherein,
the interface module is used for receiving a display updating instruction and a time sequence updating instruction;
the time sequence signal output module is used for outputting a selection switch signal according to time sequence control information, receiving the time sequence updating instruction and updating the time sequence control information according to a time sequence control parameter in the time sequence updating instruction;
the display updating instruction comprises display control parameters and parameter logical addresses, the parameter logical addresses comprise control parameter groups arranged according to the arrangement sequence of the display pixels of the pixel array, and the control parameter groups comprise at least one display control parameter;
the data signal output module includes: the display control device comprises a data selection unit, a display control storage unit and a data signal generation unit; wherein,
the data selection unit comprises Q storage registers, and the storage registers are used for caching the display control parameters; q is P-1, P is a kind of the display control parameter stored in the display control storage unit, and P > 1; the data selection unit is used for determining the sequence of physical addresses to be updated in the display control storage unit according to the parameter logical address, and updating the display control parameters stored in the display control storage unit according to the sequence of the physical addresses to be updated by using the cached display control parameters and the display control parameters in the time sequence updating instruction;
the data signal generating unit is used for generating a data driving signal according to the display control parameter stored in the display control storage unit and outputting the data driving signal to the pixel array.
Optionally, the data selecting unit updates the display control parameters stored in the display control storage unit according to the sequence of the physical addresses to be updated by using the cached display control parameters and the display control parameters in the display update instruction, specifically,
writing the display control parameters of the Q cached preset units and the display control parameters of a preset unit after the cached display control parameters into the display control storage unit according to the sequence of the physical addresses to be updated by using the cached display control parameters of the Q cached preset units and the cached display control parameters of a preset unit after the display control parameters;
and judging whether the display control parameters in the display updating instruction are all written into the display control storage unit, if not, caching the display control parameters of the last Q preset units written with the display control parameters of the display control storage unit in the display updating instruction, returning the display control parameters of the last Q preset units cached with the display control parameters of the last preset units, and writing the display control parameters of the last preset units cached with the display control parameters of the last preset units into the display control storage unit according to the sequence of the physical addresses to be updated.
Optionally, the interface module includes a first output end, a second output end, a third output end, and a fourth output end;
the data selection unit further includes: a write data selection circuit, a logic address storage circuit, a write enable signal generation circuit, and a write address selection circuit;
the storage register is connected with the first output end of the interface module and used for receiving and caching the display control parameters transmitted by the interface module;
the write data selection circuit comprises Q first input ends, a second input end and a third input end, the Q first input ends of the write data selection circuit are respectively connected with the storage register, and the second input end of the write data selection circuit is connected with the first output end of the interface module; the output end of the write data selection circuit is connected with the display control storage unit;
the input end of the logic address storage circuit is connected with the second output end of the interface module, and the output end of the logic address storage circuit is respectively connected with the second input end of the write enable signal generation circuit and the second input end of the write data selection circuit;
the first input end of the write address selection circuit is connected with the third output end of the interface module; the output end of the write address selection circuit is connected with the display control storage unit;
the first input end of the write data selection circuit is connected with the fourth output end of the interface module, and the output end of the write data selection circuit is connected with the display control storage unit;
the logic address storage circuit is used for storing the parameter logic address, the write enable signal generation circuit is used for generating a write enable signal according to the parameter logic address and transmitting the write enable signal to the display control storage unit, and the write enable signal comprises a first state and a second state;
the write data selection circuit is used for transmitting the display control parameters of the Q preset units cached by the Q storage registers and the display control parameters of one preset unit behind the cached display control parameters to the display control storage unit, and is also used for generating write data signals according to the parameter logical addresses and transmitting the write data signals to the display control storage unit, so that the display control storage unit writes the display control parameters of the Q cached preset units and the display control parameters of one preset unit behind the cached display control parameters into the display control storage unit under the control of the write data signals according to the sequence of the physical addresses to be updated; the write data signal is active when the write enable signal is in a first state.
Optionally, the display control storage unit is an SRAM or a D flip-flop register set or a latch array.
Optionally, the preset unit is a byte.
It can be seen from the above technical solutions that, when the display control parameters in the display control storage unit are updated by using the update method for the display control parameters, because the sequence of the physical addresses to be updated in the display control storage unit is determined in advance according to the logical addresses of the parameters and the display control parameters of Q preset units are cached, no matter one display control parameter in the display control storage unit is updated or a plurality of display control parameters in the display control storage unit are updated, the update process can be completed by using one-time write-through operation, the proportion of the display control parameters in the data transmitted by the interface module in the driver chip is increased, that is, the proportion of the effective data transmitted by the interface module in the total transmission data is increased, that is, when the same number of display control parameters are transmitted, the number of total transmission data required to be transmitted by the interface module is reduced, so that the requirement on the data transmission capability of the interface module in the updating process of a plurality of display control parameters is reduced, and the probability that the data transmission capability of the interface module is difficult to meet the requirement is reduced.
Drawings
In order to more clearly illustrate the embodiments of the present application or the technical solutions in the prior art, the drawings needed to be used in the description of the embodiments or the prior art will be briefly introduced below, it is obvious that the drawings in the following description are only embodiments of the present application, and for those skilled in the art, other drawings can be obtained according to the provided drawings without creative efforts.
FIG. 1 is a schematic view of the arrangement of display pixels in a pixel array;
fig. 2 is a schematic diagram of driving signal waveforms for array driving of the pixel array shown in fig. 1;
FIG. 3 is a diagram illustrating a prior art paging for storing display control parameters in a display control memory;
FIG. 4 is a diagram illustrating a data transmission sequence on a data line during a write-through operation using an I2C interface in the prior art;
FIG. 5 is a diagram illustrating the transmission timing sequence when updating all A parameters in Page 1 is completed by a write operation;
FIG. 6 is a schematic diagram of the I2C interface transmission timing sequence for updating two control parameters of a display pixel according to the display pixel sequence;
fig. 7 is a flowchart illustrating a method for updating display control parameters according to an embodiment of the present application;
fig. 8 and 9 are schematic diagrams illustrating arrangement of display control parameters in a parameter logical address according to an embodiment of the present application;
fig. 10 is a schematic diagram of data transmitted by the interface module when two display control parameters (a parameter and B parameter) are updated by using the update method for display control parameters according to the embodiment of the present application;
fig. 11 is a flowchart illustrating a method for updating display control parameters according to another embodiment of the present application;
fig. 12 is a schematic structural diagram of a driving chip according to an embodiment of the present application;
fig. 13 is a schematic structural diagram of a data signal output module according to an embodiment of the present application.
Detailed Description
As shown in fig. 1, the pixel array refers to a structure in which a plurality of display pixels are arranged in an array of M rows and N columns, and a matrix driving mode is generally adopted, and in fig. 1, 36 display pixels arranged in an array of 6 rows and 6 columns are shown, each of which operates in a time division mode. The luminance of each display pixel is determined by the average current flowing through the display pixel, and for a display pixel composed of RGB LEDs, the luminance ratio of the three colors of red, green, and blue output determines the color of the final display.
Referring to fig. 2, fig. 2 is a driving signal waveform for array driving the pixel array shown in fig. 1, and SWx, x e (1,2,3,4,5,6) represents a selection switch signal for turning on display pixels in x columns when SWx is at a high level; CSy, y e (1,2,3,4,5,6) represents the constant current source current level parameter (data drive signal determined by a display control parameter) for each display pixel in row y, and (i, j) in CS1 represents the constant current source current level parameter for a display pixel at the position of row j, column i, with the coordinate (i, j), i e (1,2,3,4,5,6), j e (1,2,3,4,5,6), in fig. 2. These two signals are output from the driver chip to control the display of the pixel array.
Early pixel array displays had less demanding performance requirements, with only simple on/off control (select switch signal control) and few current regulation levels (display control parameter control). With the continuous improvement of display technology, the control of the corresponding pixel array of the driving chip is more and more exquisite, and the brightness adjustment level is more and more. In the category of display control parameters, there are not only constant current source current level parameters to control the brightness of the display pixels, but also PWM (pulse width modulation) techniques are commonly used to obtain higher resolution of the average current by adjusting the duty ratio of the current pulses. In addition, for convenience of control and reduction of transmission time of control information, the display control parameters may further include a turn-on/turn-off control signal for each display pixel, an auto-breathing control signal, a global current control signal for all display pixels, and the like. The more display control parameters, the more display performance and functions of the pixel array are improved, and more flexibility is provided for the application of a user.
The interface module of the driving chip of the pixel array is usually controlled by an I2C interface, and the I2C interface only needs to use two signal lines of SCL and SDA, but the data transmission rate is low, usually 400kHz fast I2C interface. The number of display pixels of the pixel array is generally large and is often used for displaying animation effects, and at this time, the upper processor needs to periodically and rapidly update the control parameters of all the display pixels in the driving chip to realize pixel display. As described in the background art, with the increasing variety of display control parameters, when a plurality of display control parameters need to be updated simultaneously, the update method of the display control parameters in the prior art has a high requirement on the data transmission capability of the interface module, and is prone to cause a situation that the data transmission capability of the interface module is difficult to meet the requirement, resulting in abnormal display of the pixel array.
The following describes a method for updating display control parameters in the prior art, in which the driver chip includes a display control memory for storing the display control parameters, as shown in fig. 3, the parameters are classified into different register pages, for example, page 1 stores all a parameters in the order of display pixels in the pixel array, page 2 stores all B parameters in the order of display pixels in the pixel array, and page3 stores all C parameters in the order of display pixels in the pixel array; in fig. 3, (i, j) represents the coordinates of the display pixel.
The display control parameters thus stored can be completed by using the write-through function of the I2C interface when one of the display control parameters is updated. As shown in fig. 4, fig. 4 shows a data transmission sequence on the data line SDA in the I2C interface write-through operation, a write-through operation is completed by transmitting an address (device address/write) of a driver chip, a register address (for setting a register logical address), and a pixel address, the I2 interface is often designed to have a function of automatically incrementing the register address, and during the write-through operation, only the register address of the first data needs to be set, and then the register address can be automatically incremented by 1 after every 1 byte of data is transmitted, so that the read and write of multiple continuous address registers can be completed by 1 write-through operation of the I2C interface.
For example, when all the a parameters stored in fig. 3 are updated, the update of all the a parameters stored in page 1 can be completed by one write-through operation of I2C. As shown in fig. 5, fig. 5 is a transfer timing when updating of all a parameters in PAGE 1 is completed by one write operation, an operation of setting PAGE register PAGE to 1 is completed by one data transfer (device address/write-set PAGE address-set PAGE register PAGE address of 0x01), and then data transfer of refreshing all a parameters is performed. If the data byte of the non-display control parameter is transmitted as the overhead, the control parameters of all pixels in the same page are updated, the overhead is only 5 bytes, and the total number of transmitted bytes is M multiplied by N + 5. Therefore, when a display control parameter is updated in the prior art, the information transmission efficiency of the I2C interface is very high, and the display control parameter can be refreshed quickly.
However, when two or more display control parameters need to be updated, the updating method using the display control parameters of the prior art is inefficient, and the register address needs to be replaced many times, as shown in fig. 6, where fig. 6 is a schematic diagram of the transmission timing of the I2C interface for updating two control parameters of one display pixel according to the display pixel sequence. As can be seen from fig. 6, if each display pixel has two display control parameters, and the display needs to be updated pixel by pixel (this is to ensure normal display of the pixel array) in units of display pixels, 12 bytes need to be transmitted by the I2C interface for updating the two display control parameters of one display pixel, where the number of valid bytes (bytes occupied by display control parameters) is only 2, and the overhead is 10 bytes, and the information transmission efficiency of the I2C interface is only 1/6, which may cause the update rate of the display control parameters of the display pixels to be too slow to meet the display requirements of animation or picture replacement.
In view of this, an embodiment of the present application provides an updating method of display control parameters and a driver chip, where when updating display control parameters in a display control storage unit by using the updating method of display control parameters, since a physical address sequence to be updated in the display control storage unit is determined in advance according to a parameter logical address and Q display control parameters of preset units are cached, an updating process can be completed by using one write-through operation no matter one display control parameter in the display control storage unit is updated or a plurality of display control parameters in the display control storage unit is updated, so as to increase a proportion of the display control parameters in data transmitted by an interface module in the driver chip, that is, a proportion of effective data transmitted by the interface module in total transmission data is increased, that is, when the same number of display control parameters are transmitted, the number of total transmission data required to be transmitted by the interface module is reduced, so that the requirement on the data transmission capability of the interface module in the updating process of a plurality of display control parameters is reduced, and the probability that the data transmission capability of the interface module is difficult to meet the requirement is reduced.
The technical solutions in the embodiments of the present application will be clearly and completely described below with reference to the drawings in the embodiments of the present application, and it is obvious that the described embodiments are only a part of the embodiments of the present application, and not all of the embodiments. All other embodiments, which can be derived by a person skilled in the art from the embodiments given herein without making any creative effort, shall fall within the protection scope of the present application.
The embodiment of the present application provides an updating method of display control parameters, as shown in fig. 7, the updating method is applied to a driver chip, the driver chip is used for driving a pixel array including a plurality of display pixels to display, the driver chip includes a display control storage unit storing P types of display control parameters, P > 1, and the updating method of the display control parameters includes:
s101: acquiring a display updating instruction, wherein the display updating instruction comprises display control parameters and a parameter logic address, the parameter logic address comprises a control parameter group arranged according to the arrangement sequence of the display pixels of the pixel array, and the control parameter group comprises at least one display control parameter;
s102: caching display control parameters of Q preset units, wherein Q is P-1;
s103: determining the sequence of the physical addresses to be updated in the display control storage unit according to the parameter logical address;
s104: and updating the display control parameters stored in the display control storage unit according to the sequence of the physical addresses to be updated by using the cached display control parameters and the display control parameters in the display updating instruction.
Optionally, the preset unit is a Byte (Byte), and 1 Byte is 8 bits (bit).
Referring to fig. 8 and 9, fig. 8 and 9 show arrangement of display control parameters when the control parameter group in the parameter logical address includes two display control parameters and three display control parameters, respectively, and in fig. 8, the control parameter group includes two display control parameters, which are an a parameter and a B parameter, respectively. The a parameter and the B parameter of the display pixel having the coordinates (1,1) are arranged in the same page in order, the a parameter and the B parameter of the display pixel having the coordinates (1,2) are arranged after the B parameter of the display pixel having the coordinates (1,1), and the two parameters of the other display pixels are arranged in the order of the arrangement of the display pixels.
Similarly, in fig. 9, the control parameter group includes three display control parameters, which are an a parameter, a B parameter, and a C parameter. The a parameter, the B parameter, and the C parameter of the display pixel having the coordinates (1,1) are sequentially arranged in the same page, and after the a parameter, the B parameter, and the C parameter of the display pixel having the coordinates (1,2) are sequentially arranged in the C parameter of the display pixel having the coordinates (1,1), the three parameters of the display pixel having the coordinates (1,3) (1,4) … … (2,1) … … (x, y) are sequentially arranged in the arrangement order of the display pixels.
Referring to fig. 10, fig. 10 is a schematic diagram of data transmitted by an interface module when two display control parameters (a parameter and B parameter) are updated by using the update method of the display control parameters provided in the embodiment of the present application, and as can be seen from fig. 10, when the update method of the display control parameters provided in the embodiment of the present application is used to update multiple parameters of the display control parameters stored in the display control storage unit of the driver chip, only parameter logic addresses containing the parameters need to be set, the update of the multiple parameters can be completed by using one write-through operation of the interface module, and register paging addresses do not need to be frequently changed, so that the proportion of the display control parameters in the data transmitted by the interface module in the driver chip is increased, that is, the proportion of valid data transmitted by the interface module in total transmission data is increased, that is, when the same number of display control parameters are transmitted, the number of the total transmission data required to be transmitted by the interface module is reduced, so that the requirement on the data transmission capacity of the interface module in the updating process of a plurality of display control parameters is reduced, and the probability that the data transmission capacity of the interface module cannot meet the requirement is reduced.
It should be noted that, in this embodiment of the present application, before performing the update of the display control parameters, the display control parameters of Q preset units need to be cached, Q is P-1, because the update of the maximum P display control parameters of one display pixel can be completed only after the display control parameters of Q preset units are cached and the display control parameters of one preset unit after the cached Q preset units are written once, and then the internal physical address of the interface module is increased by 1, so that the display control parameters of Q preset units of the subsequent cache and the display control parameters of one preset unit after the cached Q preset units update the display control parameters of the next display pixel.
Specifically, referring to fig. 11, the updating, according to the sequence of the physical addresses to be updated, the display control parameters stored in the display control storage unit by using the cached display control parameters and the display control parameters in the display update instruction includes:
s1041: writing the display control parameters of the Q cached preset units and the display control parameters of a preset unit after the cached display control parameters into the display control storage unit according to the sequence of the physical addresses to be updated by using the cached display control parameters of the Q cached preset units and the cached display control parameters of a preset unit after the display control parameters;
s1042: and judging whether the display control parameters in the display updating instruction are all written into the display control storage unit, if not, caching the display control parameters of the last Q preset units written with the display control parameters of the display control storage unit in the display updating instruction, returning the display control parameters of the last Q preset units cached with the display control parameters of the last preset units, and writing the display control parameters of the last preset units cached with the display control parameters of the last preset units into the display control storage unit according to the sequence of the physical addresses to be updated.
Correspondingly, an embodiment of the present application further provides a driving chip, as shown in fig. 12, configured to drive a pixel array including a plurality of display pixels to display, where the driving chip includes: the interface module 10, the timing signal output module 30 and the data signal output module 20 connected with the interface module 10; wherein,
the interface module 10 is configured to receive a display update instruction and a timing update instruction;
the timing signal output module 30 is configured to output a selection switch signal according to timing control information, and is configured to receive the timing update instruction, and update the timing control information according to a timing control parameter in the timing update instruction;
the display updating instruction comprises display control parameters and parameter logical addresses, the parameter logical addresses comprise control parameter groups arranged according to the arrangement sequence of the display pixels of the pixel array, and the control parameter groups comprise at least one display control parameter;
the data signal output module 20 includes: the display control device comprises a data selection unit, a display control storage unit and a data signal generation unit; wherein,
the data selection unit comprises Q storage registers, and the storage registers are used for caching the display control parameters; q is P-1, P is a kind of the display control parameter stored in the display control storage unit, and P > 1; the data selection unit is used for determining the sequence of physical addresses to be updated in the display control storage unit according to the parameter logical address, and updating the display control parameters stored in the display control storage unit according to the sequence of the physical addresses to be updated by using the cached display control parameters and the display control parameters in the time sequence updating instruction;
the data signal generating unit is used for generating a data driving signal according to the display control parameter stored in the display control storage unit and outputting the data driving signal to the pixel array.
In fig. 12, Swx, x ∈ (1,2,3 … … M) represents the timing control information; csx, x ∈ (1,2,3 … … N) represents the data driving signal.
Optionally, the preset unit is a byte.
Optionally, the data selecting unit updates the display control parameters stored in the display control storage unit according to the sequence of the physical addresses to be updated by using the cached display control parameters and the display control parameters in the display update instruction, specifically,
writing the display control parameters of the Q cached preset units and the display control parameters of a preset unit after the cached display control parameters into the display control storage unit according to the sequence of the physical addresses to be updated by using the cached display control parameters of the Q cached preset units and the cached display control parameters of a preset unit after the display control parameters;
and judging whether the display control parameters in the display updating instruction are all written into the display control storage unit, if not, caching the display control parameters of the last Q preset units written with the display control parameters of the display control storage unit in the display updating instruction, returning the display control parameters of the last Q preset units cached with the display control parameters of the last preset units, and writing the display control parameters of the last preset units cached with the display control parameters of the last preset units into the display control storage unit according to the sequence of the physical addresses to be updated.
On the basis of the foregoing embodiments, in an optional embodiment of the present application, a practical configuration of a specific data selection unit is provided, as shown in fig. 13, in this embodiment, the interface module 10 includes a first output terminal, a second output terminal, a third output terminal, and a fourth output terminal;
the data selection unit further includes: a write data selection circuit 22, a logical address storage circuit 23, a write enable signal generation circuit 24, and a write address selection circuit 25;
the storage register 21 is connected to the first output end of the interface module 10, and is configured to receive and cache the display control parameter transmitted by the interface module 10;
the write data selection circuit 22 includes B first input terminals, a second input terminal and a third input terminal, the B first input terminals of the write data selection circuit 22 are respectively connected to the storage register 21, and the second input terminal of the write data selection circuit 22 is connected to the first output terminal of the interface module 10; the output end of the write data selection circuit 22 is connected to the display control storage unit 26;
the input end of the logic address storage circuit 23 is connected to the second output end of the interface module 10, and the output end of the logic address storage circuit 23 is respectively connected to the second input end of the write enable signal generation circuit 24 and the second input end of the write address selection circuit 25;
a first input end of the write enable signal generating circuit is connected with a third output end of the interface module 10; the output end of the write enable signal generating circuit is connected with the display control storage unit 26;
a first input end of the write address selection circuit 25 is connected to a fourth output end of the interface module 10, and an output end of the write address selection circuit 25 is connected to the display control storage unit 26;
the logic address storage circuit 23 is configured to store the parameter logic address, and the write enable signal generation circuit 24 is configured to generate a write enable signal according to the parameter logic address, and transmit the write enable signal to the display control storage unit 26, where the write enable signal includes a first state and a second state;
the write data selecting circuit 22 is configured to transmit the display control parameters of Q preset units buffered by the Q storage registers 21 and the display control parameter of a preset unit after the buffered display control parameter to the display control storage unit 26, and further configured to generate a write data signal according to the parameter logical address, and transmit the write data signal to the display control storage unit 26, so that the display control storage unit 26 writes the display control parameters of the Q preset units buffered and the display control parameter of a preset unit after the buffered display control parameter into the display control storage unit 26 according to the sequence of the physical address to be updated under the control of the write data signal; the write data signal is active when the write enable signal is in a first state.
Optionally, the display control storage unit 26 is a Static Random-Access memory (SRAM) or a D flip-flop register set or a latch array.
In fig. 13, P ═ 3 and Q ═ 2 are exemplified, and in other embodiments of the present application, a and B may take other possible values, which is not limited in the present application.
In the embodiment shown in fig. 13, ABUF and BBUF indicate two memory registers 21 in the data selection unit, and each display pixel in the pixel array includes A, B, C three sets of display control parameters, each set having 8 bits, for a total of 24 bits, where the a parameter is bit23-bit16, the B parameter is bit15-bit8, and the C parameter is bit7-bit 0. The display control storage unit 26 adopts a synchronous SRAM with a bit-based write operation function, and compared with a D flip-flop or a latch, the SRAM information storage density is higher and the cost is lower.
The SRAM bit width is 24 bits, the address is 8 bits, and the physical address space is 00H-FFH. When new display control parameters are written in through the interface module 10, the write enable signal generation circuit 24 and the write data selection circuit 22 respectively output different write enable signals WEN [23:0] and write data signals DI [23:0] to the SRAM for different register pages, the WEN signal is 24 bits, each bit controls whether a corresponding bit in the write data signal DI is written in the SRAM, WEN [ k ] is low and active, if WEN [ k ] is 0(k is 0-23), DI [ k ] is written in the SRAM, otherwise DI [ k ] is not written in the SRAM.
For example, referring to table 1, if only parameter a is updated in a write operation of PAGE 1, WEN is 0x00FFFF, parameter B is updated in a write operation of PGAE2, WEN is 0xFF00FF, and parameter C is updated in a write operation of PAGE3, WEN is 0xFFFF 00. For PAGE4 write operation, parameter a and parameter B can be modified simultaneously, WEN is 0x0000FF, SRAM is written every time I2C interface transfers 2 bytes, it needs to cache the first byte data in register ABUF first, and SRAM writing is executed only when the second byte is transferred. The write 24-bit data consists of ABUF, DIB, which is the second byte of data coming directly from the I2C interface. For PAGE5 write operation, all parameters can be modified, corresponding to that the SRAM is written once when the I2C interface transmits 3 bytes, the first 2 bytes of data are respectively latched to the registers ABUF and BBUF, and when the third byte is output, SRAM writing is executed once, WEN is 0x000000, and the written 24-bit data is composed of ABUF, BBUF and DIB.
Table 1 shows a transmission data table of the control parameter update process
In the driving chip provided in the embodiment of the present application, for a pixel array having multiple display control pixels, whether updating a single display control parameter or updating multiple display control parameters can be completed at one time through the write-through operation of the interface module 10, which greatly facilitates the operation of a user to quickly update display contents according to the sequence of pixel points. And the proportion of the display control parameters in the data transmitted by the interface module 10 in the driver chip is increased, that is, the proportion of the effective data transmitted by the interface module 10 in the total transmission data is increased, that is, when the same number of display control parameters are transmitted, the number of the total transmission data required to be transmitted by the interface module 10 is reduced, so that the requirement on the data transmission capability of the interface module 10 in the updating process of a plurality of display control parameters is reduced, and the probability that the data transmission capability of the interface module 10 is difficult to meet the requirement is reduced.
The embodiments in the present description are described in a progressive manner, each embodiment focuses on differences from other embodiments, and the same and similar parts among the embodiments are referred to each other.
The previous description of the disclosed embodiments is provided to enable any person skilled in the art to make or use the present application. Various modifications to these embodiments will be readily apparent to those skilled in the art, and the generic principles defined herein may be applied to other embodiments without departing from the spirit or scope of the application. Thus, the present application is not intended to be limited to the embodiments shown herein but is to be accorded the widest scope consistent with the principles and novel features disclosed herein.
Claims (8)
1. A method for updating display control parameters is applied to a driving chip, the driving chip is used for driving a pixel array comprising a plurality of display pixels to display, the driving chip comprises a display control storage unit which stores A display control parameters, P is more than 1, and the method for updating the display control parameters comprises the following steps:
acquiring a display updating instruction, wherein the display updating instruction comprises display control parameters and a parameter logic address, the parameter logic address comprises a control parameter group arranged according to the arrangement sequence of the display pixels of the pixel array, and the control parameter group comprises at least one display control parameter;
caching display control parameters of Q preset units, wherein Q is P-1;
determining the sequence of the physical addresses to be updated in the display control storage unit according to the parameter logical address;
and updating the display control parameters stored in the display control storage unit according to the sequence of the physical addresses to be updated by using the cached display control parameters and the display control parameters in the display updating instruction.
2. The method according to claim 1, wherein the updating the display control parameters stored in the display control storage unit according to the physical address sequence to be updated by using the cached display control parameters and the display control parameters in the display update instruction comprises:
writing the display control parameters of the Q cached preset units and the display control parameters of a preset unit after the cached display control parameters into the display control storage unit according to the sequence of the physical addresses to be updated by using the cached display control parameters of the Q cached preset units and the cached display control parameters of a preset unit after the display control parameters;
and judging whether the display control parameters in the display updating instruction are all written into the display control storage unit, if not, caching the display control parameters of the last Q preset units written with the display control parameters of the display control storage unit in the display updating instruction, returning the display control parameters of the last Q preset units cached with the display control parameters of the last preset units, and writing the display control parameters of the last preset units cached with the display control parameters of the last preset units into the display control storage unit according to the sequence of the physical addresses to be updated.
3. The method of claim 1, wherein the predetermined unit is a byte.
4. A driver chip for driving a pixel array display including a plurality of display pixels, the driver chip comprising: the interface module, the time sequence signal output module and the data signal output module are connected with the interface module; wherein,
the interface module is used for receiving a display updating instruction and a time sequence updating instruction;
the time sequence signal output module is used for outputting a selection switch signal according to time sequence control information, receiving the time sequence updating instruction and updating the time sequence control information according to a time sequence control parameter in the time sequence updating instruction;
the display updating instruction comprises display control parameters and parameter logical addresses, the parameter logical addresses comprise control parameter groups arranged according to the arrangement sequence of the display pixels of the pixel array, and the control parameter groups comprise at least one display control parameter;
the data signal output module includes: the display control device comprises a data selection unit, a display control storage unit and a data signal generation unit; wherein,
the data selection unit comprises Q storage registers, and the storage registers are used for caching the display control parameters; q is P-1, P is a kind of the display control parameter stored in the display control storage unit, and P > 1; the data selection unit is used for determining the sequence of physical addresses to be updated in the display control storage unit according to the parameter logical address, and updating the display control parameters stored in the display control storage unit according to the sequence of the physical addresses to be updated by using the cached display control parameters and the display control parameters in the time sequence updating instruction;
the data signal generating unit is used for generating a data driving signal according to the display control parameter stored in the display control storage unit and outputting the data driving signal to the pixel array.
5. The driver chip according to claim 4, wherein the data selecting unit updates the display control parameters stored in the display control storage unit according to the sequence of the physical addresses to be updated by using the cached display control parameters and the display control parameters in the display update instruction,
writing the display control parameters of the Q cached preset units and the display control parameters of a preset unit after the cached display control parameters into the display control storage unit according to the sequence of the physical addresses to be updated by using the cached display control parameters of the Q cached preset units and the cached display control parameters of a preset unit after the display control parameters;
and judging whether the display control parameters in the display updating instruction are all written into the display control storage unit, if not, caching the display control parameters of the last Q preset units written with the display control parameters of the display control storage unit in the display updating instruction, returning the display control parameters of the last Q preset units cached with the display control parameters of the last preset units, and writing the display control parameters of the last preset units cached with the display control parameters of the last preset units into the display control storage unit according to the sequence of the physical addresses to be updated.
6. The driver chip of claim 5, wherein the interface module comprises a first output, a second output, a third output, and a fourth output;
the data selection unit further includes: a write data selection circuit, a logic address storage circuit, a write enable signal generation circuit, and a write address selection circuit;
the storage register is connected with the first output end of the interface module and used for receiving and caching the display control parameters transmitted by the interface module;
the write data selection circuit comprises Q first input ends, a second input end and a third input end, the Q first input ends of the write data selection circuit are respectively connected with the storage register, and the second input end of the write data selection circuit is connected with the first output end of the interface module; the output end of the write data selection circuit is connected with the display control storage unit;
the input end of the logic address storage circuit is connected with the second output end of the interface module, and the output end of the logic address storage circuit is respectively connected with the second input end of the write enable signal generation circuit and the second input end of the write data selection circuit;
the first input end of the write address selection circuit is connected with the third output end of the interface module; the output end of the write address selection circuit is connected with the display control storage unit;
the first input end of the write data selection circuit is connected with the fourth output end of the interface module, and the output end of the write data selection circuit is connected with the display control storage unit;
the logic address storage circuit is used for storing the parameter logic address, the write enable signal generation circuit is used for generating a write enable signal according to the parameter logic address and transmitting the write enable signal to the display control storage unit, and the write enable signal comprises a first state and a second state;
the write data selection circuit is used for transmitting the display control parameters of the Q preset units cached by the Q storage registers and the display control parameters of one preset unit behind the cached display control parameters to the display control storage unit, and is also used for generating write data signals according to the parameter logical addresses and transmitting the write data signals to the display control storage unit, so that the display control storage unit writes the display control parameters of the Q cached preset units and the display control parameters of one preset unit behind the cached display control parameters into the display control storage unit under the control of the write data signals according to the sequence of the physical addresses to be updated; the write data signal is active when the write enable signal is in a first state.
7. The driving chip according to claim 4, wherein the display control storage unit is an SRAM or D flip-flop register set or a latch array.
8. The driver chip according to claim 4, wherein the predetermined unit is a byte.
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