CN113207209A - Data transmission method of single-wire cascade circuit and LED chip cascade system - Google Patents
Data transmission method of single-wire cascade circuit and LED chip cascade system Download PDFInfo
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Abstract
The invention provides a data transmission method of a single-wire cascade circuit and an LED chip cascade system, wherein the method comprises the following steps: when detecting that the input data is a set waveform, starting a decoding clock; generating a first data waveform at t1 and transmitting to a next stage circuit; sampling the input data waveform at t 2; when the bit is judged to be 0, changing the first data waveform into a second data waveform and stopping a decoding clock; when it is judged as bit 1, the first data waveform is changed to the second data waveform at t3 and the decoding clock is stopped; from when the decoding clock stops until the next t1, the second data waveform is single-line transmitted to the next-stage circuit. The high level duration of the output data is integral multiple of the decoding clock period, thereby avoiding the problem of gradual widening or narrowing of the high level caused by the transmission of the cascade circuit and solving the error code problem of data transmission. And the transmission time of the bit 0 is shortened, so that the overall data transmission speed of the LED chip cascade system is improved.
Description
Technical Field
The invention relates to the technical field of LED display, in particular to a data transmission method of a single-wire cascade circuit and an LED chip cascade system.
Background
The LED lamp has the characteristics of energy conservation, good chromaticity and long service life, and is widely applied. The number of lamp points which can be driven by a single LED chip is limited, and if a large-scale lamp decoration system or an LED display screen is to be realized, the LED chips need to be cascaded. Due to factors such as inconsistency of the processing process of the LED chips and changes of the application environment, the pulse width of the data signal in the data transmission process of the LED chip cascade system is gradually narrowed or widened, and even data error codes are caused, so that the data transmission is limited by the cascade number and the transmission distance. In practical application, for data transmission of the LED chip cascade system, not only the data transmission needs to be farther, but also the data transmission needs to be faster.
Disclosure of Invention
In order to solve the problems in the prior art, the invention provides a data transmission method of a single-wire cascade circuit and an LED chip cascade system.
The first aspect of the present invention provides a data transmission method for a single-wire cascade circuit, which includes:
the current-stage circuit detects an input data waveform, and when the input data waveform is detected to be a specific waveform, a decoding clock is started, and the starting time is t 0;
generating a first data waveform at time t1 and transmitting to a next stage circuit; the next stage circuit is connected with the current stage circuit through a single signal wire;
sampling and judging the input data waveform at a time t 2; when the input data is judged to be bit 0, changing the first data waveform into a second data waveform and stopping the decoding clock; when the input data is judged to be bit 1, changing the first data waveform into the second data waveform at time t3 and stopping the decoding clock; the second data waveform and the first data waveform are digital signal waveforms with two different levels;
the second data waveform is transmitted to the next stage circuit by a single line from when the decoding clock stops until the next time t 1.
Further, the air conditioner is provided with a fan,
the input data comprises the bit 0 and the bit 1;
the input data is represented by a return-to-zero code, which starts at a high level and ends at a low level;
the zeroing code duration for the bit 0 is T0, the T0 includes a high level duration T0H and a low level duration T0L;
the zeroing code duration for the bit 1 is T1, the T1 includes a high level duration T1H and a low level duration T1L;
the T1H is greater than the T0H, and the difference between the T1H and the T0H is greater than a set value;
the T1 is greater than or equal to the T0.
Further, the air conditioner is provided with a fan,
the particular waveform comprises a rising edge of the input data waveform;
the first data waveform is a high level waveform;
the second data waveform is a low level waveform.
Further, the air conditioner is provided with a fan,
the time t1 is the Kth falling edge of the decoding clock after the time t 0;
the T2 time is the Lth falling edge of the decode clock from the T1 time and after the T0H time;
the T3 time is the Mth falling edge of the decode clock since the T1 time and after the T1H time.
Further, the air conditioner is provided with a fan,
the decoding clock comprises a high-speed clock and a low-speed clock;
the period of the decode clock is less than or equal to the duration of T0H.
Further, the air conditioner is provided with a fan,
the T1H is greater than or equal to 2 times T0H;
the T0L and the T1L are both greater than or equal to the T0H.
The second aspect of the present invention provides an LED chip cascade system, which includes a plurality of LED chips cascaded with each other, wherein each of the LED chips is connected to a next-stage LED chip through a single signal line; each of the LED chips transmits data to the next stage of the LED chip by the data transmission method of the single-wire cascade circuit according to the first aspect of the present invention.
Further, the air conditioner is provided with a fan,
the data comprises a plurality of groups of data instructions, and each group of data instructions is used for the display driving of one LED chip; each set of the data instructions is adapted to express information for 3-way RGB or 4-way RGBW.
Further, the air conditioner is provided with a fan,
each LED chip extracts the data instruction for the LED chip at the current stage from the plurality of groups of data instructions and then transmits the rest of the data instructions to the LED chip at the next stage; the data instruction for the current stage is the first group of data instructions received by the LED chip of the current stage.
Further, the air conditioner is provided with a fan,
the LED chip comprises a filtering module, a decoding oscillation module, an output driving module, a conversion control module and an LED driving module,
the filtering module is used for filtering the input data waveform and then transmitting the input data waveform to the decoding module;
the decoding module is used for detecting the input data waveform, sampling and judging the input data waveform, generating a first data waveform and a second data waveform, and controlling the start and stop of a decoding clock; the decoding module is also used for extracting the data instruction of the current stage and transmitting the data instruction to the conversion control module;
the decoding oscillation module is used for generating the decoding clock and providing the decoding clock for the decoding module to use;
the output driving module is used for outputting the first data waveform and the second data waveform generated by the decoding module to the next-stage LED chip;
the conversion control module is used for converting the data instruction for the current stage into Pulse Width Modulation (PWM) data and then transmitting the PWM data to the LED driving module;
and the LED driving module is used for outputting the PWM data to an LED lamp and driving the LED lamp to display.
The invention generates a new return-to-zero code data waveform according to the input data bit and transmits the new return-to-zero code data waveform to the next-stage circuit, and the high level duration of the return-to-zero code data waveform is integral multiple of the decoding clock period of the current-stage circuit, thereby avoiding the problem that the high level is gradually widened or narrowed in the transmission process of a multi-stage cascade circuit, further solving the error code problem in data transmission and being capable of quickly transmitting data to the next-stage circuit. Compared with the prior art, the transmission time of the data bit 0 can be shortened, so that the overall data transmission speed of the LED chip cascade system is improved.
Drawings
Fig. 1 is a basic flowchart of a data transmission method of a single-wire cascade circuit according to an embodiment of the present invention;
FIG. 2 is a timing diagram illustrating the transmission of a data bit 0 according to an embodiment of the present invention;
FIG. 3 is a timing diagram of a data bit 1 transmission according to an embodiment of the present invention;
FIG. 4 is a diagram illustrating a return-to-zero code waveform according to an embodiment of the present invention;
FIG. 5 is a timing diagram illustrating the sequential transmission of data bit 0 and bit 1 according to an embodiment of the present invention;
FIG. 6 is a schematic diagram of a cascade of LED chip cascade systems according to an embodiment of the present invention;
fig. 7 is a block diagram of an LED chip according to an embodiment of the invention.
Detailed Description
Embodiments in accordance with the present invention will now be described in detail with reference to the drawings, wherein like reference numerals refer to the same or similar elements throughout the different views unless otherwise specified. It is to be noted that the embodiments described in the following exemplary embodiments do not represent all embodiments of the present invention. They are merely examples of apparatus and methods consistent with certain aspects of the present disclosure, as detailed in the claims, and the scope of the present disclosure is not limited in these respects. Features of the various embodiments of the invention may be combined with each other without departing from the scope of the invention.
Furthermore, the terms "first", "second" and "first" are used for descriptive purposes only and are not to be construed as indicating or implying relative importance or implicitly indicating the number of technical features indicated. Thus, a feature defined as "first" or "second" may explicitly or implicitly include at least one such feature. In the description of the present invention, "a plurality" means at least two, e.g., two, three, etc., unless specifically limited otherwise.
The invention provides a data transmission method of a single-wire cascade circuit in a first aspect. Fig. 1 is a basic flowchart of a data transmission method of a single-wire cascade circuit according to an embodiment of the present invention, fig. 2 is a timing diagram of data bit 0 transmission according to an embodiment of the present invention, fig. 3 is a timing diagram of data bit 1 transmission according to an embodiment of the present invention, and the following describes an embodiment of the present invention with reference to fig. 1, fig. 2, and fig. 3. As shown in fig. 1, a data transmission method of a single-wire cascade circuit according to an embodiment of the present invention includes steps S1 to S4:
in step S1, the present stage circuit detects an input data waveform, and starts a decoding clock when the input data waveform is detected to be a specific waveform, where the start time is t 0. In the embodiment of the invention, when no effective input data bit exists, the decoding oscillator of the circuit at the stage does not work, so that the electricity can be saved; as shown in fig. 2, when a rising edge of the input data waveform at the input terminal DIN is detected, the enable signal ENCK of the decoding oscillator is pulled high to enable the decoding oscillator to operate, providing the decoding clock CK for timing of subsequent data processing by the circuit of this stage.
Step S2, generating a first data waveform at time t1 and transmitting the first data waveform to a next-stage circuit; and the next stage circuit is connected with the current stage circuit through a single signal wire. In the embodiment of the present invention, as shown in fig. 2, the output data waveform supplied to the output terminal DOUT is pulled high at the time t1 of the first falling edge of the decoding clock CK, and the high level waveform is continuously transmitted to the next stage circuit until being pulled low at the time t2 or at the time t 3.
Step S3, sampling and determining the input data waveform at time t 2; when the input data is judged to be bit 0, changing the first data waveform into a second data waveform and stopping the decoding clock; when the input data is judged to be bit 1, changing the first data waveform into the second data waveform at time t3 and stopping the decoding clock; the second data waveform and the first data waveform are digital signal waveforms with two different levels. In the embodiment of the present invention, as shown in fig. 2, the input data waveform at the input terminal DIN is sampled and determined at the time of the second falling edge t2 of the decoding clock CK, and when it is determined to be low, the input data is regarded as bit 0, and the output data waveform sent to the output terminal DOUT is pulled low immediately; without being limited thereto, the time t2 may be at the third falling edge of CK (from the time CK starts), as long as the design requirements of the return-to-zero code bit 0 waveform are met (i.e., the high-level pulse width range of bit 0 is met). As shown in fig. 3, the input data waveform at the input terminal DIN is sampled and judged at the time of the second falling edge t2 of the decoding clock CK, and when judged to be high, the input data is regarded as bit 1, and the output data waveform at the output terminal DOUT is pulled low at the time of the third falling edge t3 of the decoding clock CK. As can be seen, the high level width of the output data waveform bit 0 is 1 CK cycle, and the high level width of the output data waveform bit 1 is 2 CK cycles. In fig. 2, the high level width of input data waveform bit 0 is exactly 1 CK cycle, so the output data waveform is exactly the same as the input data waveform; however, in fig. 3, the high level width of the input data waveform bit 1 is less than 2 CK cycles, while the high level width of the output data waveform bit 1 is 2 CK cycles, and it can be seen that the output data waveform is a set integer multiple of the decoding clock cycle, regardless of the high level width of the input data waveform. In the embodiment of the invention, because the return-to-zero code is adopted to represent the data bit, when the high-level transmission of the output data waveform is completed (namely when the output data waveform is pulled down), the effective part of the data waveform is transmitted, namely, whether the data is bit 0 or bit 1 can be distinguished, the decoding clock CK is not needed to count, and therefore, the decoding clock can be stopped to save power. In the embodiment of the present invention, as shown in fig. 2 and fig. 3, the waveform duration of the output data bit 0 is 2 CK, the waveform duration of the output data bit 1 is 3 CK, and the duration of the bit 0 is shorter, which is different from the waveform durations of the data bit 0 and the bit 1 in the prior art, so that the transmission of the bit 0 can be faster.
In step S4, the second data waveform is transmitted to the next stage circuit by a single line from when the decode clock stops until the next time t 1. In the embodiment of the present invention, when the decoding clock is stopped, the output data waveform (i.e. low level waveform) pulled down is continuously transmitted to the next stage circuit until a new input data comes and the decoding clock is started again after the rising edge of the input data waveform is detected (the next time t 0), and then the output data waveform is pulled up again at the first falling edge of CK (i.e. the next time t 1). In the embodiment of the present invention, the circuit will continuously detect the input signal when it is powered on, and as long as the valid data bit (return-to-zero code) is detected, the decoding clock will be started, and the above steps S1-S4 are performed cyclically from t0-t2 or t0-t 3.
In the embodiment of the invention, a new data waveform is generated in the circuit of the current stage according to the input data bit and is transmitted to the circuit of the next stage, the high level duration of the data waveform is integral multiple of the decoding clock period of the circuit of the current stage, the problem that the high level is gradually widened or narrowed in the transmission process of a multi-stage cascade circuit is avoided, the error code problem in data transmission is further solved, and the data can be quickly transmitted to the circuit of the next stage. Compared with the prior art, when the bit 0 is transmitted, the decoding clock is stopped when the high level of the bit 0 is finished, so that the power can be saved, and the transmission time of the bit 0 can be shortened, thereby improving the overall data transmission speed of the LED chip cascade system.
Alternatively,
the input data comprises the bit 0 and the bit 1;
the input data is represented by a return-to-zero code, which starts at a high level and ends at a low level;
the zeroing code duration for the bit 0 is T0, the T0 includes a high level duration T0H and a low level duration T0L;
the zeroing code duration for the bit 1 is T1, the T1 includes a high level duration T1H and a low level duration T1L;
the T1H is greater than the T0H, and the difference between the T1H and the T0H is greater than a set value;
the T1 is greater than or equal to the T0.
In the embodiment of the present invention, a return-to-zero code is used to represent data bit 0 and bit 1, the return-to-zero code is a coding method in which the signal level is restored to zero within one symbol, and is a kind of binary information coding, in which high-level pulses with different widths represent bit 0 and bit 1, respectively, and the zero level (low level) is maintained for a period of time after the pulse ends. As shown in fig. 4, the duty ratios of the high level and the low level of the bit 0 and bit 1 codes are different, the duration of the high level is the effective part, and the duration of the high level is also different. T0H represents the high level time required by bit 0, and the value range is 0.1us-1.0us, and the typical value is 0.8 us; T1H represents the high level time required by bit 1, and the value range is 1.4us-3.0us, and the typical value is 1.6 us; T0L represents the low time required for bit 0, T1L represents the low time required for bit 1, T0L and T1L range from 0.2us to 8.0us, typically 0.8 us. Generally, T1H is twice T0H, i.e., the above setting is T0H, which is beneficial for the decoding circuit to accurately sample identification bits 0 and 1. In the embodiment of the present invention, as shown in fig. 4, the sum of the high level and the low level of the bit 1 is T1, the sum of the high level and the low level of the bit 0 is T0, and T1 is greater than T0. Since the decoding circuit samples the input data signal as soon as possible after the high pulse of bit 0 ends to correctly identify whether the data is a 0 or a1, and the active portion (high) of bit 0 is complete, the low portion T0L of bit 0 may be shorter, as long as it is ensured that bit 0 is distinguished and a certain time margin is left for the input data sampling. In the prior art, T0 is the same as T1, but T0 of the invention is shorter, so that the transmission time of bit 0 is shortened, and the overall data transmission speed can be improved when a large amount of data is transmitted through a multi-stage circuit.
Alternatively,
the particular waveform comprises a rising edge of the input data waveform;
the first data waveform is a high level waveform;
the second data waveform is a low level waveform.
In the embodiment of the present invention, the decoding clock is started when data is input, and the decoding clock is started by detecting the rising edge of the return-to-zero code of the input data (i.e., the start point of the return-to-zero code). Because the return-to-zero code is adopted to represent the data bit, after the decoding clock is started, a high-level waveform (namely a first data waveform) can be generated as soon as possible and transmitted to a next-stage circuit; then, after the input return-to-zero code data is judged to be bit 0 or bit 1, the high-level waveform is pulled down to be a low-level waveform (namely, a second data waveform) at a specific moment according to the corresponding return-to-zero code high-level time length design requirement, and therefore the return-to-zero code high-level pulse of the output data waveform is generated. The present invention is not limited to the use of return-to-zero codes to represent data, and the design of the first and second data waveforms may be varied accordingly when other encoding schemes are used.
Alternatively,
the time t1 is the Kth falling edge of the decoding clock after the time t 0;
the T2 time is the Lth falling edge of the decode clock from the T1 time and after the T0H time;
the T3 time is the Mth falling edge of the decode clock since the T1 time and after the T1H;
when the current-stage circuit is in a power-on working state and the return-to-zero code is continuously transmitted through the input data waveform, the time t0, the time t1, the time t2 and the time t3 come and repeat in sequence.
In the embodiment of the present invention, as shown in fig. 5, when the rising edge of the input data waveform at the input terminal DIN comes, the decoding clock CK is started, which is t0 at this time; the output data waveform to the DOUT terminal is then pulled high on the first falling edge of CK, i.e. a first data waveform is generated, now t1, and the data waveform can be transferred early to the next stage circuit. Determining time t2 according to the high level duration of bit 0, and sampling the input data waveform at time t2 to determine whether it is bit 0 or bit 1, since the high level duration of bit 0 is 2 times the CK period in this embodiment, time t2 is at the 3 rd falling edge; when the input data is judged to be bit 0, the first data waveform (high level waveform) is pulled down to be the second data waveform (low level waveform) immediately to generate a high level pulse of the bit 0, and because the high level of the first data waveform lasts for 2 CK cycles at the time t2 and reaches the requirement of the high level duration of the bit 0, the output data waveform is pulled down immediately at the time t2 to keep the more consistent width of the high level of the bit 0 and meet the requirement of the sampling judgment time point of the next stage circuit. When the input data is determined to be bit 1, pulling down the first data waveform (high level waveform) to the second data waveform (low level waveform) at time t3 (i.e., the 5 th falling edge of CK) to generate a high level pulse of bit 1, where t3 is at the 5 th falling edge of CK because the high level of the first data waveform has continued for 4 CK cycles at time t3 and the high level duration requirement of bit 1 is reached; without being limited thereto, the time t3 may be at other time points as long as the high level duration range of bit 1 of the circuit design is satisfied. As shown in fig. 5, the transmission of bit 0 goes through t0, t1, t2, followed by the transmission of bit 1, goes through the next round of t0, t1, t2, t3, and so on, and the processes are repeated as long as the return-to-zero code data bits are input. In addition, the present invention is not limited to the use of CK falling edge timing, and CK rising edges may be used.
Alternatively,
the decoding clock comprises a high-speed clock and a low-speed clock;
the period of the decode clock is less than or equal to the duration of T0H.
In the embodiment of the invention, the decoding clock can be a high-speed clock or a low-speed clock, and in order to start data transmission and sample and judge input data in time, the CK period of the decoding clock is not more than the time length of T0H; in fig. 2 and 3, the CK period is the same as the time duration of T0H; in fig. 5, T0H is 2 times longer than the CK period. When the decoding clock is a high-speed clock, because the clock period is short, in order to ensure that the input data is correctly sampled, the time t2 can be selected to be at the 2 nd or 3 rd falling edge of the decoding clock CK; when the decoding clock is a low-speed clock, the 1 st falling edge of the decoding clock CK is selected at the time T2, so that the input data can be sampled and judged in time, the high level duration of the bit 0 which is more consistent with the designed T0H is output, and the transmission of the bit 0 can be finished in time. Without being limited thereto, the difference between T2 and T1 is larger than the high-level width of the input data bit 0 and is within the range of the design T0H. For the time T3, the value of M is 1, and the high level duration of bit 1, which is more consistent with the design T1H, can be output; the value of M is not limited to 1, as long as the difference between T3 and T1 is within the designed high level T1H range of the return-to-zero code bit 1. For the time t1, the value of K is 1, and data can be transmitted to the next stage circuit as soon as possible; the value of K is preferably 1, and the value of K is not limited to 1.
Alternatively,
the T1H is greater than or equal to 2 times T0H;
the T0L and the T1L are both greater than or equal to the T0H.
In the embodiment of the present invention, to distinguish bit 1 from bit 0, the duration of T1H is set to be more than 2 times the duration of T0H, so as to facilitate the decoding circuit to correctly sample and identify the input data bit. In view of saving data transfer time, T1H is generally set to 2 times T0H. In order to leave a certain margin for the sampling judgment time point of the input data decoding, the low level duration of bit 0 and bit 1 is not less than the high level duration of bit 0, otherwise, the sampling time point of bit 0 is shifted later, and the next data may be sampled to miss bit 0.
The second aspect of the present invention provides an LED chip cascade system, which includes a plurality of LED chips cascaded with each other, wherein each of the LED chips is connected to a next-stage LED chip through a single signal line; the LED chip transmits data to the next-stage LED chip by the data transmission method of the single-wire cascade circuit of the first aspect of the invention. In the embodiment of the present invention, as shown in fig. 6, N LED chips are cascaded, and the output terminal DOUT of each LED chip is connected to the input terminal DIN of the next-stage LED chip through a single signal line. The input end of the first LED chip at the first stage is connected to an external controller and receives data from the controller, and then the data are transmitted backwards step by step until the last Nth LED chip. Each stage of LED chip extracts data belonging to the stage of LED chip and transmits the rest data to the next stage of LED chip, and the transmission to the next stage of LED chip is suspended when the data of the stage of LED chip is extracted; when the data extraction of the chip at the current stage is finished, the data transmission method of the single-wire cascade circuit of the first part of the invention is adopted to transmit the rest data.
Alternatively,
the data comprises a plurality of groups of data instructions, each group of data instructions is used for display driving of one LED chip, and each group of data instructions is suitable for expressing information of 3 paths of RGB or 4 paths of RGBW.
Alternatively,
each LED chip extracts the data instruction for the LED chip at the current stage from the plurality of groups of data instructions and then transmits the rest of the data instructions to the LED chip at the next stage; the data instruction for the current stage is the first group of data instructions received by the LED chip of the current stage.
In the embodiment of the invention, data is transmitted in units of frames, one frame of data comprises a plurality of groups of data instructions, and each group of data instructions is used for the display driving of one LED chip. In fig. 6, Data1 includes N sets of Data commands for all N LED chips, Data2 includes N-1 sets of Data commands for the 2 nd to nth LED chips, and so on, and only 1 set of Data commands for the nth LED chip is provided by DataN. And when the last Nth LED chip receives the data instruction, the controller starts all the LED chips through the reset signal to drive the RGB display of the LED chip according to the current-level data instruction. In the embodiment of the invention, each group of data instructions consists of a plurality of data bits, and can express 3 paths of RGB or 4 paths of RGBW information, wherein each path of information is expressed by 1 or 2 bytes. Each set of data commands is converted to pulse width modulated PWM data to drive an RGB lamp display.
Alternatively,
the LED chip comprises a filtering module, a decoding oscillation module, an output driving module, a conversion control module and an LED driving module,
the filtering module is used for filtering the input data waveform and then transmitting the input data waveform to the decoding module;
the decoding module is used for detecting an input data waveform, sampling and judging the input data waveform, generating a first data waveform and a second data waveform, and controlling the start and stop of a decoding clock; the decoding module is also used for extracting the data instruction of the current stage and transmitting the data instruction to the conversion control module;
the decoding oscillation module is used for generating the decoding clock and providing the decoding clock for the decoding module to use;
the output driving module is used for outputting the first data waveform and the second data waveform generated by the decoding module to the next-stage LED chip;
the conversion control module is used for converting the data instruction into Pulse Width Modulation (PWM) data and then transmitting the PWM data to the LED driving module;
and the LED driving module is used for outputting the PWM data to an LED lamp and driving the LED lamp to display.
In the embodiment of the present invention, as shown in fig. 7, the LED chip includes a filtering module 701, a decoding module 702, a decoding oscillation module 704, an output driving module 703, a conversion control module 705, and an LED driving module 706. The modules complete the corresponding functions when the LED chip transmits data, and the modules are mutually matched to realize the data transmission method of the single-wire cascade circuit.
The invention generates a new return-to-zero code data waveform according to the input data bit and transmits the new return-to-zero code data waveform to the next-stage circuit, and the high level duration of the return-to-zero code data waveform is integral multiple of the decoding clock period of the current-stage circuit, thereby avoiding the problem that the high level is gradually widened or narrowed in the transmission process of a multi-stage cascade circuit, further solving the error code problem in data transmission and being capable of quickly transmitting data to the next-stage circuit. Compared with the prior art, the transmission time of the data bit 0 can be shortened, so that the overall data transmission speed of the LED chip cascade system is improved.
Although the present disclosure has been described above, the scope of the present disclosure is not limited thereto. Various changes and modifications may be effected therein by one of ordinary skill in the pertinent art without departing from the spirit and scope of the present disclosure, and these changes and modifications are intended to be within the scope of the present disclosure.
Claims (10)
1. A method for transmitting data in a single-wire cascade circuit, comprising:
the current-stage circuit detects an input data waveform, and when the input data waveform is detected to be a specific waveform, a decoding clock is started, and the starting time is t 0;
generating a first data waveform at time t1 and transmitting to a next stage circuit; the next stage circuit is connected with the current stage circuit through a single signal wire;
sampling and judging the input data waveform at a time t 2; when the input data is judged to be bit 0, changing the first data waveform into a second data waveform and stopping the decoding clock; when the input data is judged to be bit 1, changing the first data waveform into the second data waveform at time t3 and stopping the decoding clock; the second data waveform and the first data waveform are digital signal waveforms with two different levels;
the second data waveform is transmitted to the next stage circuit by a single line from when the decoding clock stops until the next time t 1.
2. The method for transmitting data in a single-wire cascade circuit according to claim 1,
the input data comprises the bit 0 and the bit 1;
the input data is represented by a return-to-zero code, which starts at a high level and ends at a low level;
the zeroing code duration for the bit 0 is T0, the T0 includes a high level duration T0H and a low level duration T0L;
the zeroing code duration for the bit 1 is T1, the T1 includes a high level duration T1H and a low level duration T1L;
the T1H is greater than the T0H, and the difference between the T1H and the T0H is greater than a set value;
the T1 is greater than or equal to the T0.
3. The method for transmitting data in a single-wire cascade circuit according to claim 2,
the particular waveform comprises a rising edge of the input data waveform;
the first data waveform is a high level waveform;
the second data waveform is a low level waveform.
4. The data transmission method of the single-wire cascade circuit according to claim 3,
the time t1 is the Kth falling edge of the decoding clock after the time t 0;
the T2 time is the Lth falling edge of the decode clock from the T1 time and after the T0H time;
the T3 time is the Mth falling edge of the decode clock since the T1 time and after the T1H time.
5. The method for transmitting data in a single-wire cascade circuit according to claim 4,
the decoding clock comprises a high-speed clock and a low-speed clock;
the period of the decode clock is less than or equal to the duration of T0H.
6. The data transmission method of the single-wire cascade circuit according to claim 3,
the T1H is greater than or equal to 2 times T0H;
the T0L and the T1L are both greater than or equal to the T0H.
7. An LED chip cascade system is characterized by comprising a plurality of LED chips which are cascaded mutually, wherein each LED chip is connected with the next-stage LED chip through a single signal wire; each of the LED chips transmits data to the next stage of the LED chip by the data transmission method of the single-wire cascade circuit as claimed in any one of claims 1 to 6.
8. The LED chip cascade system of claim 7,
the data comprises a plurality of groups of data instructions, and each group of data instructions is used for the display driving of one LED chip; each set of the data instructions is adapted to express information for 3-way RGB or 4-way RGBW.
9. The LED chip cascade system of claim 8,
each LED chip extracts the data instruction for the LED chip at the current stage from the plurality of groups of data instructions and then transmits the rest of the data instructions to the LED chip at the next stage; the data instruction for the current stage is the first group of data instructions received by the LED chip of the current stage.
10. The LED chip cascade system of claim 9, wherein the LED chip comprises a filtering module, a decoding oscillating module, an output driving module, a conversion control module, and an LED driving module,
the filtering module is used for filtering the input data waveform and then transmitting the input data waveform to the decoding module;
the decoding module is used for detecting the input data waveform, sampling and judging the input data waveform, generating a first data waveform and a second data waveform, and controlling the start and stop of a decoding clock; the decoding module is also used for extracting the data instruction of the current stage and transmitting the data instruction to the conversion control module;
the decoding oscillation module is used for generating the decoding clock and providing the decoding clock for the decoding module to use;
the output driving module is used for outputting the first data waveform and the second data waveform generated by the decoding module to the next-stage LED chip;
the conversion control module is used for converting the data instruction for the current stage into Pulse Width Modulation (PWM) data and then transmitting the PWM data to the LED driving module;
and the LED driving module is used for outputting the PWM data to an LED lamp and driving the LED lamp to display.
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