CN212324424U - Second pulse generating device and measuring system of digital clock - Google Patents
Second pulse generating device and measuring system of digital clock Download PDFInfo
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- CN212324424U CN212324424U CN202022023377.2U CN202022023377U CN212324424U CN 212324424 U CN212324424 U CN 212324424U CN 202022023377 U CN202022023377 U CN 202022023377U CN 212324424 U CN212324424 U CN 212324424U
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Abstract
The utility model relates to a pulse per second generating device and measurement system of digital clock belongs to digital clock measurement field. The second digit tube of the digital clock is detected by a photodiode, a plurality of detection signals are amplified by an amplifying circuit to obtain voltage signals, the voltage signals are compared with preset voltage, TTL level signals are output, the TTL level signals are sent to a pulse generating circuit directly or after being inverted by an inverter to generate pulse signals, finally the second pulse signals of the digital clock are generated by OR operation of a second pulse synthesizing circuit, reference time signals generated by a reference time frequency source are used as starting signals, the second pulse signals are used as stopping signals, time interval errors between the starting signals and the stopping signals are measured, and accurate measurement and calibration of the digital clock are further achieved.
Description
Technical Field
The utility model relates to a digital clock measurement field especially relates to a pulse per second generating device and measurement system of digital clock.
Background
In recent years, the time keeping and synchronization technology of digital clocks is rapidly developed, the time keeping precision is continuously improved, and a new problem is brought to the measurement of the digital clocks. At present, the measurement method of the digital clock mainly measures the signal output interface and determines the deviation of the signal output interface from the standard time through observation, but the method measures the time difference of the signal output interface, the time difference of the signal output interface cannot represent the time difference of the digital clock display time, and meanwhile, the time difference of the digital clock cannot be quantitatively measured through observation and comparison. In addition, the digital clock on the market at present basically has no function of outputting pulses per second, the time display resolution is not high, the digital clock is basically applied in a low-precision scene, and the specific analysis and measurement of the time keeping precision and the time deviation below the second level are difficult.
Disclosure of Invention
The utility model aims at providing a pulse per second generating device and measurement system of digital clock detects through the second digit tube to digital clock display element to produce pulse per second signal, and measure pulse per second signal, with the purpose that reaches the time difference below effective quantitative measurement digital clock second level, realize the accurate measurement and the calibration to the digital clock.
In order to achieve the above object, the utility model provides a following scheme:
a second pulse generating device of a digital clock comprises a photodiode, an amplifying circuit, a comparing circuit, a pulse generating circuit and a second pulse synthesizing circuit;
at least three segments of LEDs contained in a second digit tube of the digital clock are respectively connected with a photodiode; the photodiode is used for collecting the on-off signals of the LED connected with the photodiode and outputting corresponding current signals according to the on-off signals;
each amplifying circuit is connected with one photodiode; the amplifying circuit is used for converting the current signal output by the photodiode into a voltage signal;
each comparison circuit is connected with one amplification circuit; the comparison circuit is used for comparing the voltage signal output by the amplification circuit with a preset voltage and outputting a TTL level signal according to a comparison result; the preset voltage is between the output voltage value of the amplifying circuit corresponding to the LED which is not bright and the output voltage value of the amplifying circuit corresponding to the LED which is bright;
the output end of each comparison circuit is divided into two paths, one path is directly connected with the pulse generating circuit, the other path is connected with the phase inverter, and the other end of the phase inverter is connected with the other pulse generating circuit; the pulse generating circuit is used for outputting a pulse signal according to the received TTL level signal;
the pulse-per-second synthesis circuit is connected with all the pulse generating circuits; and the pulse-per-second synthesis circuit performs OR operation on all the pulse signals output by the pulse generation circuit through an OR gate and outputs pulse-per-second corresponding to the digital clock.
A measuring system of a digital clock comprises a second pulse generating device, a reference time frequency source and a time interval measuring instrument;
the second pulse generating device is respectively connected with a digital clock and the time interval measuring instrument; the pulse per second generating device is used for detecting the digital clock, outputting a pulse per second signal corresponding to the digital clock and transmitting the pulse per second signal to the time interval measuring instrument;
the reference time frequency source is connected with the time interval measuring instrument; the reference time frequency source is used for generating a reference time signal and transmitting the reference time signal to the time interval measuring instrument;
and the time interval measuring instrument measures a time interval error between the starting signal and the stopping signal by taking the received reference time signal as a starting signal and the received pulse per second signal as a stopping signal, wherein the time interval error is the time difference of the digital clock.
According to the utility model provides a concrete embodiment, the utility model discloses a following technological effect:
the utility model provides a pulse per second generating device of digital clock, detect the second digit pipe of digital clock through photodiode, it obtains voltage signal to pass through amplifier circuit amplification with multichannel detected signal, and send voltage signal into comparison circuit and predetermine voltage and carry out the comparison after, output TTL level signal, this TTL level signal is direct again or send into pulse generating circuit in order to produce pulse signal after the phase inverter looks, carry out or operate the second pulse signal that produces digital clock through pulse per second synthetic circuit at last, and then can realize the pulse per second output function of digital clock.
The utility model provides a measurement system of digital clock through the reference time signal that produces with reference time frequency source as the enabling signal to the pulse per second signal is as the stop signal, measures the time interval error between enabling signal and the stop signal, and then can reach the purpose of effective quantitative measurement digital clock time difference, realizes the accurate measurement and the calibration to the digital clock.
Drawings
In order to more clearly illustrate the embodiments of the present invention or the technical solutions in the prior art, the drawings required to be used in the embodiments will be briefly described below, and it is obvious that the drawings in the following description are only some embodiments of the present invention, and for those skilled in the art, other drawings can be obtained according to these drawings without creative efforts.
Fig. 1 is a schematic structural diagram of a pulse-per-second generator according to embodiment 1 of the present invention.
Fig. 2 is a schematic diagram of a second nixie tube according to embodiment 1 of the present invention.
Fig. 3 is a waveform diagram of an LED signal of the common anode nixie tube provided in embodiment 1 of the present invention.
Fig. 4 is a schematic circuit diagram of an amplifying circuit and a comparing circuit provided in embodiment 1 of the present invention.
Fig. 5 is a graph showing an output curve of the operational amplifier U1 in the amplifying circuit provided in embodiment 1 of the present invention.
Fig. 6 is a graph showing a relationship between an input voltage at a non-inverting input terminal and an input voltage at an inverting input terminal of a voltage comparator in a comparison circuit provided in embodiment 1 of the present invention.
Fig. 7 is a graph showing a relationship between an input voltage at an inverting input terminal of a voltage comparator and an output voltage of the voltage comparator in the comparison circuit provided in embodiment 1 of the present invention.
Fig. 8 is a graph showing a relationship between an input voltage at an inverting input terminal of a voltage comparator, an input voltage at a non-inverting input terminal of the voltage comparator, and an output voltage of the voltage comparator in the comparison circuit provided in embodiment 1 of the present invention.
Fig. 9 is a schematic circuit diagram of a pulse generating circuit according to embodiment 1 of the present invention.
Fig. 10 is a schematic structural diagram of a digital clock measurement system according to embodiment 2 of the present invention.
Detailed Description
The technical solutions in the embodiments of the present invention will be described clearly and completely with reference to the accompanying drawings in the embodiments of the present invention, and it is obvious that the described embodiments are only some embodiments of the present invention, not all embodiments. Based on the embodiments in the present invention, all other embodiments obtained by a person skilled in the art without creative work belong to the protection scope of the present invention.
The utility model aims at providing a pulse per second generating device and measurement system of digital clock detects through the second digit tube to digital clock display element to produce pulse per second signal, and measure pulse per second signal, in order to reach the purpose of effective quantitative measurement digital clock time difference, realize the accurate measurement and the calibration to digital clock.
In order to make the above objects, features and advantages of the present invention more comprehensible, the present invention is described in detail with reference to the accompanying drawings and the detailed description.
Example 1:
most of the digital clocks in the market do not have a function of outputting the second pulse, and therefore the time difference below the second level of the digital clock cannot be detected. As shown in fig. 1, the pulse per second generating device includes a photodiode, an amplifying circuit, a comparing circuit, a pulse generating circuit, and a pulse per second synthesizing circuit;
at least three segments of LEDs contained in a second digit tube of the digital clock are respectively connected with a photodiode; the photodiode is used for collecting the on-off signals of the LED connected with the photodiode and outputting corresponding current signals according to the on-off signals; the wavelength of an LED adopted by the digital clock is generally below 700nm, the photodiode can adopt a PIN silicon photodiode, further response can be well carried out in the wavelength range of the LED, the response time is in a nanosecond level, and on-off signals of the LED connected with the photodiode can be converted into current signals in real time. The photodiode is arranged above the LED to detect the on-off signals of the LED in real time.
Each amplifying circuit is connected with one photodiode; the amplifying circuit is used for converting the current signal output by the photodiode into a voltage signal;
each comparison circuit is connected with one amplification circuit; the comparison circuit is used for comparing the voltage signal output by the amplification circuit with a preset voltage and outputting a TTL level signal according to a comparison result; the preset voltage is between the output voltage value of the amplifying circuit corresponding to the LED which is not bright and the output voltage value of the amplifying circuit corresponding to the LED which is bright;
the output end of each comparison circuit is divided into two paths, one path is directly connected with the pulse generating circuit, the other path is connected with the phase inverter, and the other end of the phase inverter is connected with the other pulse generating circuit; the pulse generating circuit is used for outputting a pulse signal according to the received TTL level signal;
the pulse-per-second synthesis circuit is connected with all the pulse generating circuits; and the pulse-per-second synthesis circuit performs OR operation on all the pulse signals output by the pulse generation circuit through an OR gate and outputs pulse-per-second corresponding to the digital clock.
As shown in fig. 2, the second digit tube of the digital clock display unit is composed of seven segments of LEDs (light emitting diodes), which are respectively denoted by letters a to g. The digital clock can enable the second digit tube to display 10 digits of 0-9 by applying different signals to the seven-segment LED. The second nixie tube is divided into a common anode nixie tube and a common cathode nixie tube. For the common anode nixie tube, to display the number "0", signals of 0, 1 and 0, 0 and 1 should be applied to the segments a to g of LEDs respectively (0 represents a low level, at which the segment of LED is turned on, 1 represents a high level, at which the segment of LED is turned off), and when the common anode nixie tube is adopted, the waveforms of the signals of the second digit nixie tube of the digital clock from the numbers "0" to "9" are as shown in fig. 3.
As shown in fig. 3, when the second-digit nixie tube generates digital jump, a certain segment of the LED also generates on-off conversion, and thus the certain segment of the LED presents a rising edge or a falling edge of the voltage signal. For the second-digit nixie tube, a digital jump represents a new second, a second pulse is necessarily generated when the digital jump occurs, the second pulse for generating the digital clock is necessarily dependent on the digital jump of the second-digit nixie tube, and then the detection of the rising edge or the falling edge of the LED becomes the basis for generating the second pulse.
As shown in table 1, it is the corresponding relationship between the digital jump of the second digit code tube and the rising edge and falling edge of the seven-segment LED.
Table 1:
it can be easily found from observing fig. 3 and table 1 that it is not feasible to detect only the rising edge of the seven-segment LED or only the falling edge of the seven-segment LED, for example, when the number "0" jumps to the number "1", only the rising edge exists, and when the number "7" jumps to the number "8", only the falling edge exists, so that the signal detection for the seven-segment LED should include both the rising edge and the falling edge.
In addition, if the rising edges and the falling edges of the seven segments of LEDs are detected simultaneously, repeated detection signals are generated (during digital transition, the rising edges or the falling edges generated simultaneously by the different segments of LEDs are counted as the repeated detection signals), and in the worst case, 4 repeated detection signals are generated in one digital transition, and the detection signals interfere with each other. For example, when the number "0" jumps to the number "1", four repeated detection signals a, d, e, and f exist, and when the number "7" jumps to the number "8", four repeated detection signals d, e, f, and g exist, so that the factors causing interference mainly include the response time of the LED and the expansion of the response time of the detection method. Therefore, the logical relationship between the digital transition and the rising and falling edges of the LED signal should be found to reduce the generation of duplicate detection signals. By observing fig. 3 and table 1, it is found that only one segment of LED signal has a rising edge or a falling edge when some number generates a jump, for example, when the jump from the number "8" to the number "9", only the e segment of LED signal changes and presents a rising edge r1When the digital number '5' jumps to the digital number '6', only the e-segment LED signal changes and presents a falling edge r2Then the e segment LED must be detected. And the jump is carried out again because of the jump from the digital' 0In the 10-time digital jumping process of changing back to digital 0, the e-segment LED generates 8 digital jumping detection signals, only the detection signals of jumping from digital 3 to digital 4 and jumping from digital 4 to digital 5 are selected from other segment LEDs, the selection principle is that the quantity of the repeated detection signals with the e-segment LED is minimum, and the rising edge r of the b-segment LED meeting the condition is provided3Rising edge r of segment a LED4、r5Only r is5Compared with an e-segment LED which has repeated detection signals and only generates when the number jumps from '0' to '1', the method can reduce the generation of repeated detection signals to the maximum extent by only detecting the a-segment LED, the b-segment LED and the e-segment LED and further ensure the accuracy of finally generating the pulse per second by detecting the signals of the seven-segment LED.
It should be noted that although the presence of the repeated detection signal may affect the generation precision of the pulse per second, the presence of the repeated detection signal does not affect the generation of the pulse per second signal, that is, does not affect the implementation of the technical solution of this embodiment, in this embodiment, at least three segments of LEDs included in the digital second-digit nixie tube of the digital clock are respectively connected to a photodiode, and the three segments of LEDs, the four segments of LEDs, the five segments of LEDs, the six segments of LEDs, or the seven segments of LEDs included in the digital second-digit nixie tube may be simultaneously detected to detect the digital jump signal of the digital second-digit nixie tube. When the photodiode is connected with three sections of LEDs contained in a second digit tube of the digital clock in a one-to-one correspondence mode, the three sections of LEDs are respectively a section of LED, a section of LED b and a section of LED e of the second digit tube. When the photodiode is connected with four sections of LEDs contained in a second digit tube of the digital clock in a one-to-one correspondence mode, the four sections of LEDs comprise a section of LEDs, a section of LEDs and a section of LEDs, and any section of LEDs in other sections of LEDs. When the photodiode is connected with five sections of LEDs contained in a second digit tube of the digital clock in a one-to-one correspondence mode, the five sections of LEDs comprise any two sections of LEDs in other sections besides a section of LEDs, a section of LEDs and a section of LEDs. When the photodiode is connected with six sections of LEDs contained in a second digit digital tube of the digital clock in a one-to-one correspondence mode, the six sections of LEDs comprise any three sections of LEDs in other sections besides a section of LEDs, a section of LEDs and a section of LEDs. The photodiode can also be connected with seven segments of LEDs contained in a second digit tube of the digital clock in a one-to-one correspondence manner.
It should be noted that, except the above-mentioned three-segment LED, four-segment LED, five-segment LED and six-segment LED combination, all the combinations that can detect all digital jump signals should be within the protection scope of the present invention.
Further, as shown in fig. 4, the amplifying circuit includes an operational amplifier U1, a resistor R10, and a first power source VCC-8V; the inverting input end of the operational amplifier U1 is respectively connected with the photodiode PD1 and the resistor R10; the other end of the photodiode PD1 is grounded; the other end of the resistor R10 is connected with the output end of the operational amplifier U1; the output end of the operational amplifier U1 is the output end of the amplifying circuit; the first power supply VCC-8V is connected to the non-inverting input of the operational amplifier U1. Specifically, the connection mode of the first power supply VCC-8V connected to the non-inverting input terminal of the operational amplifier U1 is as follows: the first power source VCC-8V is connected with one end of a resistor R2, the other end of a resistor R2 is respectively connected with a resistor R1 and a resistor R3, the other end of the resistor R1 is grounded, and the other end of the resistor R3 is connected with the non-inverting input end of an operational amplifier U1.
The operational amplifier U1 works in a single power supply mode, a bias voltage is added to the non-inverting input end of the operational amplifier U1, the photodiode PD1 is at a zero point under the condition of no illumination, the additional time delay caused by a negative power supply when the photodiode PD1 responds does not occur, and the bias voltage also forms a reverse bias on the photodiode PD1 so as to reduce the junction capacitance and improve the operation speed.
The output voltage of the operational amplifier U1 is:
in the formula (1), VAMPIs the output voltage of the amplifying circuit; i isPD1Is the detection current of the photodiode;
in the amplifier circuit, when R1 is made equal to R2, formula (1) can be simplified as follows:
from the equation (2), the amplification factor of the operational amplifier U1 can be changed by adjusting the resistance of the resistor R10, and the calculation formula of R10 is as follows:
in the formula (3), IPD1(max)The maximum detection current of the photodiode; vAMP(min)For the bias voltage, when R1 is R2, the value of the bias voltage is
Namely 4V; vAMP(max)The maximum voltage output by the operational amplifier U1.
When I isPD1(max)60 mu A, VAMP(max)At 5V, the output curve of the operational amplifier U1 is shown in FIG. 5. Because the reverse current of the photodiode is very weak when the photodiode is not illuminated, and the reverse current is relatively large when the photodiode is illuminated, and the intensity of light emitted by the LED is always unchanged, it can be considered that the detection current of the photodiode is 0 when the LED detected by the photodiode is turned off, and the detection current of the photodiode is the maximum detection current when the LED detected by the photodiode is turned on, and the output voltage of the amplifying circuit is 4V when the LED is turned off by setting the resistance value of the resistor R10; when the LED is on, the output voltage of the amplifying circuit is 5V. And because the second digit tube adopts a common anode nixie tube, when a signal 0 is applied, the LED is on, and when a signal 1 is applied, the LED is off, so that the rising edge of the LED corresponds to the falling edge of the amplifying circuit.
Referring to fig. 4, the comparison circuit includes a voltage comparator U2, a second power supply VCC-5V, a third power supply VCC-5V, a resistor R4, a resistor R5, and a resistor R7; the inverting input end IN-of the voltage comparator U2 is connected with the output end of the amplifying circuit, and the output voltage of the amplifying circuit is the input voltage of the inverting input end of the voltage comparator U2; the second power supply VCC-5V is connected with a non-inverting input end IN + of the voltage comparator U2; the voltage output to the voltage comparator U2 by the second power supply VCC-5V is the preset voltage; one end of the resistor R7 is connected with a Q/OUT pin of the voltage comparator, and the other end of the resistor R7 is the output end of the comparison circuit; one end of the resistor R5 is connected with a # Q/OUT pin of the voltage comparator, and the other end of the resistor R5 is connected with the output end of the comparison circuit; a VCC + pin of the voltage comparator is respectively connected with the third power supply VCC-5V and the resistor R4; the other end of the resistor R4 is connected with the output end of the comparison circuit.
IN addition, the specific connection mode that the second power supply VCC-5V is connected to the non-inverting input terminal IN + of the voltage comparator U2 is as follows: the second power supply VCC-5V is connected with one end of a potentiometer R8, the other end of the potentiometer R8 is respectively connected with a resistor R9 and a non-inverting input end IN + of a voltage comparator U2, and the other end of the resistor R9 is grounded. Through calculation, when the resistance value of the potentiometer R8 ranges from (0-5) k Ω and the resistance value of R9 is 20k Ω, the input voltage V of the non-inverting input terminal of the voltage comparator U2 is foundTHIs adjustable in the range of (4-5) V, and the resistance value of the potentiometer R8 is adjusted to ensure that V is adjustedTH4.5V, the input voltage V of the inverting input terminal of the voltage comparator U2AMPInput voltage V of non-inverting input terminal of voltage comparator U2THThe graph of the relationship between the input voltage V and the inverted input voltage V of the voltage comparator U2 is shown in FIG. 6AMPAnd the output voltage V of the voltage comparator U2AThe graph of the relationship between them is shown in fig. 7.
In addition, fig. 6 and 7 are both graphs of the relationship obtained without considering the response time, and when the response time of the amplifier circuit and the comparator circuit is considered, the input voltage V at the inverting input terminal of the voltage comparator U2 is consideredAMPInput voltage V of non-inverting input terminal of voltage comparator U2THAnd the output voltage V of the voltage comparator U2AThe graph of the relationship between them is shown in fig. 8. In fig. 8, t1 is the setup time of the operational amplifier, t2 is the propagation delay of the voltage comparator, and the values of t1 and t2 change according to the model of the selected operational amplifier and voltage comparator. From FIG. 8, it can be seen thatThe output end of the circuit is connected with the inverting input end of the voltage comparator, the input voltage of the non-inverting input end of the voltage comparator is 4.5V, and when the output voltage of the amplifying circuit is 4V, the output voltage of the comparing circuit is 5V; when the output voltage of the amplifying circuit is 5V, the output voltage of the comparing circuit is 0V, and the falling edge of the amplifying circuit corresponds to the rising edge of the comparing circuit, so that the rising edge of the LED corresponds to the rising edge of the comparing circuit.
As shown in fig. 9, the pulse generating circuit includes a D flip-flop U3, a fourth power source VCC-5V, an inverter U4, and an RC charging circuit; the CLK pin of the D trigger U3 is connected with the output end of the comparison circuit; the fourth power supply VCC-5V is connected with a D pin of the D trigger; the RC charging circuit comprises a resistor R16 and a capacitor C11; one end of the resistor R16 is connected with a Q pin of the D trigger, and the other end of the resistor R16 is respectively connected with the inverter U4 and the capacitor C11; the other end of the inverter U4 is connected with an R pin of the D trigger; the other end of the capacitor C11 is grounded; and the Q pin of the D trigger is the output end of the pulse generating circuit.
After the photodiode detects the LED, the obtained detection signal is processed by the amplifying circuit and the comparing circuit to obtain a TTL level signal. In order to obtain a pulse signal corresponding to a digital clock second-digit nixie tube jump signal, an R end of a D trigger is required to be utilized and combined with an RC charging circuit to output a pulse signal with a certain pulse width when a CLK end of the D trigger has a rising edge. For the common anode nixie tube, the rising edge of the LED corresponds to the rising edge of a TTL level signal output by the comparison circuit, the TTL level signal is an input signal of a CLK pin of the D trigger, the D trigger can generate a pulse signal only when the input signal of the CLK pin has the rising edge, and in order to detect the rising edge and the falling edge of the LED at the same time, the output end of the comparison circuit needs to be divided into two paths, one path is directly connected with the pulse generation circuit, the other path is connected with the phase inverter, and the other end of the phase inverter is connected with the other pulse generation circuit. Specifically, for the rising edge of the LED, the output end of the comparison circuit is directly connected to the pulse generation circuit to generate the pulse signal corresponding to the rising edge of the LED, and for the falling edge of the LED, the output end of the comparison circuit is connected to the inverter first and then to the pulse generation circuit to generate the pulse signal corresponding to the falling edge of the LED.
The working principle of the pulse generating circuit is as follows: the TTL level signal is used as an input signal of a CLK pin of the D trigger U3, a direct-current voltage signal of a fourth power supply VCC-5V is used as an input signal of a D pin of the D trigger, when the TTL level signal changes from low level to high level, namely rising edge occurs, the output of a Q pin of the D trigger U3 is high level, and the charging time of the RC circuit is the pulse width of an output pulse. After the capacitor C11 is charged, the R pin of the D flip-flop U3 is at a low level, so that the Q pin of the D flip-flop U3 is cleared, thereby generating a pulse signal having a certain pulse width. The precision of the resistor and the capacitor in the RC circuit influences the stability of the pulse width of the pulse, but does not cause delay to the generation of the pulse signal.
After pulse signals respectively corresponding to the detected multiple sections of LEDs are obtained, the second pulse synthesizing circuit is used for carrying out OR operation on all the generated pulse signals, and then the second pulse signals corresponding to the digital clock can be obtained.
It should be noted that, in this embodiment, a specific solution is described only for the common-anode nixie tube, and it can be understood by those skilled in the art that the technical solution of this embodiment may also be applied to the common-cathode nixie tube, when the common-cathode nixie tube is adopted, since the common-cathode nixie tube applies a signal 0 to the LED, the LED is turned off; when signal 1 is applied to the LED, the LED is on. Therefore, the signal waveform of the second digit code tube is completely opposite to the signal waveform shown in fig. 3, and the corresponding relation between the digital jump and the rising edge and the falling edge of the LED is also completely opposite to the corresponding relation shown in table 1. For the common cathode nixie tube, for the falling edge of the LED, the output end of the comparison circuit is directly connected with the pulse generating circuit to generate the pulse signal corresponding to the falling edge of the LED, and for the rising edge of the LED, the output end of the comparison circuit is firstly connected with the phase inverter and then connected with the pulse generating circuit to generate the pulse signal corresponding to the rising edge of the LED.
In addition, in order to further reduce the occurrence of repeated detection signals, the rising edges and the falling edges of the a section, the b section and the e section are not detected at the same time, but for the common anode nixie tube, only the rising edge of the a section, the rising edge of the b section and the rising edge and the falling edge of the e section are detected; for the common cathode nixie tube, only the falling edge of the segment a, the falling edge of the segment b and the rising edge and the falling edge of the segment e are detected. Furthermore, the output end of the comparison circuit corresponding to the section a of LEDs is directly connected with the pulse generation circuit, and the output end of the comparison circuit corresponding to the section b of LEDs is directly connected with the pulse generation circuit; the output end of the comparison circuit corresponding to the e-section LED is divided into two paths, one path is directly connected with the pulse generating circuit, the other path is connected with the phase inverter, and the other end of the phase inverter is connected with the other pulse generating circuit.
Further, this embodiment also provides a second pulse generating method of a digital clock, which uses the second pulse generating device of the digital clock to operate, and the second pulse generating method includes the following steps:
step 101: collecting the on-off signals of the LED connected with the photodiode by using the photodiode, outputting corresponding current signals according to the on-off signals and transmitting the current signals to an amplifying circuit; the photodiode is arranged above the LED to detect the on-off signals of the LED in real time.
Step 102: converting the current signal into a voltage signal by using the amplifying circuit, and transmitting the voltage signal to a comparison circuit;
step 103: comparing the voltage signal with a preset voltage by using a comparison circuit, and outputting a TTL level signal according to a comparison result; the TTL level signal is divided into two paths, one path is directly transmitted to the pulse generating circuit, and the other path is transmitted to the other pulse generating circuit after passing through the phase inverter;
step 104: outputting a corresponding pulse signal by using a pulse generating circuit according to the received TTL level signal;
step 105: and performing OR operation on the pulse signals generated by all the pulse generating circuits by using a pulse-per-second synthesis circuit to obtain pulse-per-second signals of the digital clock.
As an optional implementation manner, when only the rising edge of a certain segment of LED or only the falling edge of a certain segment of LED is detected, if the LED belongs to the common anode nixie tube, and when the rising edge of the LED is detected, the TTL level signal output by the comparison circuit is only connected to the pulse generation circuit; when the falling edge of the LED is detected, the TTL level signal output by the comparison circuit is only connected with the inverter and then connected with the pulse generation circuit; if the LED belongs to a common cathode nixie tube, when the rising edge of the LED is detected, the TTL level signal output by the comparison circuit is only connected with the inverter firstly and then connected with the pulse generation circuit; when the falling edge of the LED is detected, the TTL level signal output by the comparison circuit is only connected with the pulse generation circuit.
Example 2:
the present embodiment is configured to provide a digital clock measurement system, as shown in fig. 10, the measurement system includes the pulse-per-second generation apparatus described in embodiment 1, a reference time frequency source, and a time interval measuring instrument;
the second pulse generating device is respectively connected with the digital clock and the time interval measuring instrument and arranged above the second digit digital tube of the digital clock display unit; the pulse per second generating device is used for detecting the digital clock, outputting a pulse per second signal corresponding to the digital clock and transmitting the pulse per second signal to the time interval measuring instrument;
the reference time frequency source is connected with the time interval measuring instrument; the reference time frequency source is used for generating a reference time signal and transmitting the reference time signal to the time interval measuring instrument;
and the time interval measuring instrument measures a time interval error between the starting signal and the stopping signal by taking the received reference time signal as a starting signal and the received pulse per second signal as a stopping signal, wherein the time interval error is the time difference of the digital clock.
Specifically, the reference time frequency source may be a rubidium atom frequency standard with GNSS, and the time interval measuring instrument may be a general counter with a time interval measuring function. The reference time signal generated by the reference time frequency source is the standard pulse per second signal 1 PPS. In addition, the reference time frequency source is also used for generating a reference frequency signal so as to calibrate the frequency of the time interval measuring instrument and improve the measurement accuracy of the time interval measuring instrument.
Further, this embodiment also provides a method for measuring a digital clock, which uses the above measurement system to perform work, and includes the following steps:
step 201: receiving a reference time signal generated by a reference time frequency source, and taking the reference time signal as a starting signal;
step 202: receiving a second pulse signal output by a second pulse generating device after detecting a digital clock, and taking the second pulse signal as a stop signal;
step 203: and measuring a time interval error between the starting signal and the stopping signal, wherein the time interval error is the time difference of the digital clock.
The embodiments in the present description are described in a progressive manner, each embodiment focuses on differences from other embodiments, and the same and similar parts among the embodiments are referred to each other.
The principle and the implementation of the present invention are explained herein by using specific examples, and the above description of the embodiments is only used to help understand the method and the core idea of the present invention; meanwhile, for the general technical personnel in the field, according to the idea of the present invention, there are changes in the concrete implementation and the application scope. In summary, the content of the present specification should not be construed as a limitation of the present invention.
Claims (10)
1. The second pulse generating device of a digital clock is characterized by comprising a photodiode, an amplifying circuit, a comparing circuit, a pulse generating circuit and a second pulse synthesizing circuit;
at least three segments of LEDs contained in a second digit tube of the digital clock are respectively connected with a photodiode; the photodiode is used for collecting the on-off signals of the LED connected with the photodiode and outputting corresponding current signals according to the on-off signals;
each amplifying circuit is connected with one photodiode; the amplifying circuit is used for converting the current signal output by the photodiode into a voltage signal;
each comparison circuit is connected with one amplification circuit; the comparison circuit is used for comparing the voltage signal output by the amplification circuit with a preset voltage and outputting a TTL level signal according to a comparison result; the preset voltage is between the output voltage value of the amplifying circuit corresponding to the LED which is not bright and the output voltage value of the amplifying circuit corresponding to the LED which is bright;
the output end of each comparison circuit is divided into two paths, one path is directly connected with the pulse generating circuit, the other path is connected with the phase inverter, and the other end of the phase inverter is connected with the other pulse generating circuit; the pulse generating circuit is used for outputting a pulse signal according to the received TTL level signal;
the pulse-per-second synthesis circuit is connected with all the pulse generating circuits; and the pulse-per-second synthesis circuit performs OR operation on all the pulse signals output by the pulse generation circuit through an OR gate and outputs pulse-per-second corresponding to the digital clock.
2. The clock-per-second generating device of claim 1, wherein the photodiode is connected to three segments of LEDs included in a second digit tube of the digital clock in a one-to-one correspondence; the three sections of LEDs are respectively an a section of LED, a b section of LED and an e section of LED of the second digit tube so as to detect the digital jump signal of the second digit tube.
3. The digital clock pulse-per-second generating apparatus according to claim 2,
the output end of the comparison circuit corresponding to the a-section LED is directly connected with the pulse generation circuit; the output end of the comparison circuit corresponding to the b-section LED is directly connected with the pulse generation circuit; the output end of the comparison circuit corresponding to the e-section LED is divided into two paths, one path is directly connected with the pulse generating circuit, the other path is connected with the phase inverter, and the other end of the phase inverter is connected with the other pulse generating circuit.
4. The apparatus for generating msec pulse according to claim 1, wherein the photodiode is connected in one-to-one correspondence with seven segments of LEDs included in a msec of the digital clock, so as to detect the digital transition signal of the msec.
5. The clock-per-second generating apparatus according to claim 1, wherein said amplifying circuit comprises an operational amplifier, a resistor R10, and a first power supply;
the inverting input end of the operational amplifier is respectively connected with the photodiode and the resistor R10; the other end of the photodiode is grounded; the other end of the resistor R10 is connected with the output end of the operational amplifier; the output end of the operational amplifier is the output end of the amplifying circuit; the first power supply is connected with the non-inverting input end of the operational amplifier.
6. The clock-per-second generating apparatus of a digital clock according to claim 5, wherein said amplifying circuit further comprises a resistor R1, a resistor R2, and a resistor R3;
the first power supply is connected with one end of the resistor R2, and the other end of the resistor R2 is respectively connected with the resistor R1 and the resistor R3; the other end of the resistor R1 is grounded; the other end of the resistor R3 is connected with the non-inverting input end of the operational amplifier.
7. The clock-per-second generating apparatus of a digital clock according to claim 1, wherein the comparing circuit includes a voltage comparator, a second power supply, a third power supply, a resistor R4, a resistor R5, and a resistor R7;
the inverting input end of the voltage comparator is connected with the output end of the amplifying circuit;
the second power supply is connected with the non-inverting input end of the voltage comparator; the voltage output by the second power supply is the preset voltage;
one end of the resistor R7 is connected with a Q/OUT pin of the voltage comparator, and the other end of the resistor R7 is the output end of the comparison circuit;
one end of the resistor R5 is connected with a # Q/OUT pin of the voltage comparator, and the other end of the resistor R5 is connected with the output end of the comparison circuit;
a VCC + pin of the voltage comparator is respectively connected with the third power supply and the resistor R4; the other end of the resistor R4 is connected with the output end of the comparison circuit.
8. The clock-per-second generating apparatus according to claim 7, wherein said comparing circuit further comprises a potentiometer R8 and a resistor R9;
the second power supply is connected with one end of the potentiometer R8, and the other end of the potentiometer R8 is respectively connected with the resistor R9 and the non-inverting input end of the voltage comparator; the other end of the resistor R9 is grounded.
9. The digital clock pulse-per-second generating device according to claim 1, wherein the pulse generating circuit comprises a D flip-flop, a fourth power supply, an inverter U4, and an RC charging circuit;
the CLK pin of the D trigger is connected with the output end of the comparison circuit;
the fourth power supply is connected with a D pin of the D trigger;
the RC charging circuit comprises a resistor R16 and a capacitor C11; one end of the resistor R16 is connected with a Q pin of the D trigger, and the other end of the resistor R16 is respectively connected with the inverter U4 and the capacitor C11; the other end of the inverter U4 is connected with an R pin of the D trigger; the other end of the capacitor C11 is grounded; and the Q pin of the D trigger is the output end of the pulse generating circuit.
10. A digital clock measuring system, comprising the pulse-per-second generating device of any one of claims 1-9, a reference time frequency source, and a time interval measuring instrument;
the second pulse generating device is respectively connected with a digital clock and the time interval measuring instrument; the pulse per second generating device is used for detecting the digital clock, outputting a pulse per second signal corresponding to the digital clock and transmitting the pulse per second signal to the time interval measuring instrument;
the reference time frequency source is connected with the time interval measuring instrument; the reference time frequency source is used for generating a reference time signal and transmitting the reference time signal to the time interval measuring instrument;
and the time interval measuring instrument measures a time interval error between the starting signal and the stopping signal by taking the received reference time signal as a starting signal and the received pulse per second signal as a stopping signal, wherein the time interval error is the time difference of the digital clock.
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Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN112235899A (en) * | 2020-09-16 | 2021-01-15 | 贵州省计量测试院 | Second pulse generating device and method of digital clock, and measuring system and method |
| CN113207209A (en) * | 2021-04-30 | 2021-08-03 | 深圳市美矽微半导体有限公司 | Data transmission method of single-wire cascade circuit and LED chip cascade system |
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2020
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Cited By (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN112235899A (en) * | 2020-09-16 | 2021-01-15 | 贵州省计量测试院 | Second pulse generating device and method of digital clock, and measuring system and method |
| CN112235899B (en) * | 2020-09-16 | 2024-05-28 | 贵州省计量测试院 | Second pulse generating device and method of digital clock, measuring system and method |
| CN113207209A (en) * | 2021-04-30 | 2021-08-03 | 深圳市美矽微半导体有限公司 | Data transmission method of single-wire cascade circuit and LED chip cascade system |
| CN113207209B (en) * | 2021-04-30 | 2022-08-30 | 深圳市美矽微半导体有限公司 | Data transmission method of single-wire cascade circuit and LED chip cascade system |
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