CN206863222U - Timing circuit, laser ranging circuit and laser range finder - Google Patents

Timing circuit, laser ranging circuit and laser range finder Download PDF

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Publication number
CN206863222U
CN206863222U CN201720602886.6U CN201720602886U CN206863222U CN 206863222 U CN206863222 U CN 206863222U CN 201720602886 U CN201720602886 U CN 201720602886U CN 206863222 U CN206863222 U CN 206863222U
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circuit
input
gate logic
signal
output end
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李碧洲
王欣欣
东尚清
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EPCO Microelectronics (Jiangsu) Co., Ltd
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Ai Puke Microelectronics (shanghai) Co Ltd
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Abstract

The application provides a kind of timing circuit, laser ranging circuit and laser range finder.Wherein, the timing circuit includes：Sequential translation circuit, integral operation circuit and analog to digital conversion circuit；The first input end of sequential translation circuit receives the emissioning controling signal of the first pulse, and the second input of sequential translation circuit receives the echo received signal of the first pulse；The input of the output end connection integral operation circuit of sequential translation circuit；The input of the output end connection analog to digital conversion circuit of integral operation circuit.The technical scheme of the application also provides a kind of laser ranging circuit and laser range finder.Timing circuit, laser ranging circuit and the laser range finder provided by the embodiment of the present application, simple in construction, cost is low.

Description

Timing circuit, laser ranging circuit and laser range finder
Technical field
The application is related to laser ranging technique field, more particularly to a kind of timing circuit, laser ranging circuit and Laser Measuring Distance meter.
Background technology
Pulse type laser ranging is a kind of e measurement technology for accurately and fast obtaining target range information, has detection range Far, the advantages that small volume.Its measuring principle is to calculate quilt by measuring the laser pulse signal of transmitting and the time difference of echo Ranging is from its formula is：S=ct/2, wherein s are tested distance, and c is the light velocity, and t is the laser pulse flight time.Thus formula Understand, because light beam is fixed c=3 × 106Km/s, measurement can be measured as long as measuring the flight time of laser pulse Distance of the instrument to measured target.Therefore pulsed laser ranging be technically characterized in that how to measure laser pulse flight time. The time of measurement is more accurate, and temporal resolution is higher, and ranging is more accurate, and precision is higher.
To realize high-precision measurement result in traditional ranging technology, using special timing chip (such as TDC-GP chips, Fpga chip etc.), circuit structure is complicated, and cost is higher.
Utility model content
The application provides a kind of timing circuit, laser ranging circuit and laser range finder.
A kind of timing circuit is provided according to the first aspect of the embodiment of the present application, including：Sequential translation circuit, integral operation Circuit and analog to digital conversion circuit；The first input end of the sequential translation circuit is used for the emission control letter for receiving the first pulse Number, the second input of the sequential translation circuit is used for the echo received signal for receiving first pulse；The sequential becomes The output end for changing circuit connects the input of the integral operation circuit；The output end of the integral operation circuit connects the mould The input of number change-over circuit；Wherein, the sequential translation circuit is believed according to the emissioning controling signal and the echo reception Number the second pulse signal of output, the pulsewidth of second pulse signal according to reception time of the emissioning controling signal with it is described The time interval received between the time of echo received signal determines；The integral operation circuit turns second pulse signal Voltage signal is changed to, and is exported to analog-digital conversion circuit as described；The voltage signal is converted to number by analog-digital conversion circuit as described Word signal, the information of the time interval is carried in the data signal.
Further, the sequential translation circuit includes set-reset flip-floop；The S ends of the set-reset flip-floop are used to receive the hair Control signal is penetrated, the R ends of the set-reset flip-floop are used to receive the echo received signal, the Q ends connection institute of the set-reset flip-floop State the input of integral operation circuit.
Further, the set-reset flip-floop includes the first nor gate logic circuit and the second nor gate logic circuit；It is described The input and output end of first nor gate logic circuit and an input of the second nor gate logic circuit and Output end interconnection；Another input of the first nor gate logic circuit is used to receive the emission control letter Number；Another input of the second nor gate logic circuit is used to receive the echo received signal, described second or The output end of NOT gate logic circuit connects the input of the integral operation circuit.
Further, the set-reset flip-floop include the first NAND gate logic circuit, the second NAND gate logic circuit, the 3rd with NOT gate logic circuit and the 4th NAND gate logic circuit；An input and output end for the first NAND gate logic circuit With an input of the second NAND gate logic circuit and output end interconnection；The first NAND gate logic circuit Another input connects the output end of the 4th NAND gate logic circuit；The second NAND gate logic circuit another Input connects the output end of the 3rd NAND gate logic circuit, the output end connection institute of the second NAND gate logic circuit State the input of integral operation circuit；Two inputs of the 3rd NAND gate logic circuit simultaneously receive the transmitting control after connecing Signal processed；Two inputs of the 4th NAND gate logic circuit simultaneously receive the echo received signal after connecing.
Further, the integral operation circuit includes operational amplifier, first resistor, second resistance and electric capacity；It is described The in-phase input end of operational amplifier connects the output end of the sequential translation circuit；The inverting input of the operational amplifier One end of the first resistor, the second resistance and electric capacity is connected respectively；The other end connection voltage source of the first resistor, The other end ground connection of the second resistance, the other end of the electric capacity connect the output end of the operational amplifier.
Further, the both ends of the electric capacity are parallel with 3rd resistor.
Further, also gone here and there between the output end of the in-phase input end of the operational amplifier and the sequential translation circuit It is associated with the 4th resistance.
A kind of laser ranging circuit, including processor and above-mentioned timing are provided according to the second aspect of the embodiment of the present application Circuit；The processor connects the output end of the analog to digital conversion circuit in the timing circuit；Wherein, the processor receives institute The data signal of analog to digital conversion circuit output is stated, and is calculated according to the information of the time interval carried in the data signal Target range.
A kind of laser range finder, including controller, generating laser, light are provided according to the third aspect of the embodiment of the present application Electric explorer and above-mentioned laser ranging circuit；The control terminal of the controller connects the generating laser and described respectively The first input end of sequential translation circuit；The photodetector connects the second input of the sequential translation circuit；Wherein, When the control terminal exports the emissioning controling signal of first pulse, the first pulse described in the laser transmitter projects；Institute When stating photodetector and detecting the echo impulse of the first pulse, the echo received signal of first pulse is exported.
In the embodiment of the present application, sequential translation circuit, integral operation circuit and analog to digital conversion circuit composition meter can be used When circuit, laser range finder is calculated from transmitting pulse signal to the time difference received echo-signal, during for according to this Between difference calculate target range between laser range finder distance objective thing, relative to using special timing core in the prior art Simple in construction for piece, cost is low.
It should be appreciated that the general description and following detailed description of the above are only exemplary and explanatory, not The application can be limited.
Brief description of the drawings
Accompanying drawing herein is merged in specification and forms the part of this specification, shows and meets the application implementation Example, and for explaining principle of the invention together with specification.
Fig. 1 is a kind of structural representation of timing circuit shown in the exemplary embodiment of the application one；
Fig. 2 is the structural representation of another timing circuit shown in the exemplary embodiment of the application one；
Fig. 3 is the structural representation of another timing circuit shown in the exemplary embodiment of the application one；
Fig. 4 is the structural representation of another timing circuit shown in the exemplary embodiment of the application one；
Fig. 5 is a kind of structural representation of laser ranging circuit shown in the exemplary embodiment of the application one；
Fig. 6 is a kind of structural representation of laser range finder shown in the exemplary embodiment of the application one.
Embodiment
Here exemplary embodiment will be illustrated in detail, its example is illustrated in the accompanying drawings.Following description is related to During accompanying drawing, unless otherwise indicated, the same numbers in different accompanying drawings represent same or analogous key element.Following exemplary embodiment Described in embodiment do not represent all embodiments consistent with the application.On the contrary, they be only with it is such as appended The example of the consistent apparatus and method of some aspects be described in detail in claims, the application.
It is only merely for the purpose of description specific embodiment in term used in this application, and is not intended to be limiting the application. " one kind " of singulative used in the application and appended claims, " described " and "the" are also intended to including majority Form, unless context clearly shows that other implications.
The method of measurement laser time of flight has pulse counting method and digital insertion at present.Wherein, pulse counting method one As be to be counted by high-precision time interval unit inside special chip, timer is begun incrementally counting up when launching pulse, Stop counting when receiving pulse, the time difference is calculated by count value.This method by electronic component and circuit due to being set The limitation of meter and production technology, general is difficult that pulse count frequency is done into height, when required precision is higher than 0.5m, pulse frequency More than 660MH must be reached, circuit common can not be realized substantially.Digital insertion is usually using large-scale special integrated electricity Road causes range accuracy to greatly improve, but circuit structure is complicated, and cost is high, it is difficult to produce in batches, difficult popularization and application.
Based on this, the embodiment of the present application provides a kind of timing circuit, can both improve the meter of laser pulse flight time Precision is calculated, circuit cost can be reduced again.As shown in Figure 1.
Fig. 1 is a kind of structured flowchart of timing circuit 10 of the exemplary embodiment of the application one.When timing circuit 10 includes Sequence translation circuit 11, integral operation circuit 12 and analog to digital conversion circuit 13.
Wherein, the first input end 111 of sequential translation circuit 11 is used for the emissioning controling signal for receiving the first pulse, sequential Second input 112 of translation circuit 11 is used for the echo received signal for receiving the first pulse；The output of sequential translation circuit 11 The input 121 of the connection integral operation of end 113 circuit 12；The output end 122 of integral operation circuit 12 connects analog to digital conversion circuit 13 input 131；Wherein, sequential translation circuit 11 is defeated according to the emissioning controling signal of reception and the echo received signal of reception Go out the second pulse signal, the pulsewidth of the second pulse signal is according to the reception time of emissioning controling signal and connecing for echo received signal Time interval between time receiving determines；Second pulse signal is converted to voltage signal by integral operation circuit 12, and is exported extremely Analog to digital conversion circuit 13；Voltage signal is converted to data signal by analog to digital conversion circuit 13, and the time is carried in data signal The information at interval.
In the embodiment of the present application, the first arteries and veins is launched when generating laser receives the emissioning controling signal of the first pulse Punching, meanwhile, the first input end 111 of sequential translation circuit 11 also receives the emissioning controling signal of first pulse.First arteries and veins When punching flight is to measured target, reflected through measured target, when the echo impulse being reflected back is received by a photoelectric detector, photodetection Device sends the echo received signal of the first pulse to the second input 112 of sequential translation circuit 11.
When first input end 111 receives the emissioning controling signal of the first pulse, show that generating laser starts to send First pulse, during the first pulse flight to the measured target, through measured target reflected echo pulses, when the second input 112 connects When receiving the echo received signal of the first pulse, illustrate that photodetector receives the echo impulse of reflection, sequential translation circuit 11 export the second pulse signal according to the emissioning controling signal of the first pulse and the echo received signal of the first pulse, wherein, the The pulsewidth of two pulse signals receives time and the time received between the time of echo received signal according to emissioning controling signal Interval determines, i.e. can calculate the time interval according to the pulsewidth of the second pulse signal.Integral operation circuit 12 is by the second arteries and veins Rush signal and be converted to voltage signal, then, voltage signal is converted to data signal by analog to digital conversion circuit 13, wherein, numeral letter The information of the time interval is carried in number.Therefore, the timing circuit 10 in the embodiment of the present application, sequential conversion electricity can be used Road 11, integral operation circuit 12 and analog to digital conversion circuit 13 form timing circuit 10, calculate transmitting pulse to receiving echo Time difference between pulse, circuit structure is simple, cost-effective.
In the embodiment of the present application, sequential translation circuit 11 can include set-reset flip-floop；The S ends of set-reset flip-floop are used to receive Emissioning controling signal, the R ends of set-reset flip-floop are used to receive echo received signal, the Q ends connection integral operation circuit of set-reset flip-floop 12 input 121.
In an optional embodiment, set-reset flip-floop includes the first nor gate logic circuit O1 and the second nor gate logic electricity Road O2, as shown in Figure 2.
Wherein, a first nor gate logic circuit O1 input and output end are with the second nor gate logic circuit O2's One input and output end interconnection, i.e.,：A first nor gate logic circuit O1 input connects the second nor gate Logic circuit O2 output end (i.e. the Q ends of set-reset flip-floop), the second nor gate logic circuit O2 input connection first Nor gate logic circuit O1 output end；First nor gate logic circuit O1 another input (i.e. S of set-reset flip-floop End) it is used to receive emissioning controling signal；Second nor gate logic circuit O2 another input (i.e. the R ends of set-reset flip-floop) For receiving echo received signal, the second nor gate logic circuit O2 output end (i.e. the Q ends of set-reset flip-floop) connection integration fortune Calculate the input 121 of circuit 12.In the present embodiment, the truth table of set-reset flip-floop is as shown in table 1, wherein, QnFor the n-th moment The state at Q ends, Qn+1For (n+1)th the moment Q end state.
Table 1：Set-reset flip-floop truth table
S R Qn+1 State (function)
0 0 Qn Keep
0 1 0 Set to 0
1 0 1 Put 1
1 1 1 It is indefinite
It follows that when S terminations receive emissioning controling signal, S ends are high level, and R ends are low level, hence in so that SR Trigger exports high level signal, i.e., Q ends are high level, and are always maintained at high level state, is connect until R terminations receive echo During the collection of letters, R ends are high level, and S ends are low level so that set-reset flip-floop exports low level signal, i.e. Q ends are low level.Cause This, time difference when receiving echo received signal with R terminations when S terminations receive emissioning controling signal exports equal to set-reset flip-floop High level signal duration, the i.e. time difference are corresponding with the pulsewidth for the second pulse that set-reset flip-floop exports.
In another optional embodiment, set-reset flip-floop includes the first NAND gate logic circuit A1, the second NAND gate logic Circuit A2, the 3rd NAND gate logic circuit A3 and the 4th NAND gate logic circuit A4, as shown in Figure 3.
Wherein, a first NAND gate logic circuit A1 input and output end are with the second NAND gate logic circuit A2's One input and output end interconnection, i.e.,：A first NAND gate logic circuit A1 input connects the second NAND gate Logic circuit A2 output end (i.e. the Q ends of set-reset flip-floop), the second NAND gate logic circuit A2 input connection first NAND gate logic circuit A1 output end.
First NAND gate logic circuit A1 another input connects the 4th NAND gate logic circuit A4 output end, the Two NAND gate logic circuit A2 another input connects the 3rd NAND gate logic circuit A3 output end, and the second NAND gate is patrolled Collect the input 121 of circuit A2 output end (i.e. the Q ends of set-reset flip-floop) connection integral operation circuit 12；3rd NAND gate logic Circuit A3 two inputs and connect (i.e. the S ends of set-reset flip-floop) be followed by receive emissioning controling signal；4th NAND gate logic circuit A4 two inputs are simultaneously received back to ripple reception signal after connecing (i.e. the R ends of set-reset flip-floop).Set-reset flip-floop in the embodiment of the present application Operation principle it is similar with the operation principle of the set-reset flip-floop in embodiment illustrated in fig. 2, will not be repeated here.
In the embodiment of the present application, as shown in Fig. 2 or Fig. 3, integral operation circuit 12 includes operational amplifier, the first electricity Hinder R1, second resistance R2 and electric capacity C；The output end 113 of the in-phase input end connection sequential translation circuit 11 of operational amplifier；Fortune The inverting input for calculating amplifier connects first resistor R1, second resistance R2 and electric capacity C one end respectively；First resistor R1's is another One end connects voltage source, second resistance R2 other end ground connection, the output end of electric capacity C other end concatenation operation amplifier.
The pulse width time of the second pulse can be calculated by integral operation circuit 12, and pulse width time signal is converted into electricity Signal is pressed, is carried in the voltage signal when sequential translation circuit 11 receives emissioning controling signal with receiving echo received signal When time difference information.In the present embodiment, pulse width time T can be obtained by below equation：
T=C*R2* (U2-U1)/U；
Wherein, C is the value of electric capacity C in Fig. 3, and R2 is the value of resistance R2 in Fig. 3, and U1 is that sequential translation circuit 11 receives hair When penetrating control signal, the magnitude of voltage of the output of integral operation circuit 12, U2 is that sequential translation circuit 11 receives echo received signal When, the magnitude of voltage of the output of integral operation circuit 12, U is the operating voltage of sequential translation circuit 11, for example can be 3.3V.
In another optional embodiment, Fig. 4 is refer to, electric capacity C both ends are parallel with 3rd resistor R3,3rd resistor R3 Error requirements can be reduced for preventing the saturation or cut off phenomenon caused by integrator drift.
In another optional embodiment, please continue to refer to Fig. 4, in-phase input end and sequential the conversion electricity of operational amplifier The 4th resistance R4 is also in series between the output end 113 on road 11.4th resistance R4 can be used for compensating caused by bias current Imbalance, the 4th resistance R4 resistance can be decided according to the actual requirements.
In the embodiment of the present application, analog to digital conversion circuit 13 can include analog-digital converter, for by integral operation circuit The electric signal of 12 outputs is converted into data signal.In an optional embodiment, the analog-digital converter of 12 can be selected, so Analog signal can be encoded into 4096 different centrifugal pumps.Therefore, 1/4096 resolution ratio is can reach, can so be reached Higher computational accuracy.So in other embodiments, the analog-digital converter of other digits can also be selected, in the embodiment of the present application It is not construed as limiting.
The present embodiment can use sequential translation circuit 11, integral operation circuit 12 and analog to digital conversion circuit 13 to form timing Circuit 10, transmitting pulse signal is calculated to the time difference received between echo-signal, relative in the prior art using special Simple in construction for timing chip, cost is low.Moreover, analog to digital conversion circuit can use the analog-digital converter of high-order output, It is high to the time difference received between echo impulse, computational accuracy so as to calculate the first pulse of transmitting.
Fig. 5 is a kind of structural representation of laser ranging circuit 50 shown in the exemplary embodiment of the application one, such as Fig. 5 institutes Show, laser ranging circuit 50 includes processor 51 and timing circuit 10.Wherein, processor 51 connects the modulus in timing circuit 10 The output end 132 of change-over circuit 13；Wherein, processor 51 receives the data signal that analog to digital conversion circuit 13 exports, and according to number The information of the time interval carried in word signal calculates target range.In the embodiment of the present application, target range s calculation is such as Under：
S=ct/2, wherein s are tested distance, and c is the light velocity (c=3 × 106Km/s), t is the laser pulse flight time.
Fig. 6 is a kind of structural representation of laser range finder 60 shown in the exemplary embodiment of the application one, including control Device 61, generating laser 62, photodetector 63 and laser ranging circuit 50；The control terminal of controller 61 connects laser respectively The first input end 111 of transmitter 62 and sequential translation circuit 11；Photodetector 63 connects the second of sequential translation circuit 11 Input 112；Wherein, when control terminal exports the emissioning controling signal of the first pulse, generating laser 62 launches the first pulse；Light When electric explorer 63 detects the echo impulse of the first pulse, the echo received signal of the first pulse is exported.It is optional real one Apply in example, the processor 51 in controller 61 and laser ranging circuit 50 may be integrally incorporated in an integrated circuit, such as monolithic Machine, analog to digital conversion circuit 13 can use AD (analog-to-digital conversion) module in single-chip microcomputer, so, can use existing circuit elements Part realizes the scheme of the embodiment of the present application, saves circuit cost.In another optional embodiment, controller 61, processor 51 And analog to digital conversion circuit 13 can also be the circuit element being separately provided, and not limited in the embodiment of the present application.
The present embodiment can use sequential translation circuit 11, integral operation circuit 12 and analog to digital conversion circuit 13 to form timing Circuit 10, laser range finder 60 is calculated from transmitting pulse signal to the time difference received echo-signal, so that basis should Time difference calculates the target range between the distance objective thing of laser range finder 60, relative in the prior art using based on special When chip for, simple in construction, cost is low.Moreover, analog to digital conversion circuit can use the analog-digital converter of high-order output, so as to count It is high to the time difference received between echo impulse, computational accuracy to calculate the first pulse of transmitting.
The preferred embodiment of the application is the foregoing is only, not limiting the application, all essences in the application God any modification, equivalent substitution and improvements done etc., should be included within the scope of the application protection with principle.

Claims (9)

  1. A kind of 1. timing circuit, it is characterised in that including：Sequential translation circuit, integral operation circuit and analog to digital conversion circuit；
    The first input end of the sequential translation circuit is used for the emissioning controling signal for receiving the first pulse, the sequential conversion electricity Second input on road is used for the echo received signal for receiving first pulse；
    The output end of the sequential translation circuit connects the input of the integral operation circuit；
    The input of the output end connection analog-digital conversion circuit as described of the integral operation circuit；
    Wherein, the sequential translation circuit exports the second pulse letter according to the emissioning controling signal and the echo received signal Number, the pulsewidth of second pulse signal is according to the reception time of the emissioning controling signal and connecing for the echo received signal Time interval between time receiving determines；Second pulse signal is converted to voltage signal by the integral operation circuit, and Export to analog-digital conversion circuit as described；The voltage signal is converted to data signal, the numeral by analog-digital conversion circuit as described The information of the time interval is carried in signal.
  2. 2. timing circuit according to claim 1, it is characterised in that the sequential translation circuit includes set-reset flip-floop；
    The S ends of the set-reset flip-floop are used to receive the emissioning controling signal, and the R ends of the set-reset flip-floop are used to receive described return Ripple reception signal, the Q ends of the set-reset flip-floop connect the input of the integral operation circuit.
  3. 3. timing circuit according to claim 2, it is characterised in that the set-reset flip-floop includes the first nor gate logic electricity Road and the second nor gate logic circuit；
    The input and output end of the first nor gate logic circuit with one of the second nor gate logic circuit Input and output end interconnection；
    Another input of the first nor gate logic circuit is used to receive the emissioning controling signal；
    Another input of the second nor gate logic circuit is used to receive the echo received signal, described second or The output end of NOT gate logic circuit connects the input of the integral operation circuit.
  4. 4. timing circuit according to claim 2, it is characterised in that the set-reset flip-floop includes the first NAND gate logic electricity Road, the second NAND gate logic circuit, the 3rd NAND gate logic circuit and the 4th NAND gate logic circuit；
    The input and output end of the first NAND gate logic circuit with one of the second NAND gate logic circuit Input and output end interconnection；
    Another input of the first NAND gate logic circuit connects the output end of the 4th NAND gate logic circuit；
    Another input of the second NAND gate logic circuit connects the output end of the 3rd NAND gate logic circuit, institute The output end for stating the second NAND gate logic circuit connects the input of the integral operation circuit；
    Two inputs of the 3rd NAND gate logic circuit simultaneously receive the emissioning controling signal after connecing；
    Two inputs of the 4th NAND gate logic circuit simultaneously receive the echo received signal after connecing.
  5. 5. timing circuit according to claim 1, it is characterised in that the integral operation circuit include operational amplifier, First resistor, second resistance and electric capacity；
    The in-phase input end of the operational amplifier connects the output end of the sequential translation circuit；
    The inverting input of the operational amplifier connects one end of the first resistor, the second resistance and electric capacity respectively；
    The other end connection voltage source of the first resistor, the other end ground connection of the second resistance, the other end of the electric capacity Connect the output end of the operational amplifier.
  6. 6. timing circuit according to claim 5, it is characterised in that the both ends of the electric capacity are parallel with 3rd resistor.
  7. 7. timing circuit according to claim 5, it is characterised in that the in-phase input end of the operational amplifier and described The 4th resistance is also in series between the output end of sequential translation circuit.
  8. 8. a kind of laser ranging circuit, it is characterised in that including the timing any one of processor and claim 1 to 7 Circuit；
    The processor connects the output end of the analog to digital conversion circuit in the timing circuit；Wherein, the processor receives institute The data signal of analog to digital conversion circuit output is stated, and is calculated according to the information of the time interval carried in the data signal Target range.
  9. 9. a kind of laser range finder, it is characterised in that including controller, generating laser, photodetector and claim 8 Described in laser ranging circuit；
    The control terminal of the controller connects the first input end of the generating laser and the sequential translation circuit respectively；
    The photodetector connects the second input of the sequential translation circuit；
    Wherein, when the control terminal exports the emissioning controling signal of first pulse, the described in the laser transmitter projects One pulse；When the photodetector detects the echo impulse of the first pulse, the echo reception letter of first pulse is exported Number.
CN201720602886.6U 2017-05-26 2017-05-26 Timing circuit, laser ranging circuit and laser range finder Active CN206863222U (en)

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Application Number Priority Date Filing Date Title
CN201720602886.6U CN206863222U (en) 2017-05-26 2017-05-26 Timing circuit, laser ranging circuit and laser range finder

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
CN201720602886.6U CN206863222U (en) 2017-05-26 2017-05-26 Timing circuit, laser ranging circuit and laser range finder

Publications (1)

Publication Number Publication Date
CN206863222U true CN206863222U (en) 2018-01-09

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Country Link
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Address after: 214135 5th floor, building 200-5, Linghu Avenue, Xinwu District, Wuxi City, Jiangsu Province

Patentee after: EPCO Microelectronics (Jiangsu) Co., Ltd

Address before: Room 307, building 1, 2966 Jinke Road, Pudong New Area pilot Free Trade Zone, Shanghai 201210

Patentee before: EPTICORE MICROELECTRONICS (SHANGHAI) Co.,Ltd.