CN115189691A

CN115189691A - Counter with a counter body

Info

Publication number: CN115189691A
Application number: CN202210897992.7A
Authority: CN
Inventors: 严波; 方超敏; 王悦
Original assignee: Puyuan Jingdian Technology Co ltd
Current assignee: Puyuan Jingdian Technology Co ltd
Priority date: 2022-07-28
Filing date: 2022-07-28
Publication date: 2022-10-14
Also published as: WO2024021360A1

Abstract

The embodiment of the application provides a counter, including: the counting module comprises a plurality of cascaded sub-counters and a delay unit connected between at least two adjacent sub-counters in the plurality of sub-counters; the sub-counters are used for counting the number of the clock pulses so as to output a counting output signal and a carry output signal; the delay unit is used for receiving a carry output signal of a previous stage of sub-counter in the at least two sub-counters and delaying the received carry output signal and outputting the delayed carry output signal to a next stage of sub-counter; and the data alignment module is used for receiving the counting output signals of the sub-counters and performing data alignment on the received counting output signals belonging to the same counting period according to the corresponding relation of the delay time caused by the delay unit so as to output a counting result. Therefore, on the premise of ensuring the counting accuracy, the running speed of the counter is increased, and the counter with higher digits is favorably realized.

Description

Counter with a memory

Technical Field

The present invention relates to the field of circuit and system technologies, and in particular, to a counter.

Background

The counter is a common sequential logic circuit, is an important component of a digital circuit, and has the most basic function of counting by counting the number of clock pulses.

The higher the number of bits (number of bits/number of bits) of the counter, the more difficult it is to realize high speed. The counter is mainly related to the composition structure of the counter, the counter utilizes an AND gate to generate carry, and the input of the AND gate is more than one stage as the number of bits of the counter increases. When the input of the AND gate exceeds a certain degree, the AND operation has to be carried out in a hierarchical level, namely, the first data are firstly subjected to the AND operation, and the operation result enters a new AND gate to carry out the next-level operation. However, this causes the propagation delay of the carry signal to rise, and the counter speed is limited when the number of stages of the and gate is increased until the propagation delay of the carry signal is comparable to the clock period. Therefore, the higher the structural digit of the traditional counter is, the slower the speed is; this becomes the biggest limitation of high-speed counters. In addition, propagation delay is also prone to cause a problem of counting errors.

How to continuously increase the running speed of the counter and realize the counter with high digit number on the premise of ensuring the counting accuracy is an important technical problem which is always solved in the field.

Disclosure of Invention

In view of the above, the embodiments of the present application provide a counter to solve at least one problem in the background art.

An embodiment of the present application provides a counter, including:

the counting module comprises a plurality of cascaded sub-counters and a delay unit connected between at least two adjacent sub-counters in the plurality of sub-counters; the sub-counter is used for counting the number of clock pulses so as to output a counting output signal and a carry output signal; the delay unit is used for receiving a carry output signal of a previous stage of sub-counter in the at least two sub-counters and delaying the received carry output signal and outputting the delayed carry output signal to a next stage of sub-counter;

and the data alignment module is used for receiving the counting output signals of the sub-counters and performing data alignment on the received counting output signals belonging to the same counting period according to the corresponding relation of the delay time caused by the delay unit so as to output a counting result.

In an alternative embodiment, a delay unit is disposed between every two adjacent sub-counters in the plurality of sub-counters.

In an optional embodiment, the delay unit includes a flip-flop, and the flip-flop receives the carry output signal of the previous stage sub-counter and outputs the delayed carry output signal to the next stage sub-counter by using a clock pulse as a control signal.

In an alternative embodiment, at least one of the sub-counters is an n-bit (n-bit) counter, where n is greater than 1; carry signals are generated among all bits in the n-bit counter through an AND gate;

the input end of the AND gate of at least one bit in the n-bit counter is connected with the input end of the AND gate of the previous bit;

the n-bit counter comprises an AND gate with no more than one bit and adopts the following connection mode: the input terminal of the AND gate of this bit is connected to the output terminal of the AND gate of the previous bit.

In an optional embodiment, the data alignment module includes a trigger, and the data alignment module performs data alignment based on the trigger.

In an alternative embodiment, the sub-counter is an n-bit (n-bit) counter, where n is greater than or equal to 1; each bit of the n-bit counter comprises a first flip-flop; the first trigger comprises a counting input end and a counting output end; the counting output signal comprises a signal of the counting input end and/or a signal of the counting output end;

the delay unit comprises at least one second flip-flop; the second trigger takes clock pulse as a control signal, receives the carry output signal of the previous-stage sub-counter and outputs the delayed carry output signal to the next-stage sub-counter;

the data alignment module comprises at least one third trigger, and the data alignment module performs data alignment based on the third trigger;

the data alignment module comprises a plurality of lines corresponding to the plurality of sub-counters, and each line in the plurality of lines receives the counting output signal of the corresponding sub-counter;

for a line, of the plurality of lines, where the received count output signal is a signal at a count output end, the number of the third flip-flops cascaded on the line is equal to the number of the second flip-flops between the sub-counter corresponding to the line and the last sub-counter in the counting module;

for a line, among the plurality of lines, for which the received count output signal is a signal at a count input terminal, the number of the third flip-flops cascaded on the line is equal to the number of second flip-flops, between the sub-counter corresponding to the line and the last sub-counter, in the counting module plus 1.

In an optional embodiment, the line corresponding to the last stage sub-counter in the counting module among the plurality of lines receives a counting output signal as a signal at a counting input terminal.

In an alternative embodiment, the count output signal comprises a signal at the count input and a signal at the count output; and the counting output signals received by other lines except the line corresponding to the last stage of sub-counter in the plurality of lines are signals of a counting output end.

In an alternative embodiment, the system further comprises a clock module,

the clock module is used for generating a first clock signal and a second clock signal, the counting module works based on the first clock signal, and the data alignment module works based on the second clock signal.

In an alternative embodiment, the clock module comprises a clock signal input end, and a first clock generation line and a second clock generation line which are connected with the clock signal input end; the first clock generation circuit is used for generating the first clock signal based on the clock signal input by the clock signal input end; the second clock generating circuit is used for generating the second clock signal based on the clock signal input by the clock signal input end; and a delay unit is connected to the first clock generation line and/or the second clock generation line.

In an optional embodiment, at least two delay units are connected to the first clock generation line and the second clock generation line, respectively, and a fan-out capability of a delay unit located at a subsequent stage is greater than a fan-out capability of a delay unit located at a previous stage.

In the counter provided by the embodiment of the application, the delay unit is arranged between at least two adjacent sub-counters in the plurality of sub-counters, and the delay unit is used for receiving the carry output signal of a previous-stage sub-counter in the at least two sub-counters, delaying the received carry output signal and outputting the delayed carry output signal to a next-stage sub-counter; further receiving the counting output signals of the plurality of sub-counters through a data alignment module, performing data alignment on the received plurality of counting output signals belonging to the same counting period according to the corresponding relation of the delay time caused by the delay unit, and finally outputting a counting result; therefore, the problem that propagation delay of carry signals in a traditional counter structure limits counting accuracy and running speed is solved, the running speed of the counter is increased on the premise that the counting accuracy is guaranteed, and the counter with higher digits is realized.

Additional aspects and advantages of the present application will be set forth in part in the description which follows and, in part, will be obvious from the description, or may be learned by practice of the present application.

Drawings

The accompanying drawings, which are included to provide a further understanding of the application and are incorporated in and constitute a part of this application, illustrate embodiment(s) of the application and together with the description serve to explain the application and not to limit the application. In the drawings:

fig. 1 is a schematic structural diagram of a counter according to an embodiment of the present application;

FIG. 2 is a schematic structural diagram of a counting module according to an embodiment of the present application;

FIG. 3 is a schematic diagram of a sub-count structure according to an embodiment of the present application;

FIG. 4 is a schematic structural diagram of a data alignment module according to an embodiment of the present application;

FIG. 5 is a schematic structural diagram of a clock module according to an embodiment of the present application;

fig. 6 is a schematic structural diagram of a counter according to a specific example of the present application.

Detailed Description

In order to make the technical solutions and advantages of the present invention more comprehensible, the following embodiments are described in detail and completely in the embodiments of the present application by way of listing specific embodiments, and it is obvious that the described embodiments are only a part of the embodiments of the present application, but not all embodiments. All other embodiments, which can be derived by a person skilled in the art from the embodiments given herein without making any creative effort, shall fall within the protection scope of the present application.

Unless defined otherwise, all technical and scientific terms used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this application belongs. The terminology used in the description of the present application is for the purpose of describing particular embodiments only and is not intended to be limiting of the application.

It will be understood that, as used herein, the terms "first," "second," and the like may be used herein to describe various elements, but these elements are not limited by these terms. These terms are only used to distinguish one element from another. For example, a first resistance may be referred to as a second resistance, and similarly, a second resistance may be referred to as a first resistance, without departing from the scope of the present application. The first resistance and the second resistance are both resistances, but they are not the same resistance. When describing "first", it does not mean that "second" is necessarily present; and the discussion of "second" does not necessarily indicate that a first element, component, region, layer or section is present in the application. As used herein, the singular forms "a", "an" and "the" may be intended to include the plural forms as well, unless the context clearly indicates otherwise. The meaning of "a plurality" is two or more unless specifically limited otherwise. It will be further understood that the term "comprises" when used in this specification is taken to specify the presence of stated features but does not preclude the presence or addition of one or more other features. As used herein, the term "and/or" includes any and all combinations of the associated listed items.

First, please refer to fig. 1. The counter provided by the embodiment of the application comprises a counting module and a data alignment module.

Specifically, the counting module comprises a plurality of cascaded sub-counters and a delay unit connected between at least two adjacent sub-counters in the plurality of sub-counters.

In fig. 1, the counting module includes a first sub-counter, a second sub-counter, a sub-counter 8230a sub-counter N, and a first delay unit and a second delay unit. It should be understood that the number of sub-counters in the embodiments of the present application may be sufficient to achieve a larger number of counts, for example, the number of sub-counters may be tens, hundreds, or more; this is not particularly limited by the present application. In addition, the improved technical scheme provided by the application is at least suitable for the counters of which the number of the sub-counters is not less than two (namely N can be more than two).

The effect of capacity expansion can be achieved through the cascade connection of the sub-counters. As shown in fig. 3, each sub-counter includes a carry input terminal CI and a carry output terminal CO; the cascade of the sub-counters means that the carry output terminal CO of the sub-counter at the previous stage is coupled to the carry input terminal CI of the sub-counter at the next stage. Accordingly, the sub-counter at a previous stage outputs a carry output signal through the carry output terminal CO, and the carry output signal is transmitted to the carry input terminal CI of the sub-counter at a subsequent stage as an input of the sub-counter at the subsequent stage to participate in the counting operation of the sub-counter at the subsequent stage. It is understood that "coupled" in the context of this application means that the coupled end and the coupled end have mutual electrical signal or data transmission, and can be understood as "electrically connected", "communicatively connected", and the like.

In addition, each sub-counter further comprises a clock signal input terminal and a count output terminal. The CLOCK signal input end may refer to one end of each sub-counter connected to CLOCK1 in fig. 1 or one end of each sub-counter connected to CLOCK in fig. 3. Each sub-counter receives a clock signal through a clock signal input end, the clock signal is specifically in a clock pulse form, and the sub-counters are used for counting the number of the clock pulses so as to output a counting output signal and a carry output signal.

Taking a 4-bit counter as an example, the output count output signal changes once every time a clock pulse increases by one, specifically, the count changes from 0000, 0001, 0010, 0011 \8230 \ 8230, and changes to 1111, a total of 16 results (the number of clock pulses changes from 0 to 15) can be output, and the signals output outwards by the 16 results in a mode that a high level represents 1 and a low level represents 0 are the count output signal. After the count result reaches 1111, the clock pulse is increased by one again, obviously, the maximum value which can be represented by the current 4 bits is exceeded, and at this time, carry is needed, namely carry output 1 and the count result becomes 0000; it will be appreciated that in binary, 10000 represents 16, i.e. the number of clock pulses varies from 0 to 16. The carry output 1 is embodied as a change in the level of the carry output signal.

As can be seen, the count output signal represents a signal corresponding to a specific result of the counter counting the number of clock pulses; the carry output signal represents a signal output when the clock pulse is increased again and the counting result needs to carry after the counter reaches the maximum counting value. The carry input end CI is used for outputting a carry output signal; the counting output end is used for outputting a counting output signal.

The counting output end can refer to D1, D2 \ 8230; \8230, DN in FIG. 1, or DA <0> to DA <3> and/or DS <0> to DS <3> in FIG. 3; hereinafter, DA <0> to DA <3> will be taken as DA <3:0> indicates that DS <0> through DS <3> will be expressed as DS <3:0> represents; obviously, DA <3 in fig. 1: 0> and/or DS <3:0> corresponds to D1 in FIG. 1, although D2 to DN in FIG. 1 can also be the same or similar to D1.

The delay unit is used for receiving the carry output signal of the previous stage sub-counter in the at least two sub-counters, delaying the received carry output signal and outputting the delayed carry output signal to the next stage sub-counter. Referring to fig. 1 specifically, the first delay unit receives a carry output signal of the first sub-counter, delays the received carry output signal, and outputs the delayed carry output signal to the second sub-counter. Fig. 1 shows a case where a delay unit is provided between every two adjacent stages of sub-counters among a plurality of sub-counters; in concrete application, the setting mode can be adopted so that the components of the whole counting module are built periodically, and therefore the counting module is simple in structure and high in operation stability, and influences caused by propagation delay of carry signals are avoided to a great extent. Of course, the number and the positions of the delay units may be specifically selected according to actual requirements. In this embodiment, a delay unit is disposed between at least one pair of adjacent sub-counters, so as to reduce, at least to some extent, the influence of the propagation delay of the carry signal generated by the and gate operation on the number and accuracy of the counters.

It can be understood that the delay unit can make the carry output signal of the previous stage sub-counter be transmitted to the next stage sub-counter after being delayed by the exact time length or the exact period, so that the next stage sub-counter can participate in the counting operation in the exact time length or the exact period; in other words, the delay of the carry output signal by the delay unit means that the carry output signal is transmitted to the next-stage sub-counter at a later time than the carry output signal is directly transmitted to the next-stage sub-counter, however, the exact duration or the exact period can be controlled by the delay unit, so that the time when the carry output signal is transmitted to the next-stage sub-counter is almost not delayed compared with the clock signal, and the time delay caused by the and gate operation is avoided.

And the data alignment module is used for receiving the counting output signals of the sub counters and performing data alignment on the received counting output signals belonging to the same counting period according to the corresponding relation of the delay time caused by the delay unit so as to output a counting result.

For example, at a first time, the first sub-counter transmits a count output signal (such as DS <3>; due to the existence of the first delay unit, the second sub-counter needs to transmit its count output signal (such as DS <7 >; similarly, if the carry output signal of the second sub-counter passes through the second delay unit and then is output to a third sub-counter (not shown in fig. 1), the third sub-counter needs to transmit its count output signal (for example, DS <11 >. The data alignment module receives the counting output signals DS <3 of each sub-counter at different time: 0>, DS <7:4> and DS <11:8>, however, DS <3:0>, DS <7:4> and DS <11:8> belong in fact to the same counting cycle; the data alignment module is configured to temporally align DS <3:0>, DS <7:4> and DS <11:8> alignment, thereby outputting the counting result. Wherein, the corresponding relation is as follows: DS <3:0> to DS <11:8> earlier than the delay time caused by the first delay cell and the second delay cell together, DS <7:4> ratio DS <11:8> earlier than the delay time due to the second delay cell.

Therefore, in the embodiment of the application, the delay unit is arranged between at least two adjacent sub-counters in the plurality of sub-counters, and the delay unit is used for receiving the carry output signal of the previous-stage sub-counter in the at least two sub-counters, delaying the received carry output signal and outputting the delayed carry output signal to the next-stage sub-counter; further receiving the counting output signals of the plurality of sub-counters through a data alignment module, performing data alignment on the received plurality of counting output signals belonging to the same counting period according to the corresponding relation of the delay time caused by the delay unit, and finally outputting a counting result; therefore, the problem that propagation delay of carry signals in the traditional counter structure limits the counting accuracy and the running speed is solved, the running speed of the counter is increased on the premise of ensuring the counting accuracy, and the counter with higher digits is favorably realized.

In one embodiment, the delay unit includes a flip-flop, which receives the carry output signal of the previous sub-counter stage and outputs the delayed carry output signal to the next sub-counter stage by using a clock pulse as a control signal.

It can be understood that the flip-flop can provide a delay of an integer period, and as a commonly used circuit element in a counter, a device structure can be simplified, and a stable and reliable delay effect can be achieved. However, the specific selection of the delay unit in the present application is not limited to this, and other components capable of delaying the carry output signal of the previous stage sub-counter may also be applied to this, for example, a programmable delay module.

Fig. 2 shows a schematic structural diagram of a specific counting module. The counting module comprises a plurality of cascaded sub-counters and a trigger connected between every two adjacent stages of the sub-counters. The flip-flop includes a clock signal input terminal, a D terminal receiving a data signal, and a Q terminal outputting a delayed data signal. The CLOCK signal input end of the flip-flop may refer to an end connected to CLOCK1 in the figure, the flip-flop receives a CLOCK signal through the CLOCK signal input end, the CLOCK signal is specifically in the form of CLOCK pulses, and the flip-flop transitions from one stable state to another stable state with the CLOCK pulses as a control signal. The CLOCK signal input terminal of the flip-flop and the CLOCK signal input terminal of each sub-counter are connected to the same CLOCK signal (e.g., CLOCK1 in the figure), and thus operate under the control of the same CLOCK signal. The D end of the trigger is connected with the carry output end of the previous-stage sub-counter (the carry output end refers to CO0 and CO1 in the figure), so that the carry output signal of the previous-stage sub-counter is received; the Q end of the trigger is connected with the carry input end of the next-stage sub-counter, so that the delayed carry output signal is output to the next-stage sub-counter. In a specific application, the trigger can be directly connected with the previous-stage sub-counter and the next-stage sub-counter, namely, other components except wires are not included between the trigger and the previous-stage sub-counter and the next-stage sub-counter.

For the sake of distinction, in the following description, a flip-flop as a delay unit may also be referred to as a "second flip-flop". In various embodiments, the second flip-flop may be a D flip-flop. Of course, the present application is not limited thereto, and other delay circuits may be utilized in other embodiments.

Next, please refer to fig. 3. It should be understood that, in the description of the present application, since it is considered that the counting module in the timer is composed of a plurality of counters in cascade, for convenience of distinction, the cascaded counters are referred to as "sub-counters"; however, this does not mean that the sub-counters differ from the counters commonly understood by those skilled in the art. As an example, fig. 3 shows a schematic structure of a sub-counter. As shown, the sub-counter includes a flip-flop, an exclusive or gate, and an and gate; for the sake of distinction, in the following description, the flip-flop in the sub-counter may also be referred to as "first flip-flop". The sub-counter is a 4-bit counter and comprises 4 groups of triggers, an exclusive-OR gate and an AND gate which are periodically arranged, and each group of the triggers, the exclusive-OR gate and the AND gate corresponds to one bit in the 4-bit counter. Wherein CI is a carry input end, and CO is a carry output end; DS in each bit is the count output of the bit, and DA is the count input of the bit. Since the signal is output after a flip-flop delay compared to the DS, the signal at the DS is usually one clock cycle later than the signal at the DA, and the counting result at the DA may also be referred to as the counter output minus 1.

The carry input end CI of the sub-counter which is taken as the first stage in the counting module can not be accessed with signals, such as being idle; the carry output end CO of the sub-counter serving as the last stage in the counting module is not coupled with other sub-counters, such as being vacant; in addition, the sub-counter cascaded in the middle of the counting module has a carry input terminal CI for receiving the output signal of the carry output terminal CO of the previous sub-counter, and a carry output terminal CO for transmitting the output signal to the carry input terminal CI of the next sub-counter.

The xor gate has two inputs, one of which is connected to the Q terminal of the flip-flops in the same group (or bit), and the other of which is connected to the output of the and gate in the previous group (or bit). The two input ends corresponding to the exclusive-or gate receive the same input signal, and if the two input ends receive a high level 1 or both receive a low level 0, the output end of the exclusive-or gate outputs the low level 0; the two input terminals corresponding to the exclusive-or gate receive different input signals, and if the two input terminals receive a high level 1 and a low level 0 respectively, the output terminal of the exclusive-or gate outputs the high level 1. The output end of the exclusive-or gate is connected with the D end of the first trigger.

The AND gate includes a plurality of inputs and an output. And carry signals are generated between each bit in the sub-counters through AND gates. A plurality of input ends corresponding to the AND gates receive the high level 1, and the output end of the AND gate outputs the high level 1; otherwise, the output of the and gate outputs a low level 0. As mentioned above, the output of the and gate is connected to the input of the xor gate in the next group (or bit). One input end of the AND gate is connected with the Q end of the trigger in the same group; the other input ends of the AND gate may have different connection modes according to the different bit numbers of the AND gate.

The input end of the AND gate in the first group (or first bit) of the sub-counter is connected with the carry input end CI of the sub-counter. The input ends of the AND gates in the second group (or the second bit) and the third group (or the third bit) of the sub-counters are connected with the input end of the AND gate of the previous bit. And the input end of the AND gate in the fourth group (or fourth group) of the sub-counters is connected with the output end of the AND gate of the previous bit. It will be appreciated that whether connected to all inputs of the previous and gate or to the output of the previous and gate, the result is the same based on the principle of operation of the and gate. However, for the case of connecting to all the input terminals of the previous and gate, the signal does not need to be and-operated by the previous and gate, but is only transmitted through the wire, and there is almost no propagation delay; on the contrary, if the output terminal of the previous and gate is connected, the and operation needs to be performed through the previous and gate, which will cause propagation delay to increase due to the and gate.

Although fig. 3 illustrates a 4-bit counter, it can be understood that as the number of counter bits increases, the input of the and gate increases. However, the number of inputs to the and gate is limited and cannot be increased infinitely, and when the input to the and gate exceeds a certain level, the and operation has to be performed in a hierarchical level. That is, as in the and gate in the fourth bit of fig. 3, the previous bit and gate performs and operation on the data of the previous bits, and the operation result is output to the fourth and gate for the next stage of operation.

As an optional implementation manner of the present application, at least one of the sub-counters is an n-bit (n-bit) counter, where n is greater than 1; carry signals are generated among all bits in the n-bit counter through an AND gate; the input end of the AND gate of at least one bit in the n-bit counter is connected with the input end of the AND gate of the previous bit; the n-bit counter comprises an AND gate with no more than one bit and adopts the following connection mode: the input terminal of the AND gate of this bit is connected to the output terminal of the AND gate of the previous bit. It can be understood that, when the more than one and gate needs to adopt a connection mode in which the input end is connected to the output end of the previous and gate, that is, the number of the input ends of the one and gate cannot bear all the input signals of the previous and gate, the and gate may not be adopted, in other words, the sub-counter including more than two and gates adopting the connection mode is not adopted, and the technical solution provided by the embodiment of the present application is adopted to solve the problem.

Optionally, n is less than or equal to 6.

In practical applications, the sub-counter may be a 4-bit counter or a 3-bit counter. The sub-counter may include and only include one and gate connected in the following connection manner: the input end of the AND gate of the bit is connected with the output end of the AND gate of the previous bit; or, the number of the connected and gates can not exceed the following connection modes: the input terminal of the AND gate of this bit is connected to the output terminal of the AND gate of the previous bit.

Fig. 4 shows a schematic structural diagram of a data alignment module. As shown in the figure, the data alignment module includes a counting output signal receiving end, a clock signal input end, and a counting result output end.

Wherein, the counting output signal receiving end refers to DA1-N and DS1-N in the figure; the structure shown in the figure does not indicate that there are two count output signal receiving ends of the data alignment module, and in fact, there may be a plurality of count output signal receiving ends; the counter output signal receiving side may receive the signals of DA1 to N and DS1 to N, may receive only the signals of DA1 to N or only the signals of DS1 to N, or may receive partial signals of DA1 to N and partial signals of DS1 to N. DA1-N and DS1-N can be understood in conjunction with FIG. 2 and FIG. 3; taking DA1 as an example, it represents the count input of the sub-counter (n-bit counter) located at the first stage in fig. 2, corresponding to DA <3 in fig. 3:0>; similarly, DS1 represents the count output of the sub-counter at the first stage in fig. 2, corresponding to DS <3 in fig. 3:0>. And DA1-N represents from DA1 to DAN; similarly, DS1-N refers to from DS1 to DSN.

Please refer to CLOCK2 in fig. 4 for the CLOCK signal input terminal of the data alignment module. CLOCK2 and CLOCK1 may be CLOCK synchronized or may have a phase difference.

Referring to DOUT in fig. 4, a count result output end of the data alignment module is configured to output a count result.

Referring to fig. 6, in an alternative embodiment of the present application, the data alignment module includes a trigger, and the data alignment module performs data alignment based on the trigger.

In a more specific alternative embodiment, the sub-counter is an n-bit (n-bit) counter, where n is greater than or equal to 1; each bit of the n-bit counter comprises a first trigger; the first trigger comprises a counting input end and a counting output end; the counting output signal comprises a signal at a counting input end and/or a signal at a counting output end; the delay unit comprises at least one second flip-flop; the second trigger takes the clock pulse as a control signal, receives the carry output signal of the previous-stage sub-counter and outputs the delayed carry output signal to the next-stage sub-counter; the data alignment module comprises at least one third trigger, and the data alignment module performs data alignment based on the third trigger; the data alignment module comprises a plurality of lines corresponding to the plurality of sub-counters, and each line in the plurality of lines receives the counting output signal of the corresponding sub-counter; for a line, the received counting output signal of the plurality of lines is the signal of the counting output end, and the number of the third flip-flops cascaded on the line is equal to the number of the second flip-flops between the sub-counter corresponding to the line and the last sub-counter in the counting module; for the line, among the plurality of lines, for which the received count output signal is the signal at the count input terminal, the number of the third flip-flops cascaded on the line is equal to the number of the second flip-flops in the count module from the sub-counter corresponding to the line to the last sub-counter plus 1.

It will be appreciated that fig. 6 illustrates a cascade of 4 sub-counters, and that each sub-counter employs a 4-bit counter, thereby implementing a 16-bit counter. Wherein, 4bit counters are divided into 4-level pipeline structures; thus, the counting module may also be referred to as a "pipeline counter core". Of course, the embodiment of the present application is not limited thereto, and the pipeline counter core may include a plurality of n-bit counters; the number of bits of each sub-counter may be the same or different.

The carry output signals of the first-stage sub-counter are orderly tapped by a trigger and enter the second-stage flowing water to participate in counting operation. The carry output signal of the second stage sub-counter participates in the third stage operation after passing through a trigger, and so on. Finally, each stage of the sub-counter generates 4 bits of DA and DS. It can be seen that when the carry output signal of the first stage sub-counter is generated, it takes a clock cycle to participate in the second stage operation. After the carry output signal is processed by the second stage of pipeline, the carry output signal enters a third stage to participate in operation through a trigger. After the third stage, the final fourth stage operation can be performed only through the first stage flip-flop, and finally output. Therefore, the counting result (counting output signal) of the first stage sub-counter finally passes through three additional flip-flops to complete the operation. This means that the count of the first stage sub-counter is transmitted to the data alignment module 3 cycles earlier than the count result of the last stage sub-counter. Therefore, when data alignment is finally performed, the DS <3 >. Similarly, the DS <7 > of the second-stage sub-counter is delayed by two clock cycles; the third stage sub-counter is delayed by one clock cycle. Thus, in the data alignment module, the line receiving the DS <3> of the first-stage sub-counter is connected with three third flip-flops at the upper stage; receiving two third triggers of a line superior cascade of the DS <7 > of the second-stage sub-counter; the line receiving DS <11 > of the third stage sub-counter is cascaded with a third flip-flop.

As an alternative embodiment, the fourth-stage sub-counter may output the DS <15 >; accordingly, no third flip-flop is cascaded on the line receiving DS <15 >. However, as another alternative embodiment, the last-stage (specifically, the fourth-stage in this embodiment) sub-counter is preferably also connected to a third flip-flop via a flip-flop, that is, a line receiving the count output signal of the last-stage sub-counter is connected to a third flip-flop. Therefore, the final output counting result can be ensured to be triggered by a synchronous CLOCK (the requirement of a synchronous sequence counter), and the problem that the DS of the last stage counter is driven by a CLOCK1 and the output counting result is driven by a CLOCK2 to generate asynchronization is avoided. For the embodiment in which a third flip-flop is connected upstream on the line receiving the count output signal of the last stage of the sub-counter, a DA <15 >.

Optionally, in a line corresponding to the last stage sub-counter in the counting module in the plurality of lines, the received counting output signal is a signal at the counting input end. In this way, for a line, among the plurality of lines, for which the received count output signal is a signal at the count input terminal, the number of the third flip-flops cascaded on the line is equal to the number of the second flip-flops in the count module from the sub-counter corresponding to the line to the last sub-counter plus 1; specifically, for the last stage sub-counter, there is no second flip-flop behind it, that is, the number is 0, and the number of the third flip-flops associated with its corresponding line upper stage is equal to 0+1, that is, one third flip-flop is connected.

Optionally, the count output signal includes a signal at a count input terminal and a signal at a count output terminal; and the other lines except the line corresponding to the last stage of sub-counter in the plurality of lines receive the counting output signal which is the signal of the counting output end. Therefore, on one hand, the counting result finally output is triggered by the synchronous clock, on the other hand, the setting number of the triggers is saved as much as possible, and the device cost is reduced.

It should be understood that, the embodiments of the present application are not limited thereto, and the received count output signal of a line corresponding to a sub-counter of another stage except the last stage in the counting module among the plurality of lines may also be a signal at the count input terminal, and should also be considered to be feasible.

Next, referring to fig. 1, fig. 5 and fig. 6, the counter according to the embodiment of the present disclosure may further include a clock module, where the clock module is configured to generate a first clock signal and a second clock signal, the counting module operates based on the first clock signal, and the data alignment module operates based on the second clock signal.

As shown in fig. 5, the CLOCK module includes a CLOCK signal input terminal (see CLOCK in the figure), a first CLOCK signal output terminal (see CLOCK1 in the figure), and a second CLOCK signal output terminal (see CLOCK2 in the figure). The clock module mainly generates a first clock signal and a second clock signal for the counting module and the data alignment module according to a clock signal input by the clock signal input end.

The phase difference between the first clock signal and the second clock signal can be set according to actual conditions. In particular, the phase relationship of the two clock signals may be tailored according to the delay of the device implementing the counter, thereby ensuring a maximum timing margin. As an alternative embodiment, the first clock signal and the second clock signal may not have a phase difference, and the two clock signals may be synchronized. As another alternative, there is a phase difference between the first clock signal and the second clock signal. It will be appreciated that CLOCK2 may be made faster or slower than CLOCK1 to achieve higher speeds, at times, in order to strive for adequate timing margin.

Considering that as the number of bits of the counter increases, the driving requirement of the synchronous clock also increases gradually, which may cause a problem of coordination of the synchronous clock, if flip-flops are different, a counting error condition may occur. Therefore, the clock module needs to consider increasing the driving capability of the clock in addition to adjusting the phase relationship between the first clock signal and the second clock signal.

Referring to fig. 6, as an alternative embodiment, the clock module includes a clock signal input terminal, and a first clock generation circuit and a second clock generation circuit connected to the clock signal input terminal; the first clock generation circuit is used for generating a first clock signal based on a clock signal input by the clock signal input end; the second clock generating circuit is used for generating a second clock signal based on the clock signal input by the clock signal input end; the first clock generation line and/or the second clock generation line are/is connected with a delay unit.

Specifically, as shown in fig. 6, two delay units (delay unit 1 and delay unit 2) are connected to the first clock generation line and two delay units (delay unit 3 and delay unit 4) are connected to the second clock generation line, and four delay units are used in total.

In an alternative embodiment, at least two delay units may be connected to the first clock generation line and the second clock generation line, respectively; thereby further increasing the flexibility of phase adjustment compared to using one delay unit. Under the condition that more than two delay units are connected on the line, the fan-out capability of the delay unit positioned at the next stage is greater than that of the delay unit positioned at the previous stage; thereby enlarge fan-out ability step by step, realize stronger driving force.

The embodiments of the present application can be applied to a high-speed pattern generator. The embodiment adopts a pipeline structure, the carry bit of each stage of sub-counter is output and then is beaten by one beat through a trigger to form the pipeline structure which is used for offsetting the delay of a carry chain; each stage of sub-counter can output respective DA and DS, the data alignment module mainly receives the values of the DS and the DA output by the assembly line counter, and data belonging to the same counting period are aligned through a determined time sequence relation to form final output. Therefore, the problem that the maximum running speed of the counter is restricted due to too long time delay generated by carry due to too long carry chain of the traditional counter structure is solved. By adopting the clock tree redistribution mode, the clock phase relation can be freely adjusted according to the characteristics of the process devices, and the maximization of the counter speed under the same group of processes is realized.

According to the embodiment of the application, the running speed of the counter can be greatly increased on the basis of not changing a used digital standard device, and great significance is achieved in function and cost.

All possible combinations of the technical features of the above embodiments may not be described for the sake of brevity, but should be considered as within the scope of the present disclosure as long as there is no contradiction between the combinations of the technical features.

The above-mentioned embodiments only express several embodiments of the present invention, and the description thereof is more specific and detailed, but not construed as limiting the scope of the invention. It should be noted that various changes and modifications can be made by those skilled in the art without departing from the spirit of the invention, and these changes and modifications are all within the scope of the invention. Therefore, the protection scope of the present patent shall be subject to the appended claims.

Claims

1. A counter, comprising:

2. The counter of claim 1, wherein a delay unit is disposed between each two adjacent sub-counters of the plurality of sub-counters.

3. The counter of claim 1 or 2, wherein the delay unit comprises a flip-flop, which receives the carry output signal of the previous stage sub-counter and outputs the delayed carry output signal to the next stage sub-counter with a clock pulse as a control signal.

4. The counter of claim 1, wherein at least one of said sub-counters is an n-bit (n-bit) counter, wherein n is greater than 1; carry signals are generated among all bits in the n-bit counter through an AND gate;

the n-bit counter comprises an AND gate with no more than one bit and adopts the following connection mode: the input end of the AND gate of the bit is connected with the output end of the AND gate of the previous bit.

5. The counter of claim 1, wherein the data alignment module comprises a trigger, and wherein the data alignment module performs data alignment based on the trigger.

6. The counter of claim 1,

the sub-counter is an n-bit (n bit) counter, wherein n is greater than or equal to 1; each bit of the n-bit counter comprises a first flip-flop; the first trigger comprises a counting input end and a counting output end; the counting output signal comprises a signal of the counting input end and/or a signal of the counting output end;

7. The counter of claim 6, wherein the line of the plurality of lines corresponding to the last stage of sub-counters in the counting module receives the counting output signal as the signal of the counting input terminal.

8. The counter of claim 7, wherein the count output signal comprises a signal at the count input and a signal at the count output; and the counting output signals received by other lines except the line corresponding to the last stage of sub-counter in the plurality of lines are signals of a counting output end.

9. The counter of claim 1, further comprising a clock module,

10. The counter of claim 9, wherein the clock module comprises a clock signal input and first and second clock generation lines connected to the clock signal input; the first clock generation circuit is used for generating the first clock signal based on the clock signal input by the clock signal input end; the second clock generating circuit is used for generating the second clock signal based on the clock signal input by the clock signal input end; and a delay unit is connected to the first clock generation line and/or the second clock generation line.

11. The counter of claim 10, wherein at least two delay units are connected to the first clock generation line and the second clock generation line, respectively, and a fan-out capability of a delay unit at a subsequent stage is larger than a fan-out capability of a delay unit at a previous stage.