CN114003544A

CN114003544A - Control chip, workload proving system and transmission method

Info

Publication number: CN114003544A
Application number: CN202111636746.8A
Authority: CN
Inventors: 田佩佳; 蔡凯
Original assignee: Sunlune Technology Beijing Co Ltd
Current assignee: Sunlune Technology Beijing Co Ltd
Priority date: 2021-12-30
Filing date: 2021-12-30
Publication date: 2022-02-01

Abstract

The embodiment of the application discloses a control chip, a workload proving system and a transmission method; the control chip includes: the system comprises a data register, a processing module and a Serial Peripheral Interface (SPI) driving module; the data register is used for storing M-bit task data to be sent and outputting the stored task data under the control of the processing module; wherein M is the bit width of the data register; the processing module is used for controlling the SPI driving module, and sending the task data which is continuously output by the data register for N times to the workload proving chip through an SPI data frame; wherein N is a positive integer greater than 1. The embodiment of the application can improve the efficiency of the workload proving system.

Description

Control chip, workload proving system and transmission method

Technical Field

The present disclosure relates to the field of block chaining, and more particularly, to a control chip, a workload certification system and a transmission method.

Background

The block chain is used as a shared database, and the data or information stored in the block chain has the characteristics of unforgeability, whole-course trace, traceability, public transparency, collective maintenance and the like. Based on the characteristics, the block chain technology lays a solid 'trust' foundation, creates a reliable 'cooperation' mechanism and has wide application prospect.

POW (Proof Of Work) is an economic countermeasure for dealing with misuse Of services and resources or blocking service attacks, and is widely used in the field Of block chains. The characteristic features of the method are that in the process of establishing a new block by a block chain, in order to prevent information from being tampered by others, an answer must be provided or a specific difficult task must be confirmed as a workload proof; this proof is difficult to provide and requires a large number of calculations to calculate.

Disclosure of Invention

The following is a summary of the subject matter described in detail in this application. This summary is not intended to limit the scope of the present application.

The application provides a control chip, a workload proving system and a transmission method, which can improve the efficiency of the workload proving system.

In one aspect, the present application provides a control chip applied to a workload certification system, including:

the system comprises a data register, a processing module and a Serial Peripheral Interface (SPI) driving module;

the data register is used for storing M-bit task data to be sent and outputting the stored task data under the control of the processing module; wherein M is the bit width of the data register;

the processing module is used for controlling the SPI driving module, and sending the task data which is continuously output by the data register for N times to the workload proving chip through an SPI data frame; wherein N is a positive integer greater than 1.

Optionally, the data register comprises a M-bit transmit buffer; the N is equal to the total number of bits of task data to be sent to one workload certification chip in one task cycle divided by M.

Optionally, the control chip further includes:

a first register and a second register;

the processing module controls the SPI driving module, and sends the task data output by the data register for N times to the workload proving chip through an SPI data frame, wherein the processing module comprises:

the processing module determines N according to the bit width M of the data register and the total bit number of the task data to be sent to each workload certification chip in one task cycle, and stores the N in the first register; the following sending operations are respectively performed for each workload proving chip: and controlling the data register to continuously output the task data to the second register until the continuous output times reach the value N stored in the first register, and controlling the SPI driving module to send the task data stored in the second register to the workload certification chip through an SPI data frame.

Optionally, the processing module is further configured to control the SPI driving module to receive result data read from the workload certification chip through an SPI data frame; the result data is N 'multiplied by M' bits, M 'is the bit width of a data register in the workload proving chip, and N' is a positive integer.

Optionally, the control chip further includes:

a first register and a second register;

the processing module controls the SPI driving module to receive the data read from the workload certification chip through an SPI data frame, and the data reading comprises the following steps:

the processing module determines N according to the bit width M of the data register of the control chip and the total bit number of the result data in an SPI data frame, and stores the N in the first register; controlling the SPI driving module to store the result data in the SPI data frame in the second register; and sequentially reading the result data in the second register, writing the result data into a data register of the control chip, and reading M bits each time until the writing times reach the value N stored in the first register.

In another aspect, an embodiment of the present application provides a workload proving system, including: the system comprises a control chip, a Serial Peripheral Interface (SPI) bus and a plurality of workload proving chips connected with the control chip through the SPI bus;

and each workload proving chip is respectively used for continuously receiving and storing task data from one SPI data frame when a chip selection signal on the SPI bus is valid.

Optionally, the workload certification chip is further configured to send the result data of the N '× M' bits to the control chip in an SPI data frame according to an instruction of the control chip after the result data is obtained; m 'is the bit width of a data register in the workload proof chip, and N' is a positive integer.

Optionally, the workload certification chip is further configured to, in a process of writing a last M 'bit of task data in an SPI data frame, if it is detected that the chip select signal is turned to be invalid, not write the last M' bit of task data in an address space corresponding to the SPI of the chip; wherein, M' is the bit width of the data register in the workload proving chip.

In another aspect, an embodiment of the present application further provides a transmission method, applied in the workload proving system, including:

writing task data continuously output by a data register in a control chip for N times into an SPI data frame, wherein N is a positive integer;

and sending the SPI data frame to a workload certification chip through an SPI bus.

Optionally, the transmission method further includes:

after the workload proving chip obtains the result data, according to the instruction of the control chip, the result data of N '× M' bit is sent to the control chip through an SPI data frame; m 'is the bit width of a data register in the workload proof chip, and N' is a positive integer.

Compared with the prior art, the method and the device have the advantages that the task data output by the data register for N times can be sent to the workload proving chip at one time, and because the command data and the addr data are fixedly contained in one SPI data frame, the overhead of transmitting the command data and the addr data can be obviously saved, so that the efficiency of transmitting the task data to the workload proving chip can be improved, the time consumption of sending the task data in a task period is reduced, and the method and the device are favorable for reducing the computational power loss. Because task data needs to be sent to a plurality of workload proving chips in one task period, the sending of the task data is a main factor influencing the time spent in the task period.

Other aspects will be apparent upon reading and understanding the attached drawings and detailed description.

Drawings

The accompanying drawings are included to provide an understanding of the present disclosure and are incorporated in and constitute a part of this specification, illustrate embodiments of the disclosure and together with the examples serve to explain the principles of the disclosure and not to limit the disclosure.

FIG. 1 is a schematic diagram of a write timing sequence for transmitting task data of one bit width per frame;

FIG. 2 is a schematic representation of a read timing for transmitting one bit wide result data per frame;

FIG. 3 is a schematic diagram of a control chip according to an embodiment of the present application;

FIG. 4 is a schematic diagram of a control chip in accordance with an exemplary embodiment;

FIG. 5 is a schematic diagram of a workload certification system of an embodiment of the present application;

fig. 6 is a schematic diagram of a transmission method according to an embodiment of the present application;

FIG. 7 is a schematic diagram illustrating a write timing sequence in example one;

FIG. 8 is a schematic diagram of read timing in example two.

Detailed Description

The present application describes embodiments, but the description is illustrative rather than limiting and it will be apparent to those of ordinary skill in the art that many more embodiments and implementations are possible within the scope of the embodiments described herein. Although many possible combinations of features are shown in the drawings and discussed in the detailed description, many other combinations of the disclosed features are possible. Any feature or element of any embodiment may be used in combination with or instead of any other feature or element in any other embodiment, unless expressly limited otherwise.

The present application includes and contemplates combinations of features and elements known to those of ordinary skill in the art. The embodiments, features and elements disclosed in this application may also be combined with any conventional features or elements to form a unique inventive aspect. Any feature or element of any embodiment may also be combined with features or elements from other inventive aspects to form yet another unique inventive aspect. Thus, it should be understood that any of the features shown and/or discussed in this application may be implemented alone or in any suitable combination. In addition, various modifications and changes may be made within the scope of protection.

Further, in describing representative embodiments, the specification may have presented the method and/or process as a particular sequence of steps. However, to the extent that the method or process does not rely on the particular order of steps set forth herein, the method or process should not be limited to the particular sequence of steps described. Other orders of steps are possible as will be understood by those of ordinary skill in the art. Accordingly, the particular order of the steps set forth in the specification should not be construed as limitations on the present application. Further, the methods and/or processes should not be limited to the performance of their steps in the order written, and one skilled in the art can readily appreciate that the sequences may be varied and still remain within the spirit and scope of the embodiments of the present application.

In addition, descriptions in this application as to "first", "second", etc. are used for differentiation in description only, and are not to be construed as indicating or implying relative importance or implicitly indicating the number of technical features indicated. Thus, a feature defined as "first" or "second" may explicitly or implicitly include at least one such feature. In the description of the present application, "plurality" means at least two, e.g., two, three, etc., unless specifically limited otherwise.

In many current blockchain platforms, workload proofs need to be done when creating valid blocks. Because the calculation amount of the workload certification is possibly huge, a workload certification system is provided in the related technology, a task of the workload certification can be issued by a central node, a plurality of workload certification nodes in the system respectively perform partial calculation in the workload certification, and if an effective result is obtained, the result is summarized to the central node; in a task period of a workload certification, the workload certification system sequentially performs the following four steps: 1) receiving a new task from the central node; 2) the control chip issues the task data to all the workload proving chips; 3) each workload proving chip respectively starts to calculate; 4) the control chip obtains effective result data calculated by the workload proving chip, if the effective result data is obtained, the effective result data is submitted to the central node, and a new block can be generated after the effective result data is successfully submitted.

Considering that the period of task update is generally short, such as about 2 seconds, once a task is updated, a new task period of workload certification is started; it is therefore necessary to complete the four steps as quickly as possible to ensure that the results of the current task are successfully submitted before the task is updated. Step 3) is mainly related to the performance of the workload certification chip in a task period of workload certification; steps 1) and 2) are preparation work before the workload proving chip starts to calculate, and the smaller the time proportion occupied by the two steps is, the smaller the calculation force loss of the workload proving chip is, and the higher the efficiency of the workload proving system is. And step 4) reading effective results from the workload proving chip, wherein the less time is consumed in the step, the higher the probability that the workload proving system meets the results before updating the tasks is increased. Wherein, the step 1) is mainly determined by the internet speed, and the steps 2) and 4) are mainly influenced by the speed and the efficiency of the communication interface of the workload proving chip. In these four steps, the cost of increasing the workload to prove the performance of the chip, i.e., speeding up step 3), is generally expensive; the internet rate in step 1) has an upper limit; if one starts from step 2) and/or 4), the cost of replacing/modifying the communication interface for the existing workload proving system and chip will be very large. Based on the above consideration, the embodiments of the present application provide a control chip, a workload certification system and a transmission method, which can significantly improve the transmission efficiency in the workload certification system at a low cost, reduce the computational power loss of the workload certification chip, and be compatible with the existing workload certification chip.

The board-level system where the workload certification chip is located generally communicates based on a bus of an SPI (Serial Peripheral Interface) full-duplex protocol, where SPI is a full-duplex, synchronous communication bus and operates in a master-slave manner, and this mode generally has one master device and at least one slave device. In the context of a workload certification system, a control chip for issuing task data and acquiring result data may be used as a master device, and each workload certification chip may be used as a slave device. In a task period of workload certification, the step of issuing task data can be regarded as writing data into a workload certification chip by a control chip, namely issuing the task data is a write time sequence; the step of obtaining the result data may be regarded as the step of the control chip reading data from the workload proving chip, that is, the step of obtaining the result data is a read timing sequence.

In one example, the transmission is performed according to the bit width of the SPI address space (or the bit width of the data registers at the two ends of the SPI bus transceiver), and one bit width of task/result data is transmitted each time.

In this example, the definition of the SPI signal for a workload demonstration chip is shown in table one:

TABLE I definition of SPI signals in workload certification chips

Signal Name	Type	Description
			cs_n	input	Chip select signal, active low
sck	input	Serial clock input
			si	input	Serial data input
so	output	Serial data output

The cs _ n signal is used to indicate whether the workload verification chip is selected, and may be regarded as an enable signal of the workload verification chip, when cs _ n is valid (at a high level or a low level), the access of the workload verification chip is enabled, and the read or write operation of the workload verification chip is valid, that is, the workload verification chip can be written with data or read with data; the low level of cs _ n in this example indicates that the workload proof chip is selected as the slave device for the current communication.

The sck signal is a clock signal generated by the master device; since the SPI is a serial communication protocol, i.e. data is transmitted one bit by one bit (i.e. bit by bit), the sck signal is required to be present, the clock pulse is provided by sck, and the si, so signals complete data transmission based on the pulse.

The si signal is the data output of the master device, the data input of the slave device, and for the workload proving chip, serial task data is received, and the control chip writes data into the workload proving chip; the so signal is the master device data input and the slave device data output, and for the workload proving chip, serial result data is output, and the control chip reads data from the workload proving chip.

In this example, it is assumed that the address spaces of the SPI of the control chip and the workload prove that both are 16 bits, and the bit widths of the data registers used in both the chip and the SPI bus are both 16 bits; the bit width refers to a data amount that can be transmitted at one time.

In this example, the SPI write timing is shown in fig. 1.

One write timing frame (frame) includes three portions of data: command, addr and data.

command, total 8 bits, representing that the action of the current frame is writing time sequence;

addr is 16 bits in total and represents the accessed address of the chip;

and the data is 16 bits in total, and represents that the control chip needs to write 16-bit task data of the workload proving chip.

In this example, the SPI read timing is shown in fig. 2.

A read timing frame includes three portions of data: command, addr and data.

The command is 8 bits in total, and represents that the behavior of the current frame is a reading sequence;

addr is 16 bits in total and represents the accessed address of the chip;

and the data is 16 bits in total and represents 16-bit result data which is stored in the address space of the addr of the workload proving chip and is to be acquired by the control chip.

It can be seen that the read or write timing requires at least 16 clock signal changes (16 clock cycles) to complete the 16bit data transfer. Assuming that the task data and the result data are 1024 bits, if 16 bits are transmitted each time, the transmission of the whole task data is completed, and the transmission is required to be performed 64 times in total. The write-once timing frame needs 40 clock cycles to complete the transmission of the whole task data, and needs 40 × 64 = 2560 clock cycles. The task data is 1024 bits, resulting in a transmission efficiency of 1024/2560 = 40%. Similarly, the transmission of the entire result data is completed, and the transmission is required to be performed 64 times in total. The read timing frame needs 40 clock cycles in total, and the transmission of the whole data packet of the obtained result needs 40 × 64 = 2560 clock cycles in total. The data packet is 1024 bits, resulting in a transmission efficiency of 1024/2560 = 40%.

It can be seen that, since the rate range supported by the SPI protocol is 4-16MHz, the interval of the transmission rate of the workload verification chip when acquiring the task data and providing the result data is basically determined, the required clock period is also basically determined, and the transmission time between the control chip and the workload verification chip is difficult to be shortened. In the workload proving system, the workload proving chip is responsible for operation and provides calculation power for the block chain. The transmission efficiency between the workload certification chip and the control chip will affect the efficiency of the whole workload certification system, and further affect the efficiency of the block chain system.

The embodiment of the present application provides a control chip, which is applied to a workload proving system, as shown in fig. 3, and includes:

a data register 31, a processing module 32 and an SPI driving module 33;

the data register 31 is used for storing task data of M bits to be sent and outputting the stored task data under the control of the processing module 32; wherein M is the bit width of the data register;

the processing module 32 is configured to control the SPI driving module 33, and send task data, which is continuously output by the data register 31 for N times, to the workload certification chip through one SPI data frame; n is a positive integer greater than 1.

In this embodiment, the task data output by the data register 31 for N consecutive times may be sent to the workload certification chip at one time, and since one SPI data frame fixedly includes the command and addr data, compared with a scheme in which the task data output by the data register 31 each time is transmitted by one SPI data frame, this embodiment may significantly save the overhead of transmitting the command and addr data, thereby improving the efficiency of transmitting the task data to the workload certification chip, reducing the time consumption of sending the task data in a task period, and being beneficial to reducing the computational power loss. Since task data needs to be sent to a plurality of workload certification chips in one task period, the sending of the task data is a main factor influencing the time spent in the task period.

In this embodiment, one control chip needs to send task data to a plurality of workload certification chips, and each workload certification chip may be processed in the manner of this embodiment. For the workload proving chip, hardware and software can be not required to be changed, and data in the SPI data frame is continuously read and stored in sequence by taking addr as a starting address when a chip selection signal is effective. On the basis of being compatible with the current workload chip, the transmission efficiency can be obviously improved by only slightly modifying the control chip.

In this embodiment, in a task period, task data issued by the central node may be first stored in a storage area corresponding to an address space of the SPI, and the storage area may be set in a storage module of the control chip or the control board or other components; then, according to the bit width M of the data register 31, the first M bit in the task data is written into the data register 31; after the task data in the data register 31 is output, writing the next M bit task data into the data register 31, and so on; until the full portion of the task data is written.

In this embodiment, the data register 31 is a register corresponding to the SPI bus, and is used to transmit data between the SPI bus and the address space of the SPI; the data register 31 may include two buffers, one of which is a transmission buffer for storing task data to be written to the workload certification chip; the other is a receiving buffer area used for storing result data obtained from the workload proving chip; the bit widths of the two buffers are typically equal.

In an implementation manner of this embodiment, it is assumed that the data register outputs M bits of task data at a time, the command is 8 bits, and the addr is 16 bits, and when the task data output N times consecutively is placed in an SPI data frame and sent to the workload certification chip, one SPI data frame includes (N × M +24) bits of data, that is, a write timing is (N × M +24) clock cycles. One piece of SPI data comprises task data of N multiplied by M bits, and if the task data to be sent to one workload proving chip in one task period is S bits, the task period needs to use S/(N multiplied by M) writing time sequences in total, namely, the task data aiming at the workload proving chip is sent by using an SPI data frame of S/(N multiplied by M); for convenience of explanation, it is assumed that S/(N × M) is an integer, and if S/(N × M) is not an integer, the number of write timings (the number of SPI data frames) to be used may be rounded up.

From the above analysis, in one task cycle, the total number P of clock cycles required for one workload proof chip to complete transmission of task data is:

P =（N×M+24）S/（N×M）= S+ 24×S/（N×M）

it can be seen that the larger (nxm), the fewer clock cycles are required to complete the task data transmission of one workload proof chip in one task cycle; since M generally depends on the bit width of the hardware, and is not variable in the case where the hardware is already selected (e.g., the workload proof chip is already manufactured or purchased), the total number P of clock cycles used to send task data to a workload proof chip in a task cycle can be further reduced by increasing N. The transmission efficiency is S/P, and the transmission efficiency increases when P decreases, i.e. the larger an SPI data frame (the more task data is contained), the higher the transmission efficiency.

In an exemplary embodiment, the data register 31 includes a transmit buffer of M bits, M being a positive integer; in general, M may be 8 or 16, and may be the same bit width as the data register in the workload proof chip that receives the task data.

In this embodiment, N may be equal to the total number of bits S of task data to be sent to one workload certification chip in one task cycle divided by M.

In this embodiment, all task data to be sent to a workload certification chip in one task cycle are put in one SPI data frame for transmission, that is, the task data to be sent to the workload certification chip in one task cycle is sent using a write timing sequence only once, the write timing sequence requires S +24 clock cycles, and the transmission efficiency is S/(S + 24).

In an embodiment of this embodiment, S =1024 bits, and M =16 bits, then N =1024/16= 64. In one task cycle, task data is transmitted by using a write timing sequence for each workload demonstration chip, the write timing sequence comprises 1048 clock cycles, and the transmission efficiency is 1024/1048= 97.7%. It can be seen that the transmission efficiency is doubled compared to the transmission efficiency of 40% in the scheme shown in fig. 1, which is 97.7%/40% = 2.44; in this embodiment, the clock cycle taken to transmit task data to a workload proof chip in a task cycle is compared to the scheme shown in fig. 1: 1048/2560 = 40.9%, it can be seen that the hour hand period is reduced by more than half, greatly reducing the transmission time.

In this embodiment, for \35764csong workload proving chips for which the control chip needs to send task data, N may be the same, which is S divided by M.

In an alternative of this embodiment, in consideration of the fact that if the task data is more and the cost is larger in case of transmission error in one SPI data frame, N may be set to (S/M)/Q, and Q may be a positive integer power of 2, such as 2, 4, 8, and the like. For example, S =1024 bit, and M =16 bit, N may be equal to 1024/16/4=16, that is: task data to be sent to a workload certification chip in one task cycle is sent in 4 write sequences, so that 1024+ 24 × 1024/(16 × 16) =1120 clock cycles are required for sending the task data by one workload certification chip, the transmission efficiency is 1024/1120=91.4%, although the scheme is slightly lower than the scheme of N =64, the transmission efficiency is greatly improved compared with 40%.

In an exemplary embodiment, the control chip may be, but is not limited to, an fpga (field Programmable Gate array) integrated with a processor core; the workload proving chip may also be referred to as a computational chip.

In an exemplary embodiment, the control chip is shown in fig. 4, and further includes:

a first register 34 and a second register 35;

the processing module 32 controls the SPI driving module 33, and sends the task data output by the data register 31 for N consecutive times to the workload certification chip through an SPI data frame, including:

the processing module 32 determines N according to the bit width M of the data register 31 and the total bit number S of the task data to be sent to each workload certification chip in one task cycle, and stores N in the first register 34; the following sending operations are respectively performed for each workload proving chip: the control data register 31 continuously outputs the task data to the second register 35 until the number of continuous outputs reaches the value N stored in the first register, and controls the SPI driver module 33 to send all the task data stored in the second register 35 to the workload certification chip through one SPI data frame.

In this embodiment, by adding two registers to the control chip, it is possible to send task data output by the data register 31 for N consecutive times through one SPI data frame, and the processing module 32 and the two registers directly interact with each other in the chip, and the interaction time is basically negligible. In an alternative of this embodiment, the first and second registers may not be disposed in the control chip; or the task data output by the data register 31 for N consecutive times is directly sent by one SPI data frame without adding a register, without using a second register for transfer, and the task data output by the data register 31 for each consecutive N times is sequentially put into the SPI data frame.

In this embodiment, the nxm bit task data may occupy all or part of the storage space of the second register 35; the capacity in the second register 35 can be set relatively large to ensure that the storage space is sufficiently used when N is large. At initialization, the second register 35 may be empty, so that all task data output from the data register 31 will be stored in the second register 35. For each task data output by the data register 31, the second register 35 may sequentially hold; after one transmission of the SPI data frame, the second register 35 may be emptied or the original task data in the second register 35 may be overwritten with the task data of the next batch.

In this embodiment, the processing module 32 may count the output of the data register 31, compare the count value with the value N stored in the first register 34, and control the data register 31 to continue outputting the task data to the second register 35 if N is not reached; alternatively, the processing module 32 subtracts 1 from the value in the first register 34 after each output of the control data register 31 until the value is 0, which means that the output has been performed N times.

In this embodiment, when N is determined according to S and M, S/M may be used as N without limitation.

In an exemplary embodiment, the processing module 32 may be further configured to control the SPI driving module 33 to receive the result data read from the workload proving chip through one SPI data frame; the result data is N 'multiplied by M' bit, M 'is the bit width of a data register in the workload proving chip, and N' is a positive integer.

In this embodiment, the workload proves that the bit width M' of the data register of the chip and the bit width M of the data register 31 of the control chip may be equal; n' and N may be equal.

In this embodiment, for the received N '× M' bit result data, M bits may be stored in the receiving buffer of the data register 31 each time, and then output from the receiving buffer to the storage area corresponding to the address space of the SPI, and the storage area may be located in the storage module of the control chip or the control board or other components; writing the M bit result data output from the receiving buffer area into the storage module in sequence each time until all the result data in the SPI data frame are stored into the storage module; the result data may be submitted to a central node.

In this embodiment, the result data output by the data register of the workload certification chip for N 'times continuously may be transmitted at one time, and since one SPI data frame fixedly includes command and addr data, compared with a scheme in which each M' bit result data is transmitted by one SPI data frame, this embodiment may significantly save the overhead of transmitting the command and addr data, thereby improving the transmission efficiency of obtaining the result data and reducing the time consumption of obtaining the result data in a task period.

In this embodiment, among the plurality of workload proof chips interacted with the control chip, a part or all of the workload proof chips may generate valid result data; in this embodiment, for the workload certification chips that generate result data, the result data may be obtained by adopting the manner of this embodiment, respectively.

In this embodiment, the workload proves that the control logic of the chip itself may not change, and the chip selection signal is still output through the data register continuously when it is valid; the data register reads the result data of the M' bit which is not output every time and writes the result data into the SPI data frame; if the chip selection signal is continuously effective, the workload proves that the chip can send the SPI data frame to the control chip until all result data of the task period are written into the SPI data frame.

In an alternative of this embodiment, the result data may be obtained according to the scheme shown in fig. 2 for at least a part of the workload proving chip that generates the result data. Although the transmission efficiency of the acquired result data is not improved, the transmission efficiency is greatly improved when the task data is sent, so that the transmission efficiency is still improved for the whole workload proving system.

In an implementation manner of this embodiment, as shown in fig. 4, the control chip further includes:

a first register 34 and a second register 35;

the controlling of the SPI driving module 33 by the processing module 32 to receive the result data read from the workload certification chip through one SPI data frame may include:

the processing module 32 determines N according to the bit width M of the data register 31 and the total bit number of the result data in one SPI data frame, and stores N in the first register 34; controlling the SPI driving module 33 to store the result data in the SPI data frame in the second register 35; the result data of the M bits read from the second register 35 are written into the data register 31 in sequence, and the M bits are read each time until the number of writing times reaches the value N stored in the first register.

In an alternative of this embodiment, the first and second registers may not be disposed in the control chip; or the result data in the SPI data frame is directly transferred to the storage module through the data register 31 in an N-time mode in a pure software control mode without adding a register, and the second register is not used for transferring.

An embodiment of the present application further provides a workload proving system, as shown in fig. 5, including: the control chip 51, the SPI bus 52, and the plurality of workload certification chips 53 connected to the control chip 51 through the SPI bus 52 in any of the above embodiments;

each workload verification chip 53 is configured to continuously receive and store task data from one SPI data frame when a chip select signal is active.

In an exemplary embodiment, the workload certification chip 53 may be further configured to send the result data of N '× M' bit to the control chip through an SPI data frame according to an instruction of the control chip after obtaining the result data; m 'is the bit width of a data register in the workload proof chip, and N' is a positive integer.

In this embodiment, the indication of the control chip may refer to a chip select signal on the SPI bus, and the workload certification chip 53 outputs result data to the control chip when the chip select signal is valid.

In this embodiment, if all of the workload verification chips obtain result data, the result data may be sent according to the method of this embodiment.

In an exemplary embodiment, the workload certification chip 53 may also be configured to, in the process of writing the last M 'bit of the task data in one SPI data frame, if it is detected that the chip select signal is turned to be invalid, not write the task data of the last M' bit into an address space corresponding to the SPI of the chip; wherein, M' is the bit width of the data register in the workload proving chip.

In this embodiment, the chip select signal is changed to be invalid, which means that the chip select signal is changed to be invalid when the chip select signal is changed to be active at a low level.

An embodiment of the present application further provides a transmission method, which is applied to the workload proving system provided in the foregoing embodiment, and as shown in fig. 6, the method includes:

s601, writing task data continuously output by the data register 31 in the control chip for N times into an SPI data frame, wherein N is a positive integer;

and S602, sending the SPI data frame to a workload proving chip through an SPI bus.

In this embodiment, when the control chip interacts with a plurality of workload verification chips, the steps of this embodiment may be respectively adopted for each workload verification chip to perform sending.

In an exemplary embodiment, the method may further include:

The above embodiments are described below using two specific examples.

Example 1

In this example, task data output by the data register of the control chip N times continuously is sent through one SPI data frame, and as shown in fig. 7, a frame of a write-once timing includes three parts: command, addr _ base, and data _ array.

addr _ base, which is 16 bits in total and represents the initial address of the chip accessed;

data _ array consists of N16-bit task data, wherein N can be an arbitrary value or determined by dividing the total number S of bits of the task data in one task period by 16 bits.

For example, the following steps are carried out: assuming that the workload certification chip uses a register with a bit width of 16 bits, if the current frame is a write timing sequence, and N task data of 16 bits included in the data _ array are data 0, data1, … …, and data N, respectively, data 0 will be written into the address addr _ base, data1 will be written into the address addr _ base +1, … …, and data N will be written into the address addr _ base + N.

In this example, it is proved based on the workload that the bit width of the data register in the chip is 16 bits, and the writing of the task data is performed by taking 16 bits as a unit; if the last data N has not transmitted 16 bits in the writing process and a stop signal occurs (cs _ N is high), the last data N of 16 bits will not be written into the address space corresponding to the SPI of the workload proving chip.

In this example, the frame of the write-once timing completes the transmission of 1024 bits, and 8+16+1024 = 1048 cycles are required, so that the transmission efficiency is 1024/1048= 97.7%. When the transmission of the task data with the same bit number is completed, the total consumed time of the example is 1048/2560 = 40.9% of the scheme shown in fig. 1, and the efficiency is 97.7%/40% = 2.44 times.

Example two

The example can adopt the scheme of the first example in the step of sending the task data; unlike the first example, the second example transmits the result data by transmitting the result data output N' times in succession from the data register in the workload verification chip through one SPI data frame. The read timing in this example is shown in fig. 8, and the frame of the one-time read timing includes three parts: command, addr _ base, and data _ array.

16 bits in total, and the addr _ base represents the initial address of the accessed chip proved by the workload;

and the data _ array consists of N '16-bit data, wherein N' is an arbitrary value or is obtained by dividing the total bit number of the result data by the bit width 16bit of the data register of the workload proving chip.

For example, the following steps are carried out: assuming that the workload proves that the chip uses a register with a bit width of 16 bits, if the current frame is a read sequence, the N16-bit result data included in the data _ array are data 0, data1, … … and data N ', respectively, then data 0 is the data stored by the chip address addr _ base, data1 is the data stored by the chip address addr _ base +1, and … …, data N is the data stored by the chip address addr _ base + N'. Where N' may be equal to N.

During continuous reading, the control chip can send out a stop signal (cs _ n is high) at any time, and after the stop signal is generated, the so line stops outputting data.

The frame of the once read sequence completes the transmission of 1024 bits totally, 8+16+1024 = 1048 periods are needed totally, and the transmission efficiency is 1024/1048= 97.7%. The reading of the result data of the same bit number is completed, the total consumed time of the example is 1048/2560 = 40.9% of the scheme of fig. 2, and the efficiency is 97.7%/40% = 2.44 times.

The example is applied to a workload proving system, and compared with the schemes shown in fig. 1 and 2, the time consumption of data transmission on a communication bus can be greatly reduced in the process of issuing task data packets and acquiring result data packets. The efficiency of issuing the task data is improved, the time consumption of preparation work in a task period can be reduced, and the calculation power loss is reduced; the efficiency of obtaining the result data is improved, the time for reading the result data from the workload proving chip can be reduced, and the probability of submitting the result of the workload proving system before the task is updated is favorably improved.

It will be understood by those of ordinary skill in the art that all or some of the steps of the methods, systems, functional modules/units in the devices disclosed above may be implemented as software, firmware, hardware, and suitable combinations thereof. In a hardware implementation, the division between functional modules/units mentioned in the above description does not necessarily correspond to the division of physical components; for example, one physical component may have multiple functions, or one function or step may be performed by several physical components in cooperation. Some or all of the components may be implemented as software executed by a processor, such as a digital signal processor or microprocessor, or as hardware, or as an integrated circuit, such as an application specific integrated circuit. Such software may be distributed on computer readable media, which may include computer storage media (or non-transitory media) and communication media (or transitory media). The term computer storage media includes volatile and nonvolatile, removable and non-removable media implemented in any method or technology for storage of information such as computer readable instructions, data structures, program modules or other data, as is well known to those of ordinary skill in the art. Computer storage media includes, but is not limited to, RAM, ROM, EEPROM, flash memory or other memory technology, CD-ROM, Digital Versatile Disks (DVD) or other optical disk storage, magnetic cassettes, magnetic tape, magnetic disk storage or other magnetic storage devices, or any other medium which can be used to store the desired information and which can accessed by a computer. In addition, communication media typically embodies computer readable instructions, data structures, program modules or other data in a modulated data signal such as a carrier wave or other transport mechanism and includes any information delivery media as known to those skilled in the art.

Claims

1. A control chip applied to a workload proving system, comprising:

2. The control chip of claim 1, wherein:

the data register comprises a M-bit transmission buffer area; the N is equal to the total number of bits of task data to be sent to one workload certification chip in one task cycle divided by M.

3. The control chip of claim 1, further comprising:

a first register and a second register;

4. The control chip of claim 1, wherein:

the processing module is also used for controlling the SPI driving module to receive result data read from the workload proving chip through an SPI data frame; the result data is N 'multiplied by M' bits, M 'is the bit width of a data register in the workload proving chip, and N' is a positive integer.

5. The control chip of claim 4, further comprising:

a first register and a second register;

6. A workload certification system, comprising: the control chip of any of claims 1-5, a Serial Peripheral Interface (SPI) bus, and a plurality of workload attestation chips connected through the SPI bus and the control chip;

7. The workload certification system according to claim 6, wherein:

the workload proving chip is also used for sending the result data of N 'multiplied by M' bits to the control chip in an SPI data frame according to the instruction of the control chip after the result data is obtained; m 'is the bit width of a data register in the workload proof chip, and N' is a positive integer.

8. The workload certification system according to claim 6, wherein:

the workload proving chip is also used for not writing the task data of the last M 'bit into an address space corresponding to the SPI of the chip if the chip selection signal is detected to be invalid in the process of writing the last M' bit of the task data in an SPI data frame; wherein, M' is the bit width of the data register in the workload proving chip.

9. A transmission method applied in the workload certification system according to any one of claims 6 to 8, comprising:

10. The transmission method of claim 9, further comprising: