CN114461477A - Method and device for realizing chip detection, computer storage medium and terminal - Google Patents
Method and device for realizing chip detection, computer storage medium and terminal Download PDFInfo
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Abstract
Disclosed herein are a method, an apparatus, a computer storage medium and a terminal for implementing chip detection, including: for a proof of work (PoW) chip in a static test, acquiring first data read by a first logic calculation unit (ALU) for each ALU, the first data being read from a first memory block according to a preset memory address; determining a first ALU for the workload proving operation according to the determined correct rate of the data reading of the first ALU; the first ALU is any ALU in the PoW chip to be detected; the memory address includes: a preset number of addresses determined according to the distribution of address lines and/or data lines for transmitting data. According to the embodiment of the invention, whether the first ALU is used for the workload proving operation or not is judged through the data reading of the preset memory address, so that the detection time of the PoW chip is reduced; furthermore, other components are prevented from influencing the current functional unit of the chip by gradually detecting other parts of the chip.
Description
Technical Field
The present disclosure relates to, but not limited to, chip detection technologies, and in particular, to a method, an apparatus, a computer storage medium, and a terminal for implementing chip detection.
Background
The proof of workload (PoW) algorithm generally requires a large memory and a large number of channels, so PoW chips often have the following characteristics: 1) integrating more compute units (ALUs); 2) integrating more storage control units; 3) and integrating a full connection control unit. The larger the number of integrated functional units of the PoW chip is, the more the functional units may cause problems, i.e., chip differences, in the chip production process.
The detection methods of the general workload proving chip are as follows: 1) design for testability (DFT), which can quickly detect whether the internal connection of the chip is correctly connected, but does not detect whether the chip functions are normal; 2) testing each functional unit by designing a functional test script program, and marking the failed functional unit if the functional unit is determined to be failed through detection; because functional units in a chip are mutually influenced, when one functional unit fails, a single test cannot judge whether the functional unit fails or is caused by the failure of other functional units, and therefore each functional unit needs to be detected as much as possible, and the problem of long test time exists; in addition, the above method cannot detect the chip in use in real time, and when a new failed functional unit occurs in the use process of the chip, the failed functional unit cannot be determined.
Disclosure of Invention
The following is a summary of the subject matter described in detail herein. This summary is not intended to limit the scope of the claims.
The embodiment of the invention provides a method and a device for realizing chip detection, a computer storage medium and a terminal, which can reduce the detection time of a PoW chip.
The embodiment of the invention provides a method for realizing chip detection, which comprises the following steps:
for a workload certification PoW chip in a static test, aiming at each first logic calculation unit ALU, obtaining first data read by the first ALU, wherein the first data are read from a first storage block according to a preset memory address;
determining the correct rate of the first ALU data reading according to the acquired first data read by the first ALU;
determining a first ALU for the workload proving operation according to the determined correct rate of the data reading of the first ALU;
the first ALU is any ALU in the PoW chip to be detected; the memory address includes: a preset number of addresses determined according to the distribution of address lines and/or data lines for transmitting data.
In one illustrative example, the determining a first ALU for a workload attestation operation includes:
and when the accuracy of the data reading of the first ALU is greater than a preset accuracy threshold value, determining that the first ALU is used for the workload proving operation.
In one illustrative example, after the determining the first ALU for the workload attestation operation, for each first ALU other than the first ALU determined for the workload attestation operation, the method further comprises:
acquiring second data read by each second ALU, wherein the second data are read from the first storage block according to the corresponding memory address of each second ALU;
according to the second data read by each second ALU, respectively determining the correct rate of the data read corresponding to each second ALU;
determining a first memory block and a first lower terminal for a workload proving operation according to the determined correct rate of data reading corresponding to each of the second ALUs; wherein the second ALU comprises: the other ALUs except the first ALU in the PoW chip; the first lower terminal is a lower terminal connected with the first storage block in the full-connection control module of the PoW chip.
In one illustrative example, the determining a first memory block and a first lower terminal for a workload attestation operation includes:
determining that the first memory block and first lower terminal are used for a workload attestation operation when a correctness rate of one or more of the second ALU data reads is greater than the correctness rate threshold.
In one illustrative example, after determining the first memory block and the first lower terminal for the workload justification operation, for each of the first ALUs, when a correct rate of all of the second ALU read data is less than or equal to the correct rate threshold, the method further comprises:
acquiring third data read by the first ALU, wherein the third data are read from all second storage blocks according to a preset memory address;
according to the acquired third data read by the first ALU, the correct rate of data reading of the first ALU from each second storage block is determined respectively;
determining a first upper terminal for workload proving operation according to the determined correct rate of data reading of the first ALU from each second storage block;
wherein the second memory block includes: storing other memory blocks in the PoW chip except the first memory block; the first upper terminal is an upper terminal connected with the first ALU in a full-connection control module of the PoW chip.
In one illustrative example, the determining a first upper terminal for workload attestation operations includes:
and when the correctness rate of the first ALU for data reading from more than one second storage block is greater than the correctness rate threshold value, determining that a first upper terminal is used for workload proving operation.
In one illustrative example, when a correct rate of data reads by the first ALU from all of the second memory blocks after the determining the first upper terminal for the workload proving operation is less than or equal to the correct rate threshold, the method further comprises:
determining that the connection between the first upper terminal and the first lower terminal is invalid.
In one illustrative example, the method further comprises:
respectively counting the operation success rate of the ALU to be executed for each ALU of the PoW chip in the working state;
and when the operation success rate of the ALU is less than a preset success rate threshold value, determining that the ALU is not used for the workload proving operation.
On the other hand, an embodiment of the present invention further provides a computer storage medium, where a computer program is stored, and when the computer program is executed by a processor, the method for implementing chip detection is implemented.
In another aspect, an embodiment of the present invention further provides a terminal, including: a memory and a processor, the memory having a computer program stored therein; wherein the content of the first and second substances,
the processor is configured to execute the computer program in the memory;
the computer program, when executed by the processor, implements a method of implementing chip detection as described above.
In another aspect, an embodiment of the present invention further provides an apparatus for implementing chip detection, including: the device comprises an acquisition unit, a correct rate determining unit and a result determining unit; wherein the content of the first and second substances,
the acquisition unit is configured to: for a workload certification PoW chip in a static test, aiming at each first logic calculation unit ALU, obtaining first data read by the first ALU, wherein the first data are read from a first storage block according to a preset memory address;
the unit for determining the correct rate is set as: determining the correct rate of the first ALU data reading according to the acquired first data read by the first ALU;
the determination result unit is set to: determining a first ALU for the workload proving operation according to the determined correctness of the data reading of the first ALU;
the first ALU is any ALU in the PoW chip to be detected; the memory address includes: a preset number of addresses determined according to the distribution of address lines and/or data lines for transmitting data.
The technical scheme of the application includes: for a proof of work (PoW) chip in a static test, acquiring first data read by a first logic calculation unit (ALU) for each ALU, the first data being read from a first memory block according to a preset memory address; determining the correct rate of the first ALU data reading according to the acquired first data read by the first ALU; determining a first ALU for the workload proving operation according to the determined correct rate of the data reading of the first ALU; the first ALU is any ALU in the PoW chip to be detected; the memory address includes: a preset number of addresses determined according to the distribution of address lines and/or data lines for transmitting data. According to the embodiment of the invention, whether the first ALU is used for the workload proving operation or not is judged by acquiring the correct rate of the data read by the first ALU through the preset number of memory addresses, so that the detection time length of the functional unit in the PoW chip is reduced; furthermore, in the embodiment of the present invention, when the accuracy of the first ALU data reading is less than or equal to the accuracy threshold, the first ALU, the first memory block, and the upper terminal and the lower terminal therebetween are detected step by step, so that the current functional unit is prevented from being affected by other functional units included in the chip.
Additional features and advantages of the invention will be set forth in the description which follows, and in part will be obvious from the description, or may be learned by practice of the invention. The objectives and other advantages of the invention will be realized and attained by the structure particularly pointed out in the written description and claims hereof as well as the appended drawings.
Drawings
The accompanying drawings are included to provide a further understanding of the invention and are incorporated in and constitute a part of this specification, illustrate embodiments of the invention and together with the example serve to explain the principles of the invention and not to limit the invention.
FIG. 1 is a flow chart of a method for implementing chip detection according to an embodiment of the present invention;
FIG. 2 is a block diagram of an apparatus for implementing chip detection according to an embodiment of the present invention;
fig. 3 is a block diagram of a PoW chip according to an exemplary embodiment of the present invention.
Detailed Description
In order to make the objects, technical solutions and advantages of the present invention more apparent, embodiments of the present invention will be described in detail below with reference to the accompanying drawings. It should be noted that the embodiments and features of the embodiments in the present application may be arbitrarily combined with each other without conflict.
The steps illustrated in the flow charts of the figures may be performed in a computer system such as a set of computer-executable instructions. Also, while a logical order is shown in the flow diagrams, in some cases, the steps shown or described may be performed in an order different than here.
Fig. 1 is a flowchart of a method for implementing chip detection according to an embodiment of the present invention, as shown in fig. 1, including:
in an illustrative example, embodiments of the invention may determine the correct rate of data reads by the first ALU based on the arithmetic logic of the first ALU.
103, determining a first ALU for workload proving operation according to the determined correct rate of the data reading of the first ALU;
the first ALU is any ALU in the PoW chip to be detected; the memory address includes: a preset number of addresses determined according to the distribution of address lines and/or data lines for transmitting data.
In an exemplary embodiment, the above processing of the embodiment of the present invention may be implemented by using a preset upper computer, a preset processor, or a preset single chip microcomputer as an execution subject.
The technical scheme of the application includes: for a proof of work (PoW) chip in a static test, acquiring first data read by a first logic calculation unit (ALU) for each ALU, the first data being read from a first memory block according to a preset memory address; determining the correct rate of the first ALU data reading according to the acquired first data read by the first ALU; determining a first ALU for the workload proving operation according to the determined correctness of the data reading of the first ALU; the first ALU is any ALU in the PoW chip to be detected; the memory address includes: a preset number of addresses determined by the distribution of address lines and/or data lines over which data is transmitted. According to the embodiment of the invention, whether the first ALU is used for the workload proving operation or not is judged by acquiring the correct rate of the data read by the first ALU through the preset number of memory addresses, so that the detection time length of the functional unit in the PoW chip is reduced; furthermore, in the embodiment of the present invention, when the accuracy of the first ALU data reading is less than or equal to the accuracy threshold, the first ALU, the first memory block, and the upper terminal and the lower terminal therebetween are detected step by step, so that the current functional unit is prevented from being affected by other functional units included in the chip.
In one illustrative example, an embodiment of the present invention determines a first ALU for a workload attestation operation, comprising:
and when the correctness of the data reading of the first ALU is greater than a preset correctness threshold, determining that the first ALU is used for the workload proving operation.
In an exemplary embodiment, the accuracy threshold in the embodiment of the present invention may be set by a person skilled in the art according to the testing time detected by the PoW chip and/or the occupation of the computational power resource by the ALU, and theoretically, the longer the testing time is, the smaller the accuracy threshold is, the shorter the testing time is, and the larger the accuracy threshold is; in an exemplary embodiment, the embodiment of the present invention sets a threshold of accuracy according to the occupancy of the ALU on the computational power resource, and when the threshold of accuracy is reasonable, determines the first ALU as being reasonable for the workload proving operation; when the accuracy threshold is too high, the ALU which occupies reasonable calculation resources is not applied; when the accuracy threshold is too low, the ALU occupying too much computational resources can be continuously applied; the embodiment of the invention adjusts the accuracy threshold value, and when the accuracy threshold value is higher, the value of the accuracy threshold value can be reduced; when the accuracy threshold is low, the value of the accuracy threshold can be improved.
In an exemplary embodiment, after determining the first ALU used for the workload proving operation, for each first ALU other than the first ALU determined for the workload proving operation, the method further comprises:
acquiring second data read by each second ALU, wherein the second data are read from the first storage block according to the corresponding memory address of each second ALU;
according to the second data read by each second ALU, respectively determining the correct rate of the data read corresponding to each second ALU;
determining a first storage block and a first lower terminal for workload proving operation according to the determined correct rate of data reading corresponding to each second ALU; wherein the second ALU comprises: ALUs except the first ALU in the PoW chip; the first lower terminal is a lower terminal connected with the first storage block in the full-connection control module of the PoW chip.
In the embodiment of the invention, for the logic calculation unit ALU in the PoW chip, the first ALU which can be used for the workload proving operation is determined firstly, after the first ALU which can be used for the workload proving operation is determined, the first storage block and the first lower terminal which can be used for the workload proving operation are further determined through the second data read by the second ALU, and through gradual detection, the mutual influence between the functional units included in the PoW chip is avoided, so that whether the first storage block and the first lower terminal can be used for the workload proving operation is determined, and the application efficiency of the operation resources of the PoW chip is improved.
In one illustrative example, embodiments of the invention determine a first memory block and a first lower terminal for a workload justification operation, comprising:
when the correctness rate of more than one second ALU data read is greater than the correctness rate threshold, the first memory block and the first lower terminal are determined to be used for the workload proving operation.
According to the embodiment of the invention, the second data reading is carried out by setting the second ALU according to the set memory address, and whether the first storage block and the first lower terminal are used for the workload proving operation or not is determined according to the accuracy of the second data, so that the application efficiency of the operation resources of the PoW chip is improved.
In an illustrative example, after determining the first memory block and the first lower terminal for the workload proving operation, when the correct rate of all the second ALU read data for each first ALU is less than or equal to the correct rate threshold, the method of the embodiment of the present invention further comprises:
acquiring third data read by the first ALU, wherein the third data are read from all second storage blocks according to a preset memory address;
according to the acquired third data read by the first ALU, the correct rate of data reading of the first ALU from each second storage block is determined respectively;
determining a first upper terminal for workload proving operation according to the determined correct rate of data reading of the first ALU from each second storage block; wherein the second memory block includes: other memory blocks except the first memory block in the PoW chip; the first upper terminal is an upper terminal connected with the first ALU in the fully-connected control module of the PoW chip.
In one illustrative example, embodiments of the present invention determine a first upper terminal for workload attestation operations, comprising:
when the correctness rate of the first ALU for data reading from more than one second memory block is greater than the correctness threshold, the first upper terminal is determined to be used for the workload proving operation.
In the embodiment of the invention, after the first storage block and the first lower terminal which can be used for workload proving operation are determined for the logic calculation unit ALU in the PoW chip, the first upper terminal is further processed, so that mutual influence among functional units contained in the PoW chip is avoided, and the application efficiency of operation resources of the PoW chip is improved by further determining whether the first upper terminal can be used for workload proving operation.
In an exemplary embodiment, when the correct rate of data reading from all the second memory blocks by the first ALU is less than or equal to the correct rate threshold, the method further includes:
it is determined that the connection between the first upper terminal and the first lower terminal is invalid.
In an illustrative example, a method of an embodiment of the present invention further includes:
respectively counting the operation success rate of the ALU to be executed for each ALU of the PoW chip in the working state;
and when the operation success rate of the ALU is less than a preset success rate threshold value, determining that the ALU is not used for the workload proving operation.
In an illustrative example, embodiments of the invention may determine whether a PoW chip is in operation based on data from an ALU performing an operation.
In an exemplary embodiment, the embodiment of the present invention may perform statistics of the success rate of the operation immediately after the PoW chip enters the operating state; in an exemplary embodiment, the embodiment of the present invention may take a preset duration as a statistical period, and count the operation success rate of the PoW chip entering the working state;
in an exemplary embodiment, the success rate threshold of the embodiment of the present invention may be set by a person skilled in the art according to the occupation of the computing power resource by the functional unit, in combination with experience; when the calculation resource occupation is not in direct proportion to the success rate or is similar to the direct proportion relation, determining that the ALU is not used for the workload proving operation; thereby avoiding the loss of computing power; for example 30%; when determining whether to use a functional unit for workload proving operation according to the computing power loss (computing power loss) caused by the functional unit, the embodiment of the present invention should theoretically reserve the functional unit for workload proving operation if the computing power loss is greater than the computing power loss caused by reserving the functional unit. If the computation power loss is less than the computation power loss caused by retaining this functional unit, then the functional unit should theoretically be determined not to be used for workload proof operations.
According to the embodiment of the invention, through static and dynamic testing methods, in static testing, the detection standard can be reduced, only the definite functional units which are not suitable for workload proving operation are detected, and the detection time of the PoW chip is reduced; the real-time detection of the PoW chip in a working state is realized in a dynamic detection mode, and the detection of a new functional unit which is not suitable for workload proving operation appears in the use process of the chip under the condition that the detection time is not increased.
The embodiment of the invention also provides a computer storage medium, wherein a computer program is stored in the computer storage medium, and when being executed by a processor, the computer program realizes the method for realizing the chip detection.
An embodiment of the present invention further provides a terminal, including: a memory and a processor, the memory having stored therein a computer program; wherein the content of the first and second substances,
the processor is configured to execute the computer program in the memory;
the computer program, when executed by a processor, implements a method of implementing chip detection as described above.
Fig. 2 is a block diagram of a device for implementing chip detection according to an embodiment of the present invention, as shown in fig. 2, including: the device comprises an acquisition unit, a correct rate determining unit and a result determining unit; wherein the content of the first and second substances,
the acquisition unit is configured to: for a workload certification PoW chip in a static test, aiming at each first logic calculation unit ALU, first data read by the first ALU are obtained, and the first data are read from a first storage block according to a preset memory address;
the unit for determining the correct rate is set as: determining the correct rate of the first ALU data reading according to the acquired first data read by the first ALU;
the determination result unit is set to: determining a first ALU for the workload proving operation according to the determined correct rate of the data reading of the first ALU;
the first ALU is any ALU in the PoW chip to be detected; the memory address includes: a preset number of addresses determined according to the distribution of address lines and/or data lines for transmitting data.
The technical scheme of the application includes: for a proof of work (PoW) chip in a static test, acquiring first data read by a first logic calculation unit (ALU) for each ALU, the first data being read from a first memory block according to a preset memory address; determining the correct rate of the first ALU data reading according to the acquired first data read by the first ALU; determining a first ALU for the workload proving operation according to the determined correct rate of the data reading of the first ALU; the first ALU is any ALU in the PoW chip to be detected; the memory address includes: a preset number of addresses determined according to the distribution of address lines and/or data lines for transmitting data. In the embodiment of the invention, whether the first ALU is used for the workload proving operation or not is judged by acquiring the accuracy of the data read by the first ALU through the preset number of memory addresses, so that the detection time of a functional unit in the PoW chip is shortened; furthermore, in the embodiment of the present invention, when the accuracy of the first ALU data reading is less than or equal to the accuracy threshold, the first ALU, the first memory block, and the upper terminal and the lower terminal therebetween are detected step by step, so that the current functional unit is prevented from being affected by other functional units included in the chip.
In an illustrative example, an embodiment of the present invention determines that the result unit is set to:
and when the accuracy of the data reading of the first ALU is greater than a preset accuracy threshold value, determining that the first ALU is used for the workload proving operation.
In an exemplary embodiment, the obtaining unit is further configured to: after the first ALU used for the workload proving operation is determined by the correct rate determining unit, for each first ALU except the first ALU determined for the workload proving operation, second data read by each second ALU is obtained, and the second data are read from the first storage block according to the corresponding memory address of each second ALU;
the determine-correct-rate unit is further arranged to: according to the second data read by each second ALU, respectively determining the correct rate of the corresponding data read by each second ALU;
the determination result unit is further configured to: determining a first memory block and a first lower terminal for a workload proving operation according to the determined correctness of the corresponding data reading of each second ALU;
wherein the second ALU comprises: ALUs except the first ALU in the PoW chip; the first lower terminal is a lower terminal connected with the first storage block in the full-connection control module of the PoW chip.
In one illustrative example, the determination result unit is configured to determine a first memory block and a first lower terminal for the workload proving operation, and includes:
when the correctness rate of more than one second ALU data read is greater than the correctness rate threshold, the first memory block and the first lower terminal are determined to be used for the workload proving operation.
In an exemplary embodiment, the obtaining unit in the embodiment of the present invention is further configured to: after a first storage block and a first lower terminal used for workload proving operation are determined, third data read by the first ALU are obtained, and the third data are read from all second storage blocks according to preset memory addresses;
the determine-correct-rate unit is further arranged to: according to the acquired third data read by the first ALU, the correct rate of data reading of the first ALU from each second storage block is determined respectively;
the determination result unit is further configured to: determining a first upper terminal for workload proving operation according to the determined correct rate of data reading of the first ALU from each second storage block;
wherein the second memory block includes: other memory blocks except the first memory block in the PoW chip; the first upper terminal is an upper terminal connected with the first ALU in the fully-connected control module of the PoW chip.
In one illustrative example, an embodiment of the present invention provides a method for determining a first upper terminal for a workload proving operation, including:
when the correctness rate of the first ALU for data reading from more than one second memory block is greater than the correctness threshold, the first upper terminal is determined to be used for the workload proving operation.
In an exemplary embodiment, the determination result unit of the embodiment of the present invention is further configured to: the determine correct rate unit determines that the connection between the first upper terminal and the first lower terminal is invalid when the determine correct rate unit determines that the correct rates of the first ALU for data reading from all the second memory blocks are less than or equal to the correct rate threshold.
In an exemplary embodiment, the unit for determining the correct rate according to the embodiment of the present invention is further configured to: respectively counting the operation success rate of the ALU to be executed for each ALU of the PoW chip in the working state;
the determination result unit is further configured to: and when the operation success rate of the ALU is less than a preset success rate threshold value, determining that the ALU is not used for the workload proving operation.
The following briefly describes the embodiments of the present invention by using application examples, which are only used to set forth the embodiments of the present invention and are not used to limit the scope of the embodiments of the present invention.
Application example
The present application example defines the detection that the ALU does not execute the operation task as static detection, and defines the detection that the ALU executes the operation task as dynamic detection. The application example detects the workload proving chip based on a static and dynamic combination mode, after the chip is started, firstly, the functional units which are not used for workload proving operation are quickly found out through a static detection method, in the process of using the PoW chip, the service conditions of the functional units are dynamically counted, and the functional units which are not used for workload proving operation and are missed to be detected due to incomplete testing are found out. Fig. 3 is a block diagram of a PoW chip according to an exemplary application of the present invention, and as shown in fig. 3, the PoW chip includes: the full-connection control unit is provided with an upper terminal and a lower terminal; after the ALU is connected with the upper terminal, the lower terminal of the full-connection control unit is connected with the storage block; it should be noted that, in the embodiment of the present invention, a storage control module is further included between the terminal and the storage block; an address line and a data line for transmitting data are included between the ALU and the memory block; the ALU is used as a calculation unit, reads data from the storage block, and obtains a corresponding operation result according to the calculation of a preset operation logic; the memory control module is used for reading data of a specified memory address from the memory block according to the execution of the ALU read data.
The application example assumes that a PoW chip comprises N ALUs, x represents the sequence number of the ALUs, the x-th ALU is recorded as ALU-x, and the value of x is 1-N; the application example assumes that a PoW chip comprises M storage blocks, y represents the sequence number of the storage blocks, the y-th storage block is recorded as a storage block y, and the value of y is 1-M; an ALU-x reads data from a predetermined memory address of a memory block y to calculate, the ALU-x inputs the memory address to an upper terminal x (the number of the upper terminal is the same as that of the ALU connected with the upper terminal), a full connection control unit judges that the address belongs to the memory block according to the memory address, for example, the memory block y belongs to, the upper terminal x and the lower terminal y are connected, and the memory address data of the memory block y is read through a memory control module y (the number of the memory block connected with the memory control module y is the same); finally, ALU-x obtains a calculation result according to the read data; the upper computer is used as an execution main body of chip detection of the application example, and can determine the accuracy of ALU-x data reading according to the arithmetic logic of the ALU;
when the accuracy of ALU-x data reading is larger than a preset accuracy threshold value, determining that ALU-x can be used for workload proving operation;
when the correctness of the ALU-x data reading is smaller than or equal to the correctness threshold, acquiring data read by the second ALU from the storage block y according to the corresponding memory address of each second ALU;
according to the obtained data read from the memory block y by each second ALU, respectively determining the correct rate of the data read corresponding to each second ALU;
when the correctness of more than one second ALU data reading is greater than the correctness threshold, determining that the storage block y and the first lower terminal can be used for workload proving operation;
wherein the second ALU comprises: ALUs other than ALU-x; the first lower terminal is a lower terminal connected with the storage block y in the fully-connected control module of the PoW chip.
When the correctness of the second ALU read data is smaller than the correctness threshold, obtaining the data read by the ALU-x from all the second storage blocks according to the preset memory address;
according to the obtained data read from the second storage blocks by the ALU-x, respectively determining the correct rate of data reading of the ALU-x from each second storage block;
when the correctness rate of the data reading of the ALU-x from the more than one second storage block is greater than the correctness rate threshold value, determining that the first upper terminal can be used for workload proving operation;
wherein the second memory block includes: other memory blocks than memory block y; the first upper terminal includes: and the upper terminal of the full connection control module is connected with the ALU-x.
And when the correct rate of data reading by the ALU-x from all the second memory blocks is less than or equal to the correct rate threshold value, determining that the connection between the first upper terminal and the first lower terminal is invalid.
When the application example is used for testing the storage block, all bytes in the storage block do not need to be tested, the preset number of addresses of the memory block are selected for data reading and writing according to the distribution of the address lines and the data lines for transmitting data, and the reading result of the whole storage block is represented by sampling data. The test time is reduced, and the influence of the measured bad blocks on the judgment of the test result is avoided; for example, a plurality of memory addresses are selected from the memory block 1, the ALU reads data on the memory addresses, if all the memory addresses are wrong, it needs to verify whether the memory block is correct, if part of the memory addresses are successful and part of the memory addresses are failed, it indicates that the ALU functional unit can be used for workload proving operation, but it needs to verify whether the memory block is correct; this application example ALU1-ALUN accesses this memory block in sequence, indicating that the memory block is available for workload proof operations if there is an ALU read that is correct, and that the memory block is problematic or that the fully connected control module is problematic if none or part of the ALU read is correct.
When the memory block can be determined to be correct, the ALU function is normal, if the read data is wrong, the connection of the current upper terminal and the current lower terminal is failed, and if the part which is correct is incorrect, the judgment needs to be carried out through a probability statistical algorithm.
The application example adjusts the accuracy parameter through probability calculation and a large number of actual tests, and balances the test time and the result accuracy. The accuracy threshold is a key parameter, and according to the characteristics of the chip, in the application example, the computing power loss caused by closing the functional unit is larger than that caused by keeping the functional unit with the problem.
The static detection in the application example is a quick detection process, and detection omission is possible, so when the chip works, the application example counts the operation success rate of the ALU, and when the operation success rate of the ALU is lower than a certain success rate threshold, the ALU is marked as unavailable for workload proving operation.
The application example detects the workload proof chip based on a static and dynamic combined method, can reduce the detection standard in the static test, only detects a clear and unavailable workload proof operation module, and reduces the chip detection time; the long-time running of the chip is utilized during dynamic testing, more accurate detection is indirectly realized, the detection quality of the PoW chip is improved under the condition that the detection time is not increased, the application of the PoW chip to computing power resources is improved, and the occupation of an ALU and a storage block which cannot be used for workload proving operation on the computing power resources is avoided.
It will be understood by those of ordinary skill in the art that all or some of the steps of the methods, systems, functional modules/units in the devices disclosed above may be implemented as software, firmware, hardware, and suitable combinations thereof. In a hardware implementation, the division between functional modules/units mentioned in the above description does not necessarily correspond to the division of physical components; for example, one physical component may have multiple functions, or one function or step may be performed by several physical components in cooperation. Some or all of the components may be implemented as software executed by a processor, such as a digital signal processor or microprocessor, or as hardware, or as an integrated circuit, such as an application specific integrated circuit. Such software may be distributed on computer readable media, which may include computer storage media (or non-transitory media) and communication media (or transitory media). The term computer storage media includes volatile and nonvolatile, removable and non-removable media implemented in any method or technology for storage of information such as computer readable instructions, data structures, program modules or other data, as is well known to those of ordinary skill in the art. Computer storage media includes, but is not limited to, RAM, ROM, EEPROM, flash memory or other memory technology, CD-ROM, Digital Versatile Disks (DVD) or other optical disk storage, magnetic cassettes, magnetic tape, magnetic disk storage or other magnetic storage devices, or any other medium which can be used to store the desired information and which can accessed by a computer. In addition, communication media typically embodies computer readable instructions, data structures, program modules or other data in a modulated data signal such as a carrier wave or other transport mechanism and includes any information delivery media as known to those skilled in the art.
Claims (11)
1. A method for realizing chip detection comprises the following steps:
for a workload certification PoW chip in a static test, aiming at each first logic calculation unit ALU, first data read by the first ALU are obtained, and the first data are read from a first storage block according to a preset memory address;
determining the correct rate of the first ALU data reading according to the acquired first data read by the first ALU;
determining a first ALU for the workload proving operation according to the determined correct rate of the data reading of the first ALU;
the first ALU is any ALU in the PoW chip to be detected; the memory address includes: a preset number of addresses determined according to the distribution of address lines and/or data lines for transmitting data.
2. The method of claim 1, wherein determining the first ALU to use for the workload attestation operation comprises:
and when the correctness of the first ALU data reading is greater than a preset correctness threshold, determining that the first ALU is used for the workload proving operation.
3. The method of claim 1, wherein after determining the first ALU for the workload proof operation, for each first ALU other than the first ALU determined for the workload proof operation, the method further comprises:
acquiring second data read by each second ALU, wherein the second data are read from the first storage block according to the corresponding memory address of each second ALU;
according to the second data read by each second ALU, respectively determining the correct rate of the data read corresponding to each second ALU;
determining a first memory block and a first lower terminal for a workload proving operation according to the determined correct rate of data reading corresponding to each of the second ALUs;
wherein the second ALU comprises: the other ALUs except the first ALU in the PoW chip; the first lower terminal is a lower terminal connected with the first storage block in the full-connection control module of the PoW chip.
4. The method of claim 3, wherein determining the first memory block and the first lower terminal for the workload attestation operation comprises:
determining that the first memory block and first lower terminal are used for a workload attestation operation when a correctness rate of one or more of the second ALU data reads is greater than the correctness rate threshold.
5. The method of claim 3, wherein after determining the first memory block and the first lower terminal for the workload justification operation, for each of the first ALUs when a correct rate of all of the second ALU read data is less than or equal to the correct rate threshold, the method further comprises:
acquiring third data read by the first ALU, wherein the third data are read from all second storage blocks according to a preset memory address;
according to the acquired third data read by the first ALU, respectively determining the correct rate of data reading of the first ALU from each second storage block;
determining a first upper terminal for workload proving operation according to the determined correct rate of data reading of the first ALU from each second storage block;
wherein the second memory block includes: storing other memory blocks in the PoW chip except the first memory block; the first upper terminal is an upper terminal connected with the first ALU in a full-connection control module of the PoW chip.
6. The method of claim 5, wherein determining the first upper terminal for the workload attestation operation comprises:
and when the correctness rate of the first ALU for data reading from more than one second storage block is greater than the correctness rate threshold value, determining that a first upper terminal is used for workload proving operation.
7. The method of claim 5 or 6, wherein after determining the first upper terminal for the workload attestation operation, when a correct rate of data reads by the first ALU from all of the second memory blocks is less than or equal to the correct rate threshold, the method further comprises:
determining that the connection between the first upper terminal and the first lower terminal is invalid.
8. The method according to any one of claims 1 to 6, further comprising:
respectively counting the operation success rate of the ALU to be executed for each ALU of the PoW chip in the working state;
and when the operation success rate of the ALU is less than a preset success rate threshold value, determining that the ALU is not used for the workload proving operation.
9. A computer storage medium having a computer program stored thereon, the computer program, when executed by a processor, implementing a method of implementing chip detection as claimed in any one of claims 1-8.
10. A terminal, comprising: a memory and a processor, the memory having a computer program stored therein; wherein the content of the first and second substances,
the processor is configured to execute the computer program in the memory;
the computer program, when executed by the processor, implements a method of implementing chip detection as claimed in any one of claims 1-8.
11. An apparatus for implementing chip detection, comprising: the device comprises an acquisition unit, a correct rate determining unit and a result determining unit; wherein the content of the first and second substances,
the acquisition unit is configured to: for a workload certification PoW chip in a static test, aiming at each first logic calculation unit ALU, first data read by the first ALU are obtained, and the first data are read from a first storage block according to a preset memory address;
the unit for determining the correct rate is set as: determining the correct rate of the first ALU data reading according to the acquired first data read by the first ALU;
the determination result unit is set to: determining a first ALU for the workload proving operation according to the determined correct rate of the data reading of the first ALU;
the first ALU is any ALU in the PoW chip to be detected; the memory address includes: a preset number of addresses determined according to the distribution of address lines and/or data lines for transmitting data.
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Citations (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN109816110A (en) * | 2019-01-24 | 2019-05-28 | 杭州嘉楠耘智信息科技有限公司 | Scrypt algorithm workload proving method and device |
| AU2020100045A4 (en) * | 2020-01-10 | 2020-02-13 | Nie, Wenchang Mr | A consortium block chain system using proof of work computing ability to realize valuable calculation |
| CN112331253A (en) * | 2020-10-30 | 2021-02-05 | 深圳市宏旺微电子有限公司 | Chip testing method, terminal and storage medium |
| CN114003544A (en) * | 2021-12-30 | 2022-02-01 | 中科声龙科技发展（北京）有限公司 | Control chip, workload proving system and transmission method |
| CN114002587A (en) * | 2021-12-30 | 2022-02-01 | 中科声龙科技发展（北京）有限公司 | Chip supporting workload proving mechanism and testing method thereof |
| CN114003552A (en) * | 2021-12-30 | 2022-02-01 | 中科声龙科技发展（北京）有限公司 | Workload proving operation method, workload proving chip and upper computer |
-
2022
- 2022-04-11 CN CN202210371014.9A patent/CN114461477B/en active Active
Patent Citations (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN109816110A (en) * | 2019-01-24 | 2019-05-28 | 杭州嘉楠耘智信息科技有限公司 | Scrypt algorithm workload proving method and device |
| AU2020100045A4 (en) * | 2020-01-10 | 2020-02-13 | Nie, Wenchang Mr | A consortium block chain system using proof of work computing ability to realize valuable calculation |
| CN112331253A (en) * | 2020-10-30 | 2021-02-05 | 深圳市宏旺微电子有限公司 | Chip testing method, terminal and storage medium |
| CN114003544A (en) * | 2021-12-30 | 2022-02-01 | 中科声龙科技发展（北京）有限公司 | Control chip, workload proving system and transmission method |
| CN114002587A (en) * | 2021-12-30 | 2022-02-01 | 中科声龙科技发展（北京）有限公司 | Chip supporting workload proving mechanism and testing method thereof |
| CN114003552A (en) * | 2021-12-30 | 2022-02-01 | 中科声龙科技发展（北京）有限公司 | Workload proving operation method, workload proving chip and upper computer |
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