CN115858172A - Processor instruction execution statistical method and device and processor system - Google Patents
Processor instruction execution statistical method and device and processor system Download PDFInfo
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- CN115858172A CN115858172A CN202211670237.1A CN202211670237A CN115858172A CN 115858172 A CN115858172 A CN 115858172A CN 202211670237 A CN202211670237 A CN 202211670237A CN 115858172 A CN115858172 A CN 115858172A
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Abstract
The invention provides a processor instruction execution statistical method, a device and a processor system, wherein the processor instruction execution statistical method is characterized in that the total number of instructions in an executable instruction set is obtained in advance, and a memory area is allocated to each instruction in the executable instruction set; when the processor executes the instructions in the executable instruction set, each memory area is used for counting the executed condition of the corresponding instruction. According to the scheme, before the processor executes the executable instruction set, a memory area with a determined storage space size is pre-allocated to each instruction in the executable instruction set by using the uniqueness of the instructions in the executable instruction set and the certainty of the total number of the instructions, and when the subsequent processor executes the instructions in the executable instruction set, the current executed instruction state information is marked to the memory area corresponding to the instruction. An exception handling mechanism is not needed, the processing flow of storage and acquisition is simplified, and the processing efficiency is improved.
Description
Technical Field
The invention relates to the technical field of computers, in particular to a processor instruction execution statistical method and device and a processor system.
Background
In computers, especially embedded systems, the computing resources are usually very limited, so there are often high efficiency requirements for computationally intensive algorithms such as image algorithms, deep learning algorithms, image codecs, and so on, and thus a programmer is required to perform deep optimization on the program. In software testing and verification, the coverage rate and hot spots of the instruction are used as important measurement indexes. The basic purpose of counting the instruction coverage rate is to find out potential missing test cases, supplement the test cases in a targeted manner, and identify unreachable waste instructions caused by requirements change and the like in the instructions, so that the overall quality of the software is guaranteed fundamentally. Generally, more than 90% of time consumption in the program is concentrated in 10% of instruction segments, so that an effective optimization method is to analyze hot spots of the instructions, optimize the time-consuming instruction segments in a targeted manner, and improve the optimization efficiency.
Currently, in the process of counting the coverage rate and hot spots of the instruction, the information of the type of the currently executed instruction is recorded. However, when the processor executes the executable instruction set, the number of instructions to be executed is unknown and uncertain, and therefore the processor cannot determine in advance the size of the memory space required for recording the information of the executed instructions. Based on this, the prior art usually allocates a very large memory space, and when the very large memory space still has a storage overflow condition, the requirement is met by timely reading data in a manner of circular coverage storage through an exception handling mechanism. However, this method not only makes the processing flow of storing and retrieving complicated or complicated, but also has low processing efficiency.
Disclosure of Invention
The invention provides a processor instruction execution statistical method and device and a processor system, which simplify the processing flow of storage and acquisition and improve the processing efficiency.
In a first aspect, the present invention provides a statistical method for processor instruction execution, where the statistical method for processor instruction execution includes: acquiring the total number of instructions in an executable instruction set of a processor; allocating a memory area for each instruction in the executable instruction set; while the processor executes the instructions in the executable instruction set, each memory area is used for counting the executed condition of the corresponding instruction.
In the above scheme, a total number of instructions in an executable instruction set is obtained in advance, and a memory area is allocated to each instruction in the executable instruction set; when the processor executes the instructions in the executable instruction set, each memory area is used for counting the executed condition of the corresponding instruction. According to the scheme, before the processor executes the executable instruction set, a memory area with a determined storage space size is pre-allocated to each instruction in the executable instruction set by using the uniqueness of the instructions in the executable instruction set and the certainty of the total number of the instructions, and when the subsequent processor executes the instructions in the executable instruction set, the current executed instruction state information is marked to the memory area corresponding to the instruction. Compared with the existing scheme, the total number of the instructions in the executable instruction set is determined, so that the total memory area allocated in advance is also determined, an overlarge memory space does not need to be allocated, and the utilization efficiency of the memory space is improved. Moreover, an exception handling mechanism is not needed, the storage and acquisition processing flow is simplified, and the processing efficiency is improved.
In one embodiment, allocating a memory region for each instruction in the set of executable instructions comprises: each instruction in the executable instruction set is allocated a memory area with one bit of memory space. When the processor executes the instructions in the executable instruction set, each memory area is used for counting the executed conditions of the corresponding instructions, and the method comprises the following steps: while the processor executes the instructions in the executable instruction set, each memory region is used for counting whether the corresponding instruction is executed. By utilizing the determined storage space, statistics of instruction coverage in the set of executable instructions can be accomplished.
In one embodiment, allocating a memory region for each instruction in the set of executable instructions comprises: each instruction in the set of executable instructions is allocated a count storage area. When the processor executes the instructions in the executable instruction set, each memory area is used for counting the executed conditions of the corresponding instructions, and the method comprises the following steps: while the processor executes the instructions in the executable instruction set, each count storage area is used for counting the number of times the corresponding instruction is executed. By allocating a counting storage area to each instruction in advance and writing the number of times that the corresponding instruction is executed in each counting storage area, the counting of the instruction hot spots in the executable instruction set is completed by using the determined storage space.
In one embodiment, allocating a memory region for each instruction in the set of executable instructions comprises: acquiring a currently and actually usable memory space of a processor; judging whether the current actually usable memory space supports allocation of a memory area for each instruction in the executable instruction set; if so, a memory region is allocated for each instruction in the set of executable instructions. The method and the device prevent the waste of computing and storing resources caused by continuous allocation and statistics when the currently and actually usable memory space does not support the allocation of a memory area for each instruction in the executable instruction set, and also avoid the occurrence of statistics errors caused by the continuous allocation and the statistics.
In a specific embodiment, allocating a memory region for each instruction in the set of executable instructions further comprises: if the current actually usable memory space does not support allocation of a memory area for each instruction in the executable instruction set, calculating the maximum number of support instructions of the current actually usable memory space supporting allocation of a memory area for each instruction; dividing the instructions in the executable instruction set into at least two groups of instructions according to the maximum number of supported instructions and the total number of the instructions in the executable instruction set, and determining the times of the processor needing to repeatedly execute the instructions in the executable instruction set, wherein the times of the processor needing to repeatedly execute the instructions in the executable instruction set correspond to the at least two groups of instructions one to one; before the processor executes the instructions in the executable instruction set each time, allocating a memory area for each instruction in a group of instructions corresponding to the time when the processor executes the instructions in the executable instruction set this time; each memory area is used for counting the executed condition of the corresponding instruction in the corresponding group of instructions when the processor executes the instructions in the executable instruction set at this time. When the currently and actually usable memory space does not support allocation of a memory area for each instruction in the executable instruction set, the processor repeatedly executes the instructions in the executable instruction set for multiple times, and only counts the executed conditions of one group of instructions during each operation, and can still complete the counting of the executed conditions of the instructions in the executable instruction set under the condition of insufficient storage resources.
In a second aspect, the present invention further provides a processor instruction execution statistics apparatus, including: the device comprises an instruction total number acquisition module, a memory allocation module and an execution information acquisition and writing module. The total number of instructions acquisition module is used for acquiring the total number of instructions in an executable instruction set of the processor; the memory allocation module is used for allocating a memory area for each instruction in the executable instruction set; the execution information acquisition writing module is used for writing the executed condition of each instruction into the corresponding memory area when the processor executes the instructions in the executable instruction set.
In the scheme, the total number of the instructions in the executable instruction set is obtained in advance through the instruction total number acquisition module, and the memory allocation module allocates a memory area for each instruction in the executable instruction set; when the processor executes the instructions in the executable instruction set, the execution information acquisition writing module writes the executed condition of each instruction into the corresponding memory area. According to the scheme, before the processor executes the executable instruction set, a memory area with a determined storage space size is pre-allocated to each instruction in the executable instruction set by using the uniqueness of the instructions in the executable instruction set and the certainty of the total number of the instructions, and when the subsequent processor executes the instructions in the executable instruction set, the current executed instruction state information is marked to the memory area corresponding to the instruction. Compared with the existing scheme, the total number of the instructions in the executable instruction set is determined, so that the total memory area allocated in advance is also determined, an overlarge memory space does not need to be allocated, and the utilization efficiency of the memory space is improved. Moreover, an exception handling mechanism is not needed, the processing flow of storage and acquisition is simplified, and the processing efficiency is improved.
In a specific embodiment, the memory allocation module allocates a storage area with one bit of storage space for each instruction in the executable instruction set. The execution information acquisition writing module is used for writing information whether each instruction is executed into a memory area corresponding to the instruction or not when the processor executes the instruction in the executable instruction set. By utilizing the determined storage space, statistics of instruction coverage in the set of executable instructions can be accomplished.
In one embodiment, the memory allocation module allocates a count storage area for each instruction in the set of executable instructions. The execution information acquisition and writing module is used for writing the executed times information of each instruction into the memory area corresponding to the instruction while the processor executes the instructions in the executable instruction set. By allocating a counting storage area to each instruction in advance and writing the number of times that the corresponding instruction is executed in each counting storage area, the counting of the instruction hot spots in the executable instruction set is completed by using the determined storage space.
In a specific embodiment, the processor instruction execution statistics apparatus further includes: the device comprises a memory space acquisition module and a judgment module. The memory space acquisition module is used for acquiring the currently and actually usable memory space of the processor. The judging module is used for judging whether the currently and actually usable memory space supports the allocation of a memory area for each instruction in the executable instruction set. The memory allocation module is used for allocating a memory area for each instruction in the executable instruction set when the judgment result of the judgment module is supported. The method and the device prevent the waste of computing and storing resources caused by continuous distribution and statistics when the currently and actually usable memory space does not support the distribution of a memory area for each instruction in an executable instruction set, and also avoid the occurrence of statistical errors caused by the continuous distribution and the statistics.
In a specific embodiment, the processor instruction execution statistics apparatus further includes: the device comprises a calculation module, an instruction grouping module and a determination module. The calculation module is configured to calculate a maximum number of support instructions that the currently and actually usable memory space supports allocation of one memory area for each instruction when the determination result of the determination module is that the memory area does not support. The instruction grouping module is used for dividing the instructions in the executable instruction set into at least two groups of instructions according to the maximum number of the supported instructions and the total number of the instructions in the executable instruction set. The determining module is used for determining the times that the processor needs to repeatedly execute the instructions in the executable instruction set; the number of times that the processor needs to repeatedly execute the instructions in the executable instruction set corresponds to at least two groups of instructions one to one. The memory allocation module is used for allocating a memory area for each instruction in a group of instructions corresponding to the current execution of the instructions in the executable instruction set by the processor before the processor executes the instructions in the executable instruction set each time. The execution information acquisition writing module is used for writing the executed condition of each instruction in a group of instructions corresponding to the execution of the instructions in the executable instruction set into the memory area corresponding to the instruction when the processor executes the instructions in the executable instruction set this time. When the currently and actually usable memory space does not support allocation of a memory area for each instruction in the executable instruction set, the processor repeatedly executes the instructions in the executable instruction set for multiple times, and only counts the executed conditions of one group of instructions during each operation, and can still complete the counting of the executed conditions of the instructions in the executable instruction set under the condition of insufficient storage resources.
In a third aspect, the present invention further provides a processor system, comprising: instruction storage module, processor and any one above-mentioned treater instruction execution statistics device. The instruction storage module is used for storing instructions in the executable instruction set; the processor includes an instruction execution module for executing instructions of the set of executable instructions. The method comprises the steps that the total number of instructions in an executable instruction set is obtained in advance through an instruction total number acquisition module, and a memory area is distributed for each instruction in the executable instruction set through a memory distribution module; and when the instruction execution module executes the instructions in the executable instruction set, the execution information acquisition writing module writes the executed condition of each instruction into the corresponding memory area. According to the scheme, before the processor executes the executable instruction set, a memory area with a determined storage space size is pre-allocated to each instruction in the executable instruction set by using the uniqueness of the instructions in the executable instruction set and the certainty of the total number of the instructions, and when the subsequent processor executes the instructions in the executable instruction set, the current executed instruction state information is marked to the memory area corresponding to the instruction. Compared with the existing scheme, the total number of the instructions in the executable instruction set is determined, so that the total memory area allocated in advance is also determined, an overlarge memory space does not need to be allocated, and the utilization efficiency of the memory space is improved. Moreover, an exception handling mechanism is not needed, the processing flow of storage and acquisition is simplified, and the processing efficiency is improved.
Drawings
FIG. 1 is a flowchart illustrating a statistical method for processor instruction execution according to an embodiment of the present invention;
FIG. 2 is a flow chart of another statistical method for processor instruction execution according to an embodiment of the present invention;
FIG. 3 is a diagram illustrating an information storage relationship of an execution instruction according to an embodiment of the present invention;
FIG. 4 is a schematic block diagram of an internal architecture of a processor according to an embodiment of the present invention;
FIG. 5 is a schematic block flow diagram of instruction execution and instruction state writing based on the processor shown in FIG. 4;
FIG. 6 is a schematic block diagram of another internal architecture of a processor according to an embodiment of the present invention;
FIG. 7 is a schematic block diagram of a flow for instruction execution and instruction state writing based on the processor shown in FIG. 6;
FIG. 8 is a flowchart of another statistical method performed by a processor according to an embodiment of the present invention;
FIG. 9 is a flowchart of another statistical method performed by a processor according to an embodiment of the present invention;
FIG. 10 is a flowchart of another statistical method performed by a processor according to an embodiment of the present invention;
FIG. 11 is a block diagram illustrating an exemplary embodiment of an apparatus for statistics of processor instruction execution;
FIG. 12 is a block diagram illustrating an alternative embodiment of an instruction execution statistics apparatus for a processor;
fig. 13 is a block diagram illustrating a processor system according to an embodiment of the present invention.
Reference numerals:
10-processor instruction execution statistical device 11-instruction total number acquisition module 12-memory allocation module
13-execution information acquisition writing module 14-memory space acquisition module 15-judgment module
16-calculation module 17-instruction grouping module 18-determination module
20-instruction storage module 30-processor 31-instruction execution module
Detailed Description
In order to make the objects, technical solutions and advantages of the embodiments of the present invention clearer, the technical solutions in the embodiments of the present invention will be clearly and completely described below with reference to the drawings in the embodiments of the present invention, and it is obvious that the described embodiments are only a part of the embodiments of the present invention, and not all of the embodiments. All other embodiments, which can be derived by a person skilled in the art from the embodiments given herein without making any creative effort, shall fall within the protection scope of the present invention.
To facilitate understanding of the statistical method for processor instruction execution provided by the embodiment of the present invention, an application scenario of the statistical method for processor instruction execution provided by the embodiment of the present invention is first described below, where the statistical method for processor instruction execution is applied in a process of testing a processor instruction. It should be construed that the processor therein may be a processor executing any type of algorithm, for example, the algorithm may be a computationally intensive algorithm of an image algorithm, a deep learning algorithm, an image codec, and so forth. The statistical method for the processor instruction execution is described in detail below with reference to the accompanying drawings.
Referring to fig. 1, an embodiment of the invention provides a statistical method for processor instruction execution, including:
step10: acquiring the total number of instructions in an executable instruction set of a processor;
step20: allocating a memory area for each instruction in the executable instruction set;
step30: while the processor executes the instructions in the executable instruction set, each memory area is used for counting the executed condition of the corresponding instruction.
In the scheme, a memory area is allocated to each instruction in the executable instruction set by acquiring the total number of the instructions in the executable instruction set in advance; when the processor executes the instructions in the executable instruction set, each memory area is used for counting the executed condition of the corresponding instruction. According to the scheme, before the processor executes the executable instruction set, a memory area with a determined storage space size is pre-allocated to each instruction in the executable instruction set by using the uniqueness of the instructions in the executable instruction set and the certainty of the total number of the instructions, and when the subsequent processor executes the instructions in the executable instruction set, the current executed instruction state information is marked to the memory area corresponding to the instruction. Compared with the existing scheme, the total number of the instructions in the executable instruction set is determined, so that the total memory area allocated in advance is also determined, an overlarge memory space does not need to be allocated, and the utilization efficiency of the memory space is improved. Moreover, an exception handling mechanism is not needed, the processing flow of storage and acquisition is simplified, and the processing efficiency is improved. The above steps will be described in detail with reference to the accompanying drawings.
First, as shown in FIG. 1, the total number of instructions in the processor's executable instruction set is obtained. The executable instruction set comprises a plurality of non-repetitive instructions, the instructions form a program, and the program can be a program which is designed to be tested and also can be a program to be tested which needs to be repaired when errors are found in the running process. As shown in fig. 3, 4 and 6, the total number of instructions in the executable instruction set after the program compilation is completed is determined, and if the total number of instructions in the executable instruction set is T, T is a positive integer. And each instruction in the executable instruction set has a unique address, and can be managed subsequently according to the address information of the instruction.
Next, with continued reference to FIG. 1, a memory region is allocated for each instruction in the set of executable instructions. When a memory region is allocated to each instruction in the executable instruction set, different memory regions may be allocated to each instruction according to different statistical instruction execution conditions. When the total number of instructions in the executable instruction set is T, T memory areas need to be allocated in advance, and each memory area corresponds to one instruction in the executable instruction set.
For example, when counting instruction coverage, i.e. counting whether each instruction in the executable instruction set is outdated or not executed, each instruction in the executable instruction set may be allocated a storage area with one bit of storage space. Illustratively, each instruction may be assigned a bit in a register. Whether the instruction corresponding to the storage area is executed is indicated by writing binary '0' and '1' in the storage area of the one bit. For example, when the binary "0" is written into the one-bit storage area, it may indicate that the instruction corresponding to the one-bit storage area has not been executed; when the binary "1" is written into the one-bit storage area, it can indicate that the instruction corresponding to the one-bit storage area is executed. Or the reverse may also be used.
In addition, when the statistics instruction hot spot is found, that is, when the statistics instruction hot spot counts the frequency of executing each instruction in the executable instruction set, each instruction in the executable instruction set may be allocated a count storage area. It is to be explained that the count storage area integrates a count and storage area. Illustratively, the count storage area may be a register integrated with the count function. When an instruction in the instruction set is executed once, the instruction is written into the counting storage area corresponding to the instruction once, and the counting storage area can accumulate the count so as to count the executed frequency of the instruction.
Next, with continued reference to fig. 1, while the processor executes the instructions in the executable instruction set, each memory area is used for counting the executed conditions of the corresponding instructions. As described above, when the counted instructions are executed differently, the specific information and manner written in each memory area are also different.
For example, when each instruction in the executable instruction set is allocated a storage area with a storage space of one bit, the processor executes the instruction in the executable instruction set, and each memory area is used for counting whether the corresponding instruction is executed. By utilizing the determined storage space, statistics of instruction coverage in the set of executable instructions can be accomplished. When each instruction in the executable instruction set is allocated with a counting storage area, the processor executes the instructions in the executable instruction set, and each counting storage area is used for counting the number of times that the corresponding instruction is executed. By allocating a counting storage area to each instruction in advance and writing the number of times that the corresponding instruction is executed in each counting storage area, the statistics of the instruction hot spots in the executable instruction set is completed by using the determined storage space.
Referring to fig. 3, 4 and 5, during execution of the instructions in the executable instruction set, the processor may execute only a portion of the instructions in the executable instruction set, but a portion of the instructions in the executable instruction set may be executed multiple times by the processor. As shown in FIG. 3, assume that the total number of times the processor executes instructions in the set of executable instructions is R, but R is a value that cannot be determined in advance. The relationship of R to T may be greater than, less than, or equal to. During execution of the instructions in the executable instruction set by the processor, the processor fetches instructions from the instructions in the executable instruction set, decodes the instructions, and executes the instructions. .
When the executed condition information of each instruction in the executable instruction set is recorded in the corresponding memory area, as shown in fig. 3, 4 and 5, the processor may record the state of the instruction currently executed by the processor through the memory base address, the executable instruction base address and the address query module, and write the recorded state into the memory area corresponding to the currently executed instruction for management, so as to ensure that the executed condition information of each instruction in the executable instruction set is recorded in the specified memory area.
The following describes an exemplary general flow of execution statistics for processor instructions, with reference to fig. 4, 5, and 8.
Before the program is run, namely the instructions in the executable instruction set are run, the memory allocation and storage function configuration is carried out, and then the program is run. Specifically, the total number of instructions in the executable instruction set of the program may be determined according to the program to be run. According to the total number of the instructions in the executable instruction set, the size of the memory space occupied by the mark required to be recorded when each instruction is executed can be determined, and the total memory space required by recording the executed condition information of the instructions when the current program is executed can be determined. And according to the storage space required by the recording of the required statistical executed situation information, allocating a memory area to each instruction in the executable instruction set, and ensuring that the allocated memory area can be more than or equal to the storage space required by the recording of the executed situation information of the instruction. And establishing a corresponding relation between the processor and the memory space according to the configuration required by the processor operation instruction storage module. And configuring the allocated memory base to a memory base address register of the processor, and establishing the connection between the processor and the allocated memory. And configuring the instruction base address of the program to an instruction base address register of the processor for the processor to process and calculate the address offset of the currently executed instruction.
In the process of running the program, acquiring instruction information currently executed by the processor, and writing the instruction information into a corresponding memory area. In the process, the processor analyzes the corresponding memory address of the currently executed instruction. Specifically, before executing the instruction, acquiring a PC value of the current execution instruction; then, according to the PC value of the current execution instruction and the configured instruction base address register, calculating the address offset of the current execution instruction; and then, inquiring the corresponding position of the current execution instruction in the allocated memory area from the memory through the address offset of the current execution instruction and the configured memory base address register. And then, the processor writes the executed condition information of the currently executed instruction into the memory area corresponding to the instruction. After the program is executed, the executed condition information of each instruction in the T instructions in the executable instruction set is recorded in the T memory areas respectively.
And then, the executed condition information of the instruction can be obtained by reading the T memory areas. And counting the instruction coverage rate, and analyzing the total number of executed instructions and the ratio of the total number of the instructions in the executable instruction set to obtain the instruction coverage rate.
In addition, another internal structure of a processor and a method for collecting the execution condition of an instruction are shown in fig. 6 and 7. At this time, the processor does not include an address query module. Instead, the following manner is adopted to collect the instruction executed condition information. First, based on the value of the PC of the currently executing instruction, the address of the currently executing instruction may be determined (taking the processor as a three-stage pipeline of a 32-bit fixed length instruction set for example, the execution address is equal to the current PC value minus 8); then, the relative offset address of the current execution instruction can be obtained through the address of the current execution instruction and the base address of the executable instruction; and then, obtaining the instruction execution state information through the offset address and the executable base address of the currently executed instruction, and recording the instruction execution state information into the corresponding memory area.
As shown in fig. 9, after the executed instruction condition information stored in the memory area corresponding to each instruction in the executable instruction set is read, the executed instruction may be parsed to obtain an executed instruction set. Besides coverage rate statistics is carried out through the total number of the instructions in the executable instruction set of the executed instruction set and the known program, after the information of the executed condition of the corresponding instructions stored in the memory area corresponding to each instruction in the executable instruction set is read, the unexecuted instructions are analyzed to obtain the unexecuted instruction set, and the unexecuted program data are reversely generated through the unexecuted instruction set and are analyzed by development and verification personnel. The coverage rate of the unexecuted instructions can be counted according to the total number of the unexecuted instructions and the known executable instructions. In addition, reverse statistics of the execution coverage can also be performed by the non-execution coverage.
In addition, as shown in fig. 2, when a memory area is allocated to each instruction in the executable instruction set, a currently and actually usable memory space of the processor may also be obtained first; then judging whether the currently and actually usable memory space supports allocation of a memory area for each instruction in the executable instruction set; and if the judgment result is that the currently actually usable memory space supports allocation of a memory area for each instruction in the executable instruction set, allocating a memory area for each instruction in the executable instruction set. The method and the device prevent the waste of computing and storing resources caused by continuous allocation and statistics when the currently and actually usable memory space does not support the allocation of a memory area for each instruction in the executable instruction set, and also avoid the occurrence of statistics errors caused by the continuous allocation and the statistics.
It should be explained that, when determining whether the currently actually usable memory space supports allocating a memory region for each instruction in the executable instruction set, the main determination is based on whether the currently actually usable memory space can provide enough memory space to satisfy the requirement of allocating a memory region for each instruction in the executable instruction set when allocating a memory region for each instruction in the executable instruction set. That is, when a memory region is allocated to each instruction in the executable instruction set, whether the total storage space of the required memory region is smaller than or equal to the currently actually usable memory space is determined. If the total storage space of the required memory area is less than or equal to the current actually usable memory space, the current actually usable memory space supports allocation of a memory area for each instruction in the executable instruction set; otherwise, it indicates that the currently actually usable memory space does not support allocation of a memory region for each instruction in the executable instruction set.
With continued reference to FIG. 2, if the result of the determination is: and if the currently and actually usable memory space does not support allocation of a memory region for each instruction in the executable instruction set, calculating the maximum number of support instructions of the currently and actually usable memory space supporting allocation of a memory region for each instruction. Specifically, when allocating a memory area to each instruction, it needs to be calculated how many instructions can be allocated with the currently and actually usable memory space at most. And then, dividing the instructions in the executable instruction set into at least two groups of instructions according to the maximum supported instruction number and the total number of the instructions in the executable instruction set, and determining the times of the processor needing to repeatedly execute the instructions in the executable instruction set, wherein the times of the processor needing to repeatedly execute the instructions in the executable instruction set correspond to the at least two groups of instructions one by one. I.e., the number of instruction sets into which the instructions in the executable instruction set are divided is equal to the number of times the processor needs to repeatedly execute the instructions in the executable instruction set. Subsequently, before the processor executes the instructions in the executable instruction set each time, it is necessary to allocate a memory area for each instruction in a group of instructions corresponding to the time when the processor executes the instructions in the executable instruction set this time. Each memory area is used for counting the executed condition of the corresponding instruction in the corresponding group of instructions when the processor executes the instructions in the executable instruction set at this time. After the processor completes the execution of the instructions in the executable instruction set, before the instructions in the executable instruction set are executed repeatedly for the next time, the executed condition information of each instruction in the group of instructions obtained after the execution is read, each storage area allocated for the current time is emptied, then, a memory area is allocated to another group of instructions corresponding to the next time when the instructions in the executable instruction set are executed repeatedly in the above mode, and the execution is repeated. After repeating the above steps for multiple times, the segment statistics completes the statistics of the executed conditions of all the instructions in the executable instruction set. When the currently actually usable memory space does not support the allocation of one memory area for each instruction in the executable instruction set, the processor repeatedly executes the instructions in the executable instruction set for multiple times, counts the executed conditions of only one group of instructions in each running, and can still complete the counting of the executed conditions of the instructions in the executable instruction set under the condition of insufficient storage resources.
For example, the total number of instructions in the executable instruction set of a program T =100, the maximum number of supported instructions that the currently actually usable memory space supports to allocate a memory region for each instruction is 30, and then the instructions in the executable instruction set are divided into the instructions according to the maximum number of supported instructions and the total number of instructions in the executable instruction set
Are combined withIt is determined that the processor needs to repeatedly execute the instructions in the executable instruction set four times, i.e., the program needs to be run 4 times, to complete the recording of the executed instances of all the instructions in the executable instruction set.
Referring to fig. 10, a flow chart of counting instruction coverage rate by multiple execution segments is shown, in which the difference from fig. 8 is mainly that a step of grouping and segmenting an executable instruction set according to the size of the currently actually usable memory space is added before the program is executed. Then, before each program is run, a memory area needs to be allocated to each instruction in the corresponding group of instructions in the currently actually usable memory space. After the program is run this time, the information of the executed instruction conditions stored in the memory area allocated in the corresponding group of instructions needs to be read out in time, then the allocated memory area this time is emptied, one memory area is allocated again to each instruction in a group of instructions corresponding to the next execution, and then the executable instruction set is executed repeatedly until the statistics of the instruction execution conditions of all groups of instructions is completed. And then merging and analyzing data of the executed situation information of the instruction read after each operation, and counting the instruction coverage rate. It should be appreciated that the method is not limited to statistics of instruction coverage, but can also be applied to statistics of instruction hot spots.
In the various embodiments described above, a memory area is allocated to each instruction in the executable instruction set by obtaining the total number of instructions in the executable instruction set in advance; when the processor executes the instructions in the executable instruction set, each memory area is used for counting the executed condition of the corresponding instruction. According to the scheme, before the processor executes the executable instruction set, a memory area with a determined storage space size is pre-allocated to each instruction in the executable instruction set by using the uniqueness of the instructions in the executable instruction set and the certainty of the total number of the instructions, and when the subsequent processor executes the instructions in the executable instruction set, the current executed instruction state information is marked to the memory area corresponding to the instruction. Compared with the existing scheme, the total number of the instructions in the executable instruction set is determined, so that the total memory area allocated in advance is also determined, an overlarge memory space does not need to be allocated, and the utilization efficiency of the memory space is improved. Moreover, an exception handling mechanism is not needed, the processing flow of storage and acquisition is simplified, and the processing efficiency is improved.
In addition, an embodiment of the present invention further provides a processor instruction execution statistics apparatus, and referring to fig. 11, the processor instruction execution statistics apparatus includes: the system comprises an instruction total number acquisition module 11, a memory allocation module 12 and an execution information acquisition writing module 13. The total number of instructions acquisition module 11 is configured to acquire a total number of instructions in an executable instruction set of the processor; the memory allocation module 12 is configured to allocate a memory area for each instruction in the executable instruction set; the execution information acquiring and writing module 13 is configured to write the executed condition of each instruction into the corresponding memory area while the processor executes the instructions in the executable instruction set.
In the above scheme, the total number of instructions in the executable instruction set is obtained in advance by the instruction total number acquisition module 11, and a memory area is allocated to each instruction in the executable instruction set by the memory allocation module 12; while the processor executes the instructions in the executable instruction set, the execution information acquisition writing module 13 writes the executed condition of each instruction into the corresponding memory area. According to the scheme, before the processor executes the executable instruction set, a memory area with a certain storage space size is pre-allocated to each instruction in the executable instruction set by using the uniqueness of the instructions in the executable instruction set and the certainty of the total number of the instructions, and when the subsequent processor executes the instructions in the executable instruction set, the state information of the currently executed instructions is marked to the memory area corresponding to the instructions. Compared with the existing scheme, the total number of the instructions in the executable instruction set is determined, so that the total memory area allocated in advance is also determined, an overlarge memory space does not need to be allocated, and the utilization efficiency of the memory space is improved. Moreover, an exception handling mechanism is not needed, the processing flow of storage and acquisition is simplified, and the processing efficiency is improved.
The memory allocation module 12 may allocate a storage space as a storage area of one bit for each instruction in the executable instruction set. At this time, the execution information acquiring and writing module 13 is configured to write information indicating whether each instruction has been executed into a memory area corresponding to the instruction while the processor executes the instruction in the executable instruction set. By utilizing the determined storage space, statistics of instruction coverage in the set of executable instructions can be accomplished.
In addition, the memory allocation module 12 may allocate a count storage area for each instruction in the executable instruction set. At this time, the execution information acquiring and writing module 13 is configured to write the information of the number of times that each instruction has been executed into the memory area corresponding to the instruction while the processor executes the instruction in the executable instruction set. By allocating a counting storage area to each instruction in advance and writing the number of times that the corresponding instruction is executed in each counting storage area, the counting of the instruction hot spots in the executable instruction set is completed by using the determined storage space.
Still referring to fig. 12, the processor instruction execution statistics apparatus may further include: a memory space acquisition module 14 and a judgment module 15. The memory space acquisition module 14 is configured to acquire a currently and actually usable memory space of the processor. The determining module 15 is configured to determine whether the currently and actually usable memory space supports allocating a memory area for each instruction in the executable instruction set. The memory allocation module 14 is configured to allocate a memory area for each instruction in the executable instruction set when the determination result of the determination module is supported. The method and the device prevent the waste of computing and storing resources caused by continuous allocation and statistics when the currently and actually usable memory space does not support the allocation of a memory area for each instruction in the executable instruction set, and also avoid the occurrence of statistics errors caused by the continuous allocation and the statistics.
As shown in fig. 12, the processor instruction execution statistics apparatus may further include: a calculation module 16, an instruction grouping module 17 and a determination module 18. The calculating module 16 is configured to calculate a maximum number of support instructions that the currently and actually usable memory space supports allocating a memory area to each instruction when the determination result of the determining module is that the memory area is not supported. The instruction grouping module 17 is configured to divide the instructions in the executable instruction set into at least two groups of instructions according to the maximum number of supported instructions and the total number of instructions in the executable instruction set. The determining module 18 is used for determining the number of times the processor needs to repeatedly execute the instructions in the executable instruction set; the processor needs to repeatedly execute the times of the instructions in the executable instruction set, and the times correspond to at least two groups of instructions one by one. The memory allocation module 12 is configured to allocate a memory area for each instruction in a group of instructions corresponding to the current time when the processor executes the instructions in the executable instruction set, before the processor executes the instructions in the executable instruction set each time. The execution information acquiring and writing module 13 is configured to, when the processor executes an instruction in the executable instruction set this time, write an executed condition of each instruction in a group of instructions corresponding to the execution of the instruction in the executable instruction set into a memory area corresponding to the instruction. When the currently and actually usable memory space does not support allocation of a memory area for each instruction in the executable instruction set, the processor repeatedly executes the instructions in the executable instruction set for multiple times, and only counts the executed conditions of one group of instructions during each operation, and can still complete the counting of the executed conditions of the instructions in the executable instruction set under the condition of insufficient storage resources.
It should be explained that each of the above-mentioned total instruction number collecting module 11, memory allocating module 12, execution information collecting and writing module 13, memory space collecting module 14, judging module 15, calculating module 16, instruction grouping module 17 and determining module 18 is a functional module, and the functional module not only includes necessary hardware for implementing corresponding functions, but also includes firmware embedded in the hardware thereof to complete corresponding functions.
In addition, an embodiment of the present invention further provides a processor, and with reference to fig. 11 to 13, the processor system includes: instruction storage module 20, processor 30, and any of the above processor instruction execution statistics apparatus 10. Wherein, the instruction storage module 20 is used for storing the instructions in the executable instruction set; the processor 30 includes an instruction execution module 31, and the instruction execution module 31 is configured to execute instructions in an executable instruction set. The total number of the instructions in the executable instruction set is obtained in advance through an instruction total number acquisition module 11, and a memory area is allocated to each instruction in the executable instruction set through a memory allocation module 12; while the instruction execution module 31 executes the instructions in the executable instruction set, the execution information acquisition and writing module 13 writes the executed condition of each instruction into the corresponding memory area. According to the scheme of the application, before the processor 30 executes the executable instruction set, a memory area with a determined storage space size is pre-allocated to each instruction in the executable instruction set by using the uniqueness of the instructions in the executable instruction set and the certainty of the total number of the instructions, and when the subsequent processor 30 executes the instructions in the executable instruction set, the currently executed instruction state information is marked to the memory area corresponding to the instruction. Compared with the existing scheme, the total number of the instructions in the executable instruction set is determined, so that the total memory area allocated in advance is also determined, an overlarge memory space does not need to be allocated, and the utilization efficiency of the memory space is improved. Moreover, an exception handling mechanism is not needed, the processing flow of storage and acquisition is simplified, and the processing efficiency is improved.
It should be noted that the instruction storage module 20 and the instruction execution module 31 are also a functional module, and the functional module includes not only the necessary hardware for implementing the corresponding functions, but also firmware embedded in the hardware thereof to implement the corresponding functions.
The above description is only for the specific embodiment of the present invention, but the scope of the present invention is not limited thereto, and any changes or substitutions that can be easily conceived by those skilled in the art within the technical scope of the present invention are included in the scope of the present invention. Therefore, the protection scope of the present invention shall be subject to the protection scope of the claims.
Claims (11)
1. A statistical method of processor instruction execution, comprising:
acquiring the total number of instructions in an executable instruction set of a processor;
allocating a memory area for each instruction in the executable instruction set;
and when the processor executes the instructions in the executable instruction set, each memory area is used for counting the executed condition of the corresponding instruction.
2. The statistical method of processor instruction execution of claim 1, wherein said allocating a memory region for each instruction in the set of executable instructions comprises: allocating a storage space as a storage area with one bit for each instruction in the executable instruction set;
when the processor executes the instructions in the executable instruction set, each memory area is used for counting the executed conditions of the corresponding instructions, and the method comprises the following steps: while the processor executes the instructions in the executable instruction set, each memory area is used for counting whether the corresponding instruction is executed.
3. The statistical method of processor instruction execution of claim 1, wherein said allocating a memory region for each instruction in the set of executable instructions comprises: allocating a count storage area for each instruction in the set of executable instructions;
when the processor executes the instructions in the executable instruction set, each memory area is used for counting the executed conditions of the corresponding instructions, and the method comprises the following steps: and when the processor executes the instructions in the executable instruction set, each counting storage area is used for counting the number of times of executing the corresponding instruction.
4. The statistical method of processor instruction execution of claim 1, wherein said allocating a memory region for each instruction in the set of executable instructions comprises:
acquiring a currently and actually usable memory space of the processor;
judging whether the current actually usable memory space supports allocation of a memory area for each instruction in the executable instruction set;
if so, allocating a memory region for each instruction in the executable instruction set.
5. The statistical method of processor instruction execution of claim 4, wherein said allocating a memory region for each instruction in the set of executable instructions further comprises:
if the current actually usable memory space does not support allocation of a memory area for each instruction in the executable instruction set, calculating the maximum number of support instructions of the current actually usable memory space supporting allocation of a memory area for each instruction;
dividing the instructions in the executable instruction set into at least two groups of instructions according to the maximum number of the supported instructions and the total number of the instructions in the executable instruction set, and determining the times that the processor needs to repeatedly execute the instructions in the executable instruction set; wherein the processor is required to repeat the execution times of the instructions in the executable instruction set, corresponding to the at least two groups of instructions one to one;
before the processor executes the instructions in the executable instruction set each time, allocating a memory area for each instruction in a group of instructions corresponding to the time when the processor executes the instructions in the executable instruction set this time; each memory area is used for counting the executed condition of a corresponding instruction in a group of instructions corresponding to the memory area when the processor executes the instructions in the executable instruction set this time.
6. A processor instruction execution statistics apparatus, comprising:
the total number of the instructions is acquired by the total number acquisition module, and the total number of the instructions in the executable instruction set of the processor is acquired;
a memory allocation module, configured to allocate a memory area for each instruction in the executable instruction set;
and the execution information acquisition and writing module is used for writing the executed condition of each instruction into the corresponding memory area while the processor executes the instructions in the executable instruction set.
7. The processor instruction execution statistics apparatus of claim 6, wherein the memory allocation module allocates a storage space for each instruction in the executable instruction set as a storage area of one bit;
the execution information acquisition writing module is used for writing information whether each instruction is executed into a memory area corresponding to the instruction or not while the processor executes the instructions in the executable instruction set.
8. The processor instruction execution statistics apparatus of claim 6, wherein the memory allocation module allocates a count storage area for each instruction in the set of executable instructions;
the execution information acquisition and writing module is used for writing the executed times information of each instruction into the memory area corresponding to the instruction while the processor executes the instructions in the executable instruction set.
9. The processor instruction execution statistics apparatus of claim 6, further comprising:
the memory space acquisition module is used for acquiring the currently and actually usable memory space of the processor;
the judging module is used for judging whether the currently and actually usable memory space supports the allocation of a memory area for each instruction in the executable instruction set;
and the memory allocation module is used for allocating a memory area for each instruction in the executable instruction set when the judgment result of the judgment module is support.
10. The processor instruction execution statistics apparatus of claim 9, further comprising:
the calculation module is used for calculating the maximum number of the support instructions of a memory area allocated to each instruction by the currently and actually usable memory space support when the judgment result of the judgment module is that the memory area is not supported;
the instruction grouping module is used for dividing the instructions in the executable instruction set into at least two groups of instructions according to the maximum number of the supported instructions and the total number of the instructions in the executable instruction set;
a determining module for determining a number of times the processor needs to repeatedly execute instructions in the set of executable instructions; wherein the processor is required to repeat the execution times of the instructions in the executable instruction set, corresponding to the at least two groups of instructions one to one;
the memory allocation module is configured to allocate a memory area for each instruction in a group of instructions corresponding to the current execution of the instructions in the executable instruction set by the processor before the processor executes the instructions in the executable instruction set each time; the execution information acquisition writing module is used for writing the executed condition of each instruction in a group of instructions corresponding to the execution of the instructions in the executable instruction set into the memory area corresponding to the instruction when the processor executes the instructions in the executable instruction set this time.
11. A processor system, comprising:
the instruction storage module is used for storing instructions in the executable instruction set;
a processor having an instruction execution module therein for executing instructions of the set of executable instructions;
processor instruction execution statistics apparatus as claimed in any one of claims 6 to 10.
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| CN116431220A (en) * | 2023-06-14 | 2023-07-14 | 青岛鑫晟汇科技有限公司 | Multi-system architecture intercommunication system based on data distributed instruction set |
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| Publication number | Priority date | Publication date | Assignee | Title |
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| CN116431220A (en) * | 2023-06-14 | 2023-07-14 | 青岛鑫晟汇科技有限公司 | Multi-system architecture intercommunication system based on data distributed instruction set |
| CN116431220B (en) * | 2023-06-14 | 2023-08-18 | 青岛鑫晟汇科技有限公司 | Multi-system architecture intercommunication system based on data distributed instruction set |
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