JPS5883377A - Buffer memory control system - Google Patents

Abstract

PURPOSE:To increase the hit rate to a program and to optimize main storage area allocation dynamically by measuring the use frequency and hit rate of every segment, and altering the allocation of a main storage area according to the measured results. CONSTITUTION:An address register 1 is equipped with a block number specification part 11 stored with keys for retrieving whether a reference block resides in a buffer memory 6 or not, a set number specification part 12, and an in-block relative address specification part 13. Then, the storage area in a main storage device 7 is divided into segments, and the storage area in the main storage device 7 are allocated to the respective segments; and a CPU measures reference frequencies and hit rates corresponding to the segments, and the allocation of the storage area of the main storage 7 to the segments is altered dynamically according to the measured results, the kind of the program, or the both.

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a buffer memory control method that improves the rehit rate by dividing a storage area into a plurality of segments.

As one of the measures to improve the processing speed of a computer, it has become common practice to install a high-speed buffer memory between the arithmetic control section of the central processing unit and the main storage device. When data referenced by the arithmetic unit exists in the memory on the main memory, the contents of a storage area of a predetermined size (pages to blocks, etc.) on the main memory containing the memory are transferred and stored in the buffer memory. Thereafter, as long as this content exists in the Pacifier memory, data is referenced from the high-speed buffer memory, and when there is no free space on the buffer memory, blocks etc. are replaced from the main memory.

The probability (hit rate) that a referenced page exists on the buffer memory is determined by managing this block replacement. Conventionally, LRU (L@ast Rec@ ntly Use
d) method and FIFO (First In First
Out ) method is used.

In the buffer system, the area on the main memory used (referenced) by the program to be executed has locality, and when executing a certain section of the program, a large number of discrete areas are used (referenced). It is based on the assumption that it will not. However, for some types of programs, such as programs incorporated into computer control systems, this locality is not guaranteed and the hit rate decreases for the following reasons. First, in realizing real-time functions, the service routine of a control program located in an area separate from the program to be executed is frequently called. Second: In achieving high responsiveness,
Many of the subroutines that perform basic process input/output and man-machine interface processing are main memory resident routines located in an area separate from the executing program, and are called frequently. Third, in order to maintain responsiveness, a portion of the data file resides in main memory, but this data file not only resides in an area separate from the program, but is generally There are times when multiple data files are randomly referenced.

As described above, for programs of computer control systems where locality is not so guaranteed, the hit rate cannot be expected to be improved much by the conventional patch/file memory control system.

SUMMARY OF THE INVENTION The present invention has been made in view of the above-mentioned conventional problems, and an object of the present invention is to provide a buffer error control method that can improve the hit rate even for programs whose locality is not so guaranteed. .

The purpose of the present invention as described above is to divide a storage area on a buffer memory into a plurality of segments, allocate a storage area on a main storage device to each segment, measure the reference frequency or hit rate for each segment, This is realized by the control method of the present invention, which dynamically changes the allocation of the O storage area in the main memory to the above-mentioned instruction segment according to the performance measurement result, the type of program, or both.

The details of the present invention will be explained below with reference to Examples.

A buffer memory system applying an embodiment of the present invention,
An example of the configuration of the first WAK is shown below. The configuration in the figure exemplifies a case where a set associative method is adopted as a mapping method between the main storage device and the buffer memory. 1 is an address register that holds the main memory address referenced by the arithmetic control WAK of the central processing unit, 2 is a segment number converter, 3 is a comparator, 4 is a buffer memory index array, 5 is a counter, and 6 is a buffer memory ,7
is the main memory. Buffer memory 6, etc. size 4
The index array 4 and counter 6 are divided into four segments 4-1 to 4-4, 5-1 to 5-4. It is divided into.

One address register company stores a main memory address (which may be a logical address or a physical address), and one company uses a register company to search whether a reference block exists on the buffer memory 6, corresponding to the illustrated set associative method. The block number designating part 11 stores a block number serving as a second key, a set number designation part ν stores a set number, and an intra-block relative address designation part n stores an intra-block relative address. Block number specification section 1
This is used to specify the segment specification register for several bits from the beginning of 1, and the segment specification registers 21, 22.2 in the segment number converter 2 depending on the contents.
3...11nC) Any one is selected. The segment designation registers 21 to 2n are provided corresponding to the areas on the main memory that are divided according to the method of the present invention. Second, its index array 4C) ill of four segment numbers
Stored. Each register 21~! The contents of Otori O can be read and written by the program, as shown by the arrow thorns. Segment designation register 21~! according to the register designation bit placed at the beginning of block number designation section U in address register 1! When any one of n is specified, one of the segments of index array 4 whose segment number is stored in that register is specified. The segment designated as 5K in this way is simultaneously assigned the set number designated TEA in the address register l.
From each of the block number storage sections 41 that exist in the set (column) designated by K, the number of block groups (rows) is equal to the number of comparators 3 provided corresponding to these storage sections.
Transfer the fake 4-tsuku number to.

In FIG. 1, only the ill comparator 3 is illustrated on the illustrated tube. On the other hand, the comparator 3 provided corresponding to the block group is supplied with the block number specified in the address register month and the main memory address (block number) in parallel, and compared with the contents of the index array 4, It is checked whether the contents of the main memory address referenced by the arithmetic control unit of the processing device exist on the buffer memory 6 or not.

As a result, there is a matching block number storage section 41, and the block number storage section 4 in the rounding and index array 4 is 8 and the arrangement within each segment is the same.
1 K corresponding reference block 61 in buffer memory 6
The location of address register 1 is determined uniquely, and address register 1
Access to the reference memory area configuration becomes possible based on the contents of the intra-block relative addressing 1fIS13. In this case, the access number counter in the counter 5 provided for each segment of the buffer memory 6 is incremented.

If there is no comparison by the comparator 3, it is found that the contents of the referenced main memory address do not exist on the buffer memory 6. In this case, the above-mentioned LRU method or F
According to the IFO method or other appropriate block replacement management method, the brick to be replaced is determined from among the blocks/groups of the same segment and the same set on the buffer memory 6, and the referenced block in the main storage device T, e.g. n is transferred to the buffer memory 6, and the brick number of the main memory address is written into the index array 4. At the same time, the access count counter &O count >') value of counter 5 corresponding to this segment is added by 1 count, but since the hit count counter O count value remains at its current value, the TS F rate is The decline is recorded. An arrow 51 inside the counter 5 indicates that the contents of this counter can be read and written by the program 2.

FIG. 2 shows segment designation registers 21, 22, 23, . . . 2 in the segment number converter 2 shown in FIG.
Contents of n and 4 segments 4 of index array 4
-1°4-2, 4-3 and 4-4 are illustrated. The solid arrow indicates that the number of segment 4-1 is written in the segment specification registers 21, 22, and n, and the number of segment 4-2 is written in the segment specification register. Similarly, segment 4-1 is stored in each segment specification register.
It is illustrated that any one number from 4-4 to 4-4 is written. As described above, the segment designation registers 21 to 2n are provided corresponding to nine divided memory areas on the main memory, respectively. In FIG. 1, a central processing unit (not shown) calculates the hit rate for each segment by reading the count values of the access counter 52 and the hit counter provided for each segment using a program. If the hit rate of segment 4-1 is lower than the hit rate of segment 4-2, 1 rewrites the contents of segment designation register n using arrow 20, as shown in the figure. As illustrated by the arrow, the divided area on the main memory corresponding to this register is divided into the buffer memory 6, and therefore from segment 4-1 to segment 4-1! of the index array 4. Perform % accommodation replacement. Such re-accommodation can also be performed according to the contents of the access count counter 52. When designing an application system, it is possible to allocate and change the main memory divided areas to appropriate buffer memory segments based on the layout of the main memory and the movement of the program.

The above mapping method is set atssia tape method 2′
Although the present invention has been described in detail with reference to the case in which the mapping method is adopted, the present invention is not limited thereto, and any other suitable mapping method may be adopted. There are 41 segments! Although the case of I has been illustrated, this can be set to an appropriate number of 2 or more. Although the case in which the size of the segment νF is all the same has been illustrated, the present invention is not limited to this, but is not limited to O, but generally segments of different sizes.
□ can also be used. In addition, although we have given an example of a case in which segment allocation and conversion are performed by the central processing unit, this [method performed by a buffer memory management device% formula%% formula%] As explained in detail above, the method of the present invention allocates the storage area on the buffer memory. Since the system is divided into a plurality of segments and a storage area on the main storage device is allocated to each segment, it is possible to smooth out the temporal fluctuations in the hit rate in the conventional method and improve the time average value thereof.

In other words, in the conventional method that does not perform K-division (segment), when execution of a certain section of the program starts, many blocks near the corresponding main storage area are replaced in the buffer memory due to the corresponding locality, and the hit rate gradually increases. do. In this situation, the program stopped running. J+
When moving to an interval, the hit rate decreases significantly until the blocks near the main storage area corresponding to that interval are replaced in the buffer memory.

In this way, in the conventional method, the hit rate increases or decreases significantly every time the section on the program is changed, and (if the K section is changed frequently, the hit rate will increase or decrease before you see an improvement in the hit rate after changing the section). With the new section change, the hit rate drops again to a low level.

On the other hand, according to the configuration of the present invention described above, since the capacity of the buffer memory stored in each section is substantially reduced, the improvement in the hit rate within each section is limited to some extent. While a section is being executed, the main storage area corresponding to another section is always held in the buffer memory, so the hit rate does not drop significantly immediately after changing the section as in the conventional example O. The improvement effect becomes more noticeable as the section changes become more frequent. In short, according to the present invention, as described above, it is possible to smooth out the temporal fluctuations in the hit rate of the conventional example K and improve the time average value thereof.

According to the above-described configuration of the present invention, different types of optimal replacement management methods (replacement management methods) are used as needed to correspond to divided segments, that is, to correspond to divided areas on the main memory.
There is also the advantage that algorithms can be applied.

(9) The method of the present invention is configured to actually measure the usage frequency and hit rate for each segment, and flexibly change the allocation of the main storage area to each segment according to the actual measurement results, the type of program, or both. This has the advantage that it is possible to dynamically optimize main storage area allocation for the purpose of improving efficiency.

[Brief explanation of drawings]

FIG. 1 is a block diagram showing an example of the configuration of a system to which the method of the present invention is applied, and FIG. 2 is a block diagram for explaining the operation of allocating and changing main storage areas corresponding to segments. 1...address register that stores the main memory address;
2... Segment number converter, 3... Comparator, 4...
... Buffer memory index array, 5... Counter, 6... Buffer memory, 7... Main memory. Patent applicant Fuji Electric Manufacturing Co., Ltd. (1 other person) Representative patent attorney Hisashi Tamamushi (3 others) Figure 1

Claims (1)

[Claims] Divide the storage area on the buffer memory into a plurality of segments, allocate the storage area on the main storage device for each segment, measure the reference frequency or hit rate for each segment, and measure the measurement results or the type of program or these. 1. A buffer memory control method characterized in that allocation of a storage area on a main storage device to each segment is changed according to both of the above.