CN110045743A - It is a kind of to be added in the air by oily visual sensing system hardware structure based on nobody of DSP and FPGA - Google Patents
It is a kind of to be added in the air by oily visual sensing system hardware structure based on nobody of DSP and FPGA Download PDFInfo
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- G—PHYSICS
- G05—CONTROLLING; REGULATING
- G05D—SYSTEMS FOR CONTROLLING OR REGULATING NON-ELECTRIC VARIABLES
- G05D1/00—Control of position, course, altitude or attitude of land, water, air or space vehicles, e.g. using automatic pilots
- G05D1/08—Control of attitude, i.e. control of roll, pitch, or yaw
- G05D1/0808—Control of attitude, i.e. control of roll, pitch, or yaw specially adapted for aircraft
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- G—PHYSICS
- G05—CONTROLLING; REGULATING
- G05D—SYSTEMS FOR CONTROLLING OR REGULATING NON-ELECTRIC VARIABLES
- G05D1/00—Control of position, course, altitude or attitude of land, water, air or space vehicles, e.g. using automatic pilots
- G05D1/10—Simultaneous control of position or course in three dimensions
- G05D1/101—Simultaneous control of position or course in three dimensions specially adapted for aircraft
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Abstract
The present invention relates to one kind, nobody is aerial plus by oily visual sensing system hardware structure, based on multi-core DSP and FPGA platform, using XILINX Kintex7 series of X C7K325T FPGA as primary processor, it is mainly responsible for the high speed acquisition of image, pretreatment, transmission and display, using the eight core DSP of TMS320C6678 of Texas Instruments company as coprocessor, after the image for receiving Kintex7 FPGA transmission, call its internal eight nuclear resource, realize target identification, tracking and location algorithm, 6 series of X C6SLX45 FPGA of XILINX Spartan realizes Kintex7 FPGA and TMS320C66 as system administration chip The upper power-off sequential of 78 DSP and starting management.The framework solves the latency issue of Conventional visual sensor-based system on hardware structure level, realizes real time high-speed acquisition, the processing of image.
Description
Technical field
The invention belongs to air vehicle technique fields, and being related to one kind, nobody adds by oily visual sensing system hardware structure in the air.
Background technique
Currently, machine vision is one of artificial intelligence, the important research field of robot research, key technology is exactly high
Fast Image Acquisition, processing system.Traditional image processing system is the image procossing based on PC framework, based on PC framework mostly
System mainly has the advantages that versatile, scalability is strong, but its operation be function complexity windows operating system, compared with
More system resources consumptions are in system service, to influence the calculated performance and real-time of whole system.And for unmanned empty
In plus by for oil, quick dynamic characteristic, high flying speed then determine vision system must have high real-time and
High accuracy also has higher requirement simultaneously for system dimension.Although also having already appeared based on DSP and FPGA on the market at present
High speed Image Acquisition, processing board, as Microelectronics Institute, the Chinese Academy of Sciences research and develop the Kintex-7 towards CameraLink interface
The TL6678F-EasyEVM development board developed with TMS320C6678 visual pattern processing system and Guangzhou Chuan Long company, this two
Product can realize the acquisition and processing of high speed image, but this two product all just for Cameralink camera with
The framework of FPGA is discussed, and is all technical grade product, and framework is unable to satisfy the specific demand of air refuelling.
Summary of the invention
Technical problems to be solved
In order to avoid the shortcomings of the prior art, the present invention proposes a kind of high real-time, height of the base based on DSP and FPGA
Processing speed, system hardware framework small in size, low in energy consumption is aerial in case of nobody plus is used by oil.
Technical solution
It is a kind of to be added in the air by oily visual sensing system hardware structure based on nobody of DSP and FPGA, it is characterised in that including
Two FPGA, a DSP, power conversion module and clock-generating device；One of FPGA uses XILINX company Kintex7
Series of X C7K325T-2FFG900I, as host processor chip；External 256MB DDR3-1333 memory is used as image data
Buffer area；External 128MB NOR FLASH can will be solidificated in NOR using logic circuit by being configured to BPI mode
In FLASH, is realized and powered on automatically from NOR FLASH starting by the configuration of user's toggle switch；The FPGA provides two-way independent thousand
Mbit ethernet interface is used as GigE Vision camera interface all the way, is used as host computer interface all the way；The FPGA extends two-way
CameraLink interface, can be configured to the input of two-way Base mode or Full mode inputs all the way；The FPGA draws 2 outward
Road SPI interface, 2 tunnel I2C interfaces, 8 road I/O interfaces, 1 road RS232/485 interface and 8 road user modes selection switch are for user
It uses；DSP uses the TMS320C6678 DSP of Texas Instruments company, as harmonizing processor chip, is responsible for image
Processing；The external 1GB DDR3-1333 memory of DSP, the buffer area as image data；The external 16MB NOR FLASH of DSP leads to
It crosses spi bus to hang on DSP, for storing application program；The external 64MB NAND FLASH of DSP, passes through EMIF interface and DSP
It is connected, for storing algorithm routine；The external 128KB EEPROM of DSP, is connect by iic bus with DSP, and storing initial is used to
Parameter and Boot program power on automatic guidance by the configuration of user's toggle switch and are stored in NAND FLASH or NOR FLASH's
Application program；DSP provides two-way 100 m ethernet mouth, transmits for data；DSP provides high-performance HyperLink interface all the way,
It is connected for plate grade, two boards card can be used and constitute double redundancy system；Another FPGA uses XILINX company Spartan 6
Series of X C6SLX45T-CSG324 FPGA is responsible for TMS320C6678, XC7K325T-2FFG900I as system administration chip
Upper power-off sequential control, starting management；The external 16MB NOR FLASH of the FPGA is coupled by spi bus, is used to burning
Cure applications logic circuit program is realized by the configuration of user's toggle switch and is powered on automatically from NOR FLASH starting；Kintex7
FPGA realizes data transmission by UART protocol or 20 couples of difference I/O and Spartan6 FPGA interconnection；Kintex7 FPGA passes through
Image data is transferred to TMS320C6678 DSP by high speed I/O port or PCIE bus；TMS320C6678 DSP passes through spi bus
Processing result image is returned into Kintex7 FPGA；Spartan6 FPGA by GPIO or spi bus or UART protocol with
Data transmission is completed in TMS320C6678 DSP interconnection；Power conversion module converts external power supply to the electricity that each chip needs
Source, clock-generating device provide the clock of each chip operation.
Beneficial effect
Nobody adds by oily visual sensing system hardware structure one kind proposed by the present invention in the air, is on the one hand base using FPGA
In the strong feature of the processing complicated algorithm ability of this strong advantage of the parallel processing capability of pure hardware logic and DSP, so that system
Framework had not only been able to satisfy system real time but also can guarantee the high reliability of system and largely reduce the power consumption of system, allowed
System has stronger environmental suitability；On the other hand directly passed through by improving image capture module framework on the original basis
FPGA drives the GigE camera to further improve the acquisition rate of image, it can be achieved that 50 frames/s image transmitting.
Detailed description of the invention
Fig. 1 is hardware architecture diagram one of the invention.
Fig. 2 is hardware structure diagram two of the invention.
Specific embodiment
Now in conjunction with embodiment, attached drawing, the invention will be further described:
The external two gigabit networking interfaces of Kintex7 FPGA are used to the acquisition and display of image in hardware structure of the present invention,
One connect the image data for obtaining camera in real time with GigE camera, another connect real-time display image with host computer；In addition
External two-way CameraLink interface is connect with CameraLink camera on Kintex7 FPGA, can be configured to two-way Base mould
Formula input or all the way input of Full mode.It is passed after FPGA gets image data by the image data that SRIO interface will acquire
Algorithm process is done to DSP, and treated result by SPI interface is returned to Kintex7 FPGA by DSP, and Kintex7 FPGA is most
Send processing result to host computer real-time display afterwards.
Hardware structure key characteristic of the present invention is as follows:
(1) it is born using XILINX company Kintex7 series of X C7K325T-2FFG900I FPGA as host processor chip
Blame Image Acquisition, transmission and peripheral interface control；
(2) image is responsible for as harmonizing processor chip using Texas Instruments company's T MS320C6678 DSP
Processing；
(3) using 6 series of X C6SLX45T-CSG324 FPGA of XILINX company Spartan as system administration chip,
It is responsible for power-off sequential control on TMS320C6678, Kintex7 FPGA, starting management；
(4) the external 1GB DDR3-1333 memory of TMS320C6678, the buffer area as image data；
(5) the external 256MB DDR3-1333 memory of Kintex7 FPGA, the buffer area as image data；
(6) the external 16MB NOR FLASH of TMS320C6678, is hung on DSP by spi bus, simple for storing, and is needed
Start fast application program；
(7) the external 64MB NAND FLASH of TMS320C6678 is connected, for storing complexity with DSP by EMIF interface
Algorithm routine；
(8) the external 128KB EEPROM of TMS320C6678 is connect by iic bus with DSP, is used to storing initialization and is joined
Several and Boot program powers on automatic guidance by the configuration of user's toggle switch and is stored in answering for NAND FLASH or NOR FLASH
Use program；
(9) the external 128MB NOR FLASH of Kintex7 FPGA can will be applied and be patrolled by being configured to BPI mode
It collects circuit to be solidificated in NOR FLASH, is realized and powered on automatically from NOR FLASH starting by the configuration of user's toggle switch；
(10) the external 16MB NOR FLASH of 6 FPGA of Spartan is coupled by spi bus, is used to burning and solidifies
Using logic circuit program, is realized and powered on automatically from NOR FLASH starting by the configuration of user's toggle switch；
(11) Kintex7 FPGA provides two-way independence gigabit ethernet interface, connects all the way as GigE Vision camera
Mouthful, it is used as host computer interface all the way；
(12) Kintex7 FPGA extend two-way CameraLink interface, can be configured to two-way Base mode input or
Full mode inputs all the way；
(13) TMS320C6678 provides 100,000,000 100 m ethernet mouth of two-way, transmits for data；
(14) TMS320C6678 provides high-performance HyperLink interface all the way, connects for plate grade, can be used two pieces
Board constitutes double redundancy system；
(15) Kintex7 FPGA draws 2 road SPI interfaces, 2 tunnel I2C interfaces, 8 road I/O interfaces, 1 road RS232/485 outward
Interface and 8 road user modes selection switch are for users to use；
(16) framework is powered using 5V/6A DC power supply.
The present invention uses the framework of eight core TMS320C6678 DSP of Kintex7 FPGA+, the Kintex7 of Xilinx company
Acquisition, processing and Interface Expanding of the FPGA as image, the TMS320C6678 DSP of TI company be used to carry out image processing,
Identification and tracking pass through high speed I/O port (SRIO) or PCIE mouthfuls of connections between FPGA and DSP.Kintex7 FPGA passes through kilomega network
Network interface, GigE agreement are communicated with GigE camera, by CameraLink interface, CameraLink agreement and CameraLink phase
Machine communication, by gigabit networking interface, udp protocol is communicated with host computer.In addition, completing DSP using 6 FPGA of Spartan
Timing and starting management.System hardware architecture design mainly includes following module:
(1) power module
The present invention is basic power supply with DC power supply, is powered by 5V/10A power supply adaptor, passes through DC/DC, LDO etc. afterwards
Circuit conversion is at desired voltage value.Wherein, DSP core power supply CVDD ((0.9V~1.05V) (Smart Reflex)) is used
The integrated mode of LM10011 chip+TPS56221 (DC-DC) chip, the base that LM10011 passes through the FB pin of change TPS56211
Quasi- voltage come realize voltage intelligence adjust；TMS320C6678DSP 1.0V power supply is for supplying DSP storage inside and SerDes
Serial transceiver mainly provides the high speed protocols such as SRIO, PCIE, Hyperlink, EMIF and uses, using TPS56221 (DC-DC)
Chip, major advantage are high-efficient, and ripple is smaller, and input range is wide, and stability is good, and power is high；Kintex7 FPGA core electricity
Source (1.0V), using ISL8225 chip, structure and circuit are simple, do not need outer connecting resistance, and power is also met the requirements, Ke Yida
To 15A electric current；Accessory power supply 3.3V and 1.8V are provided, doubleway output, every road using TPS7A89 (DC-DC) power supply chip of TI
Electric current is up to 3A or so, for supplying other circuits use such as 6 Series FPGA of Spartan and debugging LED light, switch；In DSP
2.5V, 1.8V, 1.5V, 1.2V power supply, required electric current is between 1~3A, in order to simplify circuit while guarantee power and efficiency
It is required that can export 4 road power supplys simultaneously using LTM4644 (DC-DC) power supply chip, every road can stablize output 4A electric current；
The 2.5V of Kintex7 FPGA, 1.8V, 1.5V, 1.0V power supply are equally realized using LTM4644 power supply chip；Used in DR3
0.75V supplies DDR3 reference voltage, then realizes mainly have pressure difference small, the small advantage of noise using the TPS51200 chip of TI.
(2) clock module
The present invention has directlyed adopt source crystal oscillator as clock-generating device, and specific chip is using SiTime company
SIT9122, SIT9121, SIT91565 and SIT8008B series.Wherein, the master clock frequency of Spartan6 FPGA is
100MHz；TMS320C6678 DSP configure three road 100MHz clocks (be respectively used to DSP core clock, DSP_PCIE clock,
PASS network coprocessor clock), two-way 312.5MHz clock (all the way for DSP_SRIO, all the way be used for Hyperlink), one
Road 66.667MHz clock (is used for DDR3)；Kintex7 FPGA configuration two-way 125MHz clock (be respectively used to FPGA_SRIO,
FPGA_PCIE), 156.25MHz clock (be used for FPGA_SRIO reference clock), all the way 200MHz clock (K7 nuclear clock) all the way.
(3) memory module
In the present invention, TMS320C6678 DSP has used 3 external memories, wherein by EMIF-16bit interface with
The NAND FLASH connection of one piece of 64MB, is connected with the EEPROM of one piece of 128KB by iic bus, passes through SPI and one piece of 16MB
NOR FLASH be connected；Spartan6 FPGA is used to do power management, and therefore amount of circuitry is smaller, configures the NOR of a 16MB
FLASH；Kintex7 FPGA is used to Image Acquisition, processing and communication, therefore amount of circuitry is larger, using the BPI agreement of 128MB
NOR FLASH has reading speed fast, the big feature of capacity.For the operation for cooperating multicore digital signal processing platform powerful
Ability and data communication bandwidth, it is necessary to introduce high speed storing technology, the capacity and bandwidth of memory are also to measure at digital signal
One basic index of platform performance.DDR3 memory is the high speed dynamic that current high-end computer system is most widely used
Memory has the technical characterstics such as high bandwidth, high density, low-power consumption.Traditional memory technology is substantially better than in transmission rate,
Power consumption is also reduced while promoting storage performance, core voltage is further reduced.In addition, the order of DDR3, address
Fly-B topological structure is all made of instead of traditional T-type structure with control line, to reduce cabling branch, length and simultaneously
The signal number of switch, it is suppressed that signal reflex reduces simultaneous switching noise, enhances the quality of signal and power supply.According to being
The demand of system and the advantage of DDR3, the present invention in use DDR3 memory technology, for TM320C6678 DSP configure 5 1Gbit
1333 storage chip of DDR3 uses 64bit mode；Kintex7FPGA is due to needing the acquisition of data to transmit, pre-process etc. other
Communication protocol functions, therefore 1333 storage chip of two panels 1Gbit DDR3 is configured for it.
(4) communication link
In the present invention, there are the transmission of image data between Kintex7 FPGA and TM320C6678 DSP, and need
Real-time is fine, it is therefore desirable to which the channel of high speed is realized.Be attached using SRIO or PCIE communication interface, it is additional all the way
SPI communication realizes the interaction of small data；Data exchange is less between Kintex7 FPGA and Spartan6 FPGA, therefore adopts
Communication is realized with UART and 20 couple of difference IO；Communication is mainly boot mould between Spartan6 FPGA and TM320C6678 DSP
The selection of formula and other initial configurations, therefore shared drive SPI is used, GPIO, UART mode are realized.
(5) application environment
The visual sensing system hardware structure that the present invention designs adds in the air by unmanned plane is mainly used in by oily docking rank
Section provides precise position information in case subsequent aspect controls for unmanned plane in docking operation.By being mounted on aircraft
On GigE camera or Cameralink camera obtain the position of oiling bar or fuel filling taper sleeve in real time, then Kintex7FPGA
The image information of acquisition is transmitted to host computer all the way and shown into after crossing the operation such as pretreatment, be transmitted to all the way TM320C6678 DSP into
The processing of row target identification, track algorithm, obtains the precise position information of oiling bar or tapered sleeve, and last TM320C6678 DSP will
Result that treated is sent to Kintex7 FPGA, sends result to host computer real-time display or biography by Kintex7 FPGA
To flight control system, closed loop is formed with flight control system, completes the control of aspect, to improve docking success rate and docking essence
Degree.
The present invention is based on multi-core DSPs and FPGA platform, using XILINX Kintex7 series of X C7K325T FPGA as main place
Device is managed, high speed acquisition, pretreatment, transmission and the display of image are mainly responsible for, using Texas Instruments company
Eight core DSP of TMS320C6678 is as coprocessor, after the image for receiving Kintex7 FPGA transmission, calls its inside eight
Nuclear resource realizes target identification, tracking and location algorithm, and 6 series of X C6SLX45 FPGA of XILINX Spartan is as system
Managing chip realizes upper power-off sequential and the starting management of Kintex7 FPGA and TMS320C6678 DSP.The framework is in hardware
It solves the latency issue of Conventional visual sensor-based system on framework level, realizes real time high-speed acquisition, the processing of image.
Claims (1)
1. a kind of added by oily visual sensing system hardware structure in the air based on nobody of DSP and FPGA, it is characterised in that including two
A FPGA, a DSP, power conversion module and clock-generating device；One of FPGA uses Kintex7 system, XILINX company
XC7K325T-2FFG900I is arranged, as host processor chip；External 256MB DDR3-1333 memory, as image data
Buffer area；External 128MB NOR FLASH can will be solidificated in NOR using logic circuit by being configured to BPI mode
In FLASH, is realized and powered on automatically from NOR FLASH starting by the configuration of user's toggle switch；The FPGA provides two-way independent thousand
Mbit ethernet interface is used as GigE Vision camera interface all the way, is used as host computer interface all the way；The FPGA extends two-way
CameraLink interface, can be configured to the input of two-way Base mode or Full mode inputs all the way；The FPGA draws 2 outward
Road SPI interface, 2 tunnel I2C interfaces, 8 road I/O interfaces, 1 road RS232/485 interface and 8 road user modes selection switch are for user
It uses；DSP uses the TMS320C6678 DSP of Texas Instruments company, as harmonizing processor chip, is responsible for image
Processing；The external 1GB DDR3-1333 memory of DSP, the buffer area as image data；The external 16MB NOR FLASH of DSP leads to
It crosses spi bus to hang on DSP, for storing application program；The external 64MB NAND FLASH of DSP, passes through EMIF interface and DSP
It is connected, for storing algorithm routine；The external 128KB EEPROM of DSP, is connect by iic bus with DSP, and storing initial is used to
Parameter and Boot program power on automatic guidance by the configuration of user's toggle switch and are stored in NAND FLASH or NOR FLASH's
Application program；DSP provides two-way 100 m ethernet mouth, transmits for data；DSP provides high-performance HyperLink interface all the way,
It is connected for plate grade, two boards card can be used and constitute double redundancy system；Another FPGA uses XILINX company Spartan 6
Series of X C6SLX45T-CSG324 FPGA is responsible for TMS320C6678, XC7K325T-2FFG900I as system administration chip
Upper power-off sequential control, starting management；The external 16MB NOR FLASH of the FPGA is coupled by spi bus, is used to burning
Cure applications logic circuit program is realized by the configuration of user's toggle switch and is powered on automatically from NOR FLASH starting；Kintex7
FPGA realizes data transmission by UART protocol or 20 couples of difference I/O and Spartan6 FPGA interconnection；Kintex7 FPGA passes through
Image data is transferred to TMS320C6678 DSP by high speed I/O port or PCIE bus；TMS320C6678 DSP passes through spi bus
Processing result image is returned into Kintex7 FPGA；Spartan6 FPGA by GPIO or spi bus or UART protocol with
Data transmission is completed in TMS320C6678 DSP interconnection；Power conversion module converts external power supply to the electricity that each chip needs
Source, clock-generating device provide the clock of each chip operation.
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| CN112182873A (en) * | 2020-09-24 | 2021-01-05 | 西北工业大学 | Method for accelerating aircraft engine model based on hardware system |
| CN112650543A (en) * | 2020-12-21 | 2021-04-13 | 北京神州飞航科技有限责任公司 | FPGA dynamic configuration method |
| CN113961505A (en) * | 2021-10-14 | 2022-01-21 | 南京熊猫电子制造有限公司 | High-performance hardware acceleration and algorithm verification system and method |
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