CN112182873A - Method for accelerating aircraft engine model based on hardware system - Google Patents

Abstract

The invention discloses a method for accelerating an aircraft engine model based on a hardware system. The method adopts DSP to realize a general algorithm, and because the DSP can use C language in development and the DSP is good at floating point operation, the development process is simpler; the FPGA is adopted to realize high-speed transmission of data and a specific algorithm, and the FPGA has higher parallelism, so the speed is very high when the algorithm is processed.

Description

Method for accelerating aircraft engine model based on hardware system

Technical Field

The invention belongs to the field of aviation, and particularly relates to an aircraft engine model acceleration method.

Background

At present, the realization method of the aircraft engine model is based on a computer, most of the adopted software is MATLAB, and a plurality of nonlinear aircraft engine simulation software packages based on MATLAB, such as a civil modularized aviation propulsion system simulation program package (CMAPSS) developed by the NASA Green research center, an engine performance simulation program T-MATS and the like, are provided. The operation speed is low due to the limitation of the operation speed of the computer and the used simulation software. In addition, there are many basic algorithms in the model of the aircraft engine that are frequently called, and such algorithms take up a lot of time of the CPU, thereby resulting in a reduction in the time of the CPU to process the core events. For some tasks with higher parallelism in the model, such as matrix operation, the realization by a computer is not very advantageous.

In summary, the existing implementation method of the aircraft engine simulation model is slow in operation speed and low in efficiency of processing core events.

Disclosure of Invention

In order to overcome the defects of the prior art, the invention provides a method for accelerating an aircraft engine model based on a hardware system. The method adopts DSP to realize a general algorithm, and because the DSP can use C language in development and the DSP is good at floating point operation, the development process is simpler; the FPGA is adopted to realize high-speed transmission of data and a specific algorithm, and the FPGA has higher parallelism, so the speed is very high when the algorithm is processed.

The technical scheme adopted by the invention for solving the technical problem comprises the following steps:

step 1: building a hardware system for accelerating an aircraft engine model algorithm;

the hardware system adopts a DSP + FPGA + DDR3 architecture, wherein the DSP adopts TMS320C6657 of TI company for the calculation function of the model algorithm of the aeroengine;

the FPGA part comprises XC7VX690T FPGA of Virtex-7 series and XC200AN FPGA of Spartan-3 series of Xilinx company; XC7VX690T FPGA is used for accelerating a high-parallelism algorithm in an aircraft engine model algorithm and quickly transmitting data; the XC200AN FPGA is used for managing a clock, a power supply and peripheral equipment of a hardware system;

TMS320C6657 DSP, XC7VX690T FPGA and XC200AN FPGA can be communicated with each other in two ways;

TMS320C6657 DSP and XC7VX690T FPGA are externally provided with DDR3 memory and are used for caching temporary data of an aircraft engine model algorithm; TMS320C6657 DSP and XC7VX690T FPGA are both configured with Flash for programming of an aircraft engine model algorithm program; high-speed data transmission is carried out between the TMS320C6657 DSP and the XC7VX690T FPGA through an SRIO interface, and low-speed data transmission is carried out through an EMIF16 interface; the communication protocol of the hardware system adopts a TCP/IP protocol, and the TMS320C6657 DSP and the XC7VX690T FPGA are both connected with an Ethernet interface;

step 2: importing an aircraft engine model algorithm;

compiling a high-parallelism algorithm in an aircraft engine model algorithm by using a hardware description language, and realizing the high-parallelism algorithm by adopting XC7VX690T FPGA;

importing a general algorithm in an aircraft engine model algorithm into a TMS320C6657 DSP, which comprises the following specific steps:

creating a project in a CCS (development center system), selecting a TMS320C6657 equipment model, introducing a general algorithm in an aircraft engine model algorithm into the created project, and adding a gel file and a cmd file, wherein the gel file and the cmd file respectively realize the functions of initializing a DSP (digital signal processor) and distributing a DSP storage space; then compiling the algorithm, and correcting syntax errors until the compiling is passed;

and step 3: through the steps 1 and 2, the aim of accelerating the aircraft engine model through hardware is achieved.

The invention has the beneficial effects that: by adopting the method for accelerating the aircraft engine model based on the hardware system, the basic algorithm in the model is realized by the DSP, and the operating speed of the basic algorithm is improved by utilizing the characteristics of high floating point operation speed and low overhead loop body support of the DSP; the FPGA is adopted to realize the algorithm with higher parallelism, and the running speed of the algorithm is improved.

Drawings

FIG. 1 is a diagram of a hardware system architecture according to the present invention.

Detailed Description

The invention is further illustrated with reference to the following figures and examples.

As shown in FIG. 1, the present invention provides a method for accelerating an aircraft engine model based on a hardware system, comprising the steps of:

step 1: building a hardware system for accelerating an aircraft engine model algorithm;

the hardware system adopts a DSP + FPGA + DDR3 architecture, wherein the DSP adopts TMS320C6657 of TI company for the calculation function of the model algorithm of the aeroengine;

the FPGA part comprises XC7VX690T FPGA of Virtex-7 series and XC200AN FPGA of Spartan-3 series of Xilinx company; XC7VX690T FPGA is used for accelerating a high-parallelism algorithm in an aircraft engine model algorithm and quickly transmitting data; the XC200AN FPGA is used for managing a clock, a power supply and peripheral equipment of a hardware system;

TMS320C6657 DSP, XC7VX690T FPGA and XC200AN FPGA can be communicated with each other in two ways;

TMS320C6657 DSP and XC7VX690T FPGA are externally provided with DDR3 memory and are used for caching temporary data of an aircraft engine model algorithm; TMS320C6657 DSP and XC7VX690T FPGA are both configured with Flash for programming of an aircraft engine model algorithm program; high-speed data transmission is carried out between the TMS320C6657 DSP and the XC7VX690T FPGA through an SRIO interface, and low-speed data transmission is carried out through an EMIF16 interface; the communication protocol of the hardware system adopts a TCP/IP protocol, and the TMS320C6657 DSP and the XC7VX690T FPGA are both connected with an Ethernet interface;

step 2: importing an aircraft engine model algorithm;

compiling a high-parallelism algorithm in an aircraft engine model algorithm by using a hardware description language, and realizing the high-parallelism algorithm by adopting XC7VX690T FPGA;

importing a general algorithm in an aircraft engine model algorithm into a TMS320C6657 DSP, which comprises the following specific steps:

creating a project in a CCS (development center system), selecting a TMS320C6657 equipment model, introducing a general algorithm in an aircraft engine model algorithm into the created project, and adding a gel file and a cmd file, wherein the gel file and the cmd file respectively realize the functions of initializing a DSP (digital signal processor) and distributing a DSP storage space; then compiling the algorithm, and correcting syntax errors until the compiling is passed;

and step 3: through the steps 1 and 2, the aim of accelerating the aircraft engine model through hardware is achieved.

The specific embodiment is as follows:

take an algorithm of an aero-thermodynamic module in an aero-engine model as an example.

1. Analysis, import and debug of algorithms

Firstly, the module algorithm is obtained by analysis, and the characteristics are as follows: the algorithm is simple, the calling frequency is high, a large number of floating-point number operations are included, and a loop body is used as a main structure. Based on the characteristics of the algorithm analyzed above and the characteristics of the DSP, the algorithm is suitable for being implemented on the DSP. Because the algorithm is C language, the development software Code Composer Studio (CCS) of the DSP can be directly imported, and if the algorithm is to be realized on the FPGA, the algorithm needs to be rewritten by using a hardware description language.

A project is created in the CCS, and the device model is selected as the DSP model actually used on the development board, i.e., TMS320C 6657. And importing the algorithm into the project, and adding a gel file and a cmd file, wherein the two files respectively realize the functions of initializing the DSP and distributing the storage space. And compiling the algorithm, and correcting syntax errors until the compiling is passed.

During debugging, one end of the simulator is connected with the development board, the other end of the simulator is connected with the computer, a switch on the development board is adjusted to a debug mode, the debug mode is clicked in the CCS, the program is downloaded into the DSP to run, the running result is observed to see whether the running result is consistent with the running result of the computer, and if the running result is consistent with the running result of the computer, the function is correct. Besides the debug mode, the program can be solidified in the NOR Flash connected with the TMS320C6657, and the switch on the development board is adjusted to the other side, so that the development board is not required to be connected with a computer through an emulator, and the development board can load the program from the NOR Flash to run after being electrified.

2. Development board communication with MATLAB

In the case of MATLAB used with a development board, data and control information needs to be communicated between the two. Taking a function of temperature enthalpy value calculation known in the aerodynamic thermodynamic module as an example, the MATLAB transmits the input values T, fa and i to the DSP, and the DSP transmits the function operation result H back to the MATLAB.

At the MATLAB end, a TCP/IP object is firstly created, and the network attribute, the IP address, the buffer size, the byte order and other attributes of the TCP/IP object are set. On the DSP side, the specific programming method may refer to TI official routines.

After the code writing of the communication protocol is completed, the development board is connected with the computer by using a network cable, and the IP address of the Ethernet adapter is set on the computer. After the setting is finished, the program of the server end in the DSP and the program of the MATLAB are firstly operated, and then the program of the client end is operated, so that the data transmission of the DSP and the MATLAB can be finished.

Claims (1)

1. A method for accelerating an aircraft engine model based on a hardware system is characterized by comprising the following steps:

step 1: building a hardware system for accelerating an aircraft engine model algorithm;

the hardware system adopts a DSP + FPGA + DDR3 architecture, wherein the DSP adopts TMS320C6657 of TI company for the calculation function of the model algorithm of the aeroengine;

the FPGA part comprises XC7VX690T FPGA of Virtex-7 series and XC200AN FPGA of Spartan-3 series of Xilinx company; XC7VX690T FPGA is used for accelerating a high-parallelism algorithm in an aircraft engine model algorithm and quickly transmitting data; the XC200AN FPGA is used for managing a clock, a power supply and peripheral equipment of a hardware system;

TMS320C6657 DSP, XC7VX690T FPGA and XC200AN FPGA can be communicated with each other in two ways;

TMS320C6657 DSP and XC7VX690T FPGA are externally provided with DDR3 memory and are used for caching temporary data of an aircraft engine model algorithm; TMS320C6657 DSP and XC7VX690T FPGA are both configured with Flash for programming of an aircraft engine model algorithm program; high-speed data transmission is carried out between the TMS320C6657 DSP and the XC7VX690T FPGA through an SRIO interface, and low-speed data transmission is carried out through an EMIF16 interface; the communication protocol of the hardware system adopts a TCP/IP protocol, and the TMS320C6657 DSP and the XC7VX690T FPGA are both connected with an Ethernet interface;

step 2: importing an aircraft engine model algorithm;

compiling a high-parallelism algorithm in an aircraft engine model algorithm by using a hardware description language, and realizing the high-parallelism algorithm by adopting XC7VX690T FPGA;

importing a general algorithm in an aircraft engine model algorithm into a TMS320C6657 DSP, which comprises the following specific steps:

creating a project in a CCS (development center system), selecting a TMS320C6657 equipment model, introducing a general algorithm in an aircraft engine model algorithm into the created project, and adding a gel file and a cmd file, wherein the gel file and the cmd file respectively realize the functions of initializing a DSP (digital signal processor) and distributing a DSP storage space; then compiling the algorithm, and correcting syntax errors until the compiling is passed;

and step 3: through the steps 1 and 2, the aim of accelerating the aircraft engine model through hardware is achieved.

Images