CN209803659U

CN209803659U - Clock control system in GPU server

Info

Publication number: CN209803659U
Application number: CN201920509948.8U
Authority: CN
Inventors: 孔祥涛
Original assignee: Suzhou Wave Intelligent Technology Co Ltd
Current assignee: Suzhou Wave Intelligent Technology Co Ltd
Priority date: 2019-04-16
Filing date: 2019-04-16
Publication date: 2019-12-17
Anticipated expiration: 2029-04-16

Abstract

The utility model provides a clock control system in a GPU server, which comprises a mainboard and a GPU board; the mainboard comprises an internal clock signal module; the GPU board comprises a local clock signal module, a clock selection module, a clock expansion module and a plurality of GPUs; when a Common refclk architecture is needed, an external clock source is selected to access the clock mux by controlling a control end of the clock mux, and clock sources of the CPU and the GPU are homologous clocks. When the Independent refclk architecture is needed, a local clock source is selected to access the clock mux by controlling the control terminal of the clock mux. At this time, the clock sources of the CPU and the GPU are non-homologous clocks. The utility model discloses provide two kinds of selections of local clock source and external clock source for GPU.

Description

Clock control system in GPU server

Technical Field

The utility model relates to a clock control system technical field in the server specifically provides a clock control system in GPU server.

Background

GPU servers are a type of server that deploys 2-block or even 16-block GPUs on the basis of a traditional server architecture. GPU servers are often used for acceleration computing in cloud computing or large-scale deep neural network model training occasions. The GPU acceleration calculation refers to the fact that the GPU and the CPU are simultaneously utilized to accelerate the running speed of the application program. The CPU consists of several cores optimized specifically for sequential serial processing. GPUs have a massively parallel computing architecture consisting of thousands of smaller, more efficient cores designed to handle multiple tasks simultaneously. Great excellence is in large-scale concurrent computation. The CPU and the GPU work cooperatively. The workload of the compute-intensive portion of the application is transferred to the GPU while the remaining program code is still run by the CPU. From the user's perspective, the running speed of the application program is significantly increased. When the number of GPUs is large, a GPU box is usually fabricated to centrally deploy the GPUs. The GPUbox is composed of a GPU board, a power supply, a fan, a structural part and the like. The GPU box is provided with an external interface and can be connected to an external server through a cable. This approach may provide centralized power, management, clocking and heat dissipation for all GPUs. The channel for data transmission between the CPU and the GPU is PCI-e. Therefore, all GPUs need to be provided with a 100MHZ reference clock. The PCI SIG defines two clock architectures. Common refclk and Independent refclk. The Common refclk architecture requires that the CPU and GPU have the same clock source. Independent refclk allows the GPU and CPU to have different clock sources.

Existing GPU box clock schemes only provide a local clock source. The Common refclk architecture can support SSCs, and the Independent refclk architecture cannot support SSCs. Opening the SSC can help reduce EMI when the server has EMI problems. Therefore, the prior art does not have the function of reducing EMI.

Disclosure of Invention

To above shortcoming, the embodiment of the utility model provides a clock control system in GPU server provides two kinds of selections of local clock source and external clock source for GPU, solves the problem that does not have the homologous clock among the prior art.

A clock control system in a GPU server comprises a mainboard and a GPU board;

The mainboard comprises an external clock signal module;

the GPU board comprises a local clock signal module, a clock selection module, a clock expansion module and a plurality of GPUs;

The external clock signal module and the local clock signal module are both connected with the input end of the clock selection module; the output end of the clock selection module is connected with the input end of the clock expansion module; and the output end of the clock expansion module is connected with a plurality of GPU boards.

Furthermore, the clock selection module is also connected with the clock selection control module.

Further, the clock selection control module is preferably configured with a jump cap.

further, the Clock spreading module is a Clock buffer.

Further, the External clock signal module is an External clock Source.

Further, the Local Clock signal module is a Local Clock Source.

Further, the Clock selection module is a Clock selector Clock mux.

Further, the Clock selector Clock mux is an alternative Clock selector Clock mux.

the effect provided in the summary of the invention is only the effect of the embodiment, not all the effects of the invention, and one of the above technical solutions has the following advantages or beneficial effects:

the embodiment of the utility model provides a clock control system in GPU server, including mainboard, GPU board; the mainboard comprises an external clock signal module; the GPU board comprises a local clock signal module, a clock selection module, a clock expansion module and a plurality of GPUs; the external clock signal module and the local clock signal module are both connected with the input end of the clock selection module; the output end of the clock selection module is connected with the input end of the clock expansion module; the output end of the clock expansion module is connected with a plurality of GPU boards. Wherein the Clock selection module selects an alternative Clock selector Clock mux. The clock selection module selects an external clock signal or a local clock signal to access the clock selection module through the clock selection control module. When the Common refclk architecture is required. And selecting an external clock source to access the clock mux by controlling the control end of the clock mux. At this time, the clock sources of the CPU and the GPU are the same source clock. When the Independent refclk architecture is required. And selecting a local clock source to access the clock mux by controlling the control end of the clock mux. At this time, the clock sources of the CPU and the GPU are non-homologous clocks. The utility model discloses provide two kinds of selections of local clock source and external clock source for GPU.

Drawings

fig. 1 is a clock control system architecture diagram in a GPU server according to embodiment 1 of the present invention.

Detailed Description

in order to clearly illustrate the technical features of the present invention, the present invention is explained in detail by the following embodiments in combination with the accompanying drawings. The following disclosure provides many different embodiments, or examples, for implementing different features of the invention. In order to simplify the disclosure of the present invention, the components and arrangements of specific examples are described below. Furthermore, the present invention may repeat reference numerals and/or letters in the various examples. This repetition is for the purpose of simplicity and clarity and does not in itself dictate a relationship between the various embodiments and/or configurations discussed. It should be noted that the components illustrated in the figures are not necessarily drawn to scale. Descriptions of well-known components and processing techniques and processes are omitted so as to not unnecessarily limit the invention.

Example 1

The embodiment 1 of the utility model provides a clock control system in a GPU server, which is used for a mainboard and a GPU board;

the mainboard comprises an external clock signal module; the GPU board comprises a local clock signal module, a clock selection module, a clock expansion module and a plurality of GPUs;

The external clock signal module and the local clock signal module are both connected with the input end of the clock selection module; the output end of the clock selection module is connected with the input end of the clock expansion module; the output end of the clock expansion module is connected with a plurality of GPU boards. The clock selection module is also connected with the clock selection control module.

Fig. 1 is a schematic diagram of a clock control system in a GPU server according to embodiment 1 of the present invention.

In inventive example 1

The mainboard and the motherboard part provide External clock signals, and the External clock signal module is External clock Source. External clock source provides a clock source to the CPU and other PCI-e devices. And simultaneously, providing a path of clock externally connected to the GPU board.

The GPU board comprises a local clock signal module, a clock selection module, a clock expansion module and a plurality of GPUs; the Local Clock signal module is Local Clock Source. The Clock selection module is an alternative Clock selector Clock mux.

the clock expansion module is a clock buffer and can expand one path of clock into multiple paths of clock. The output of the clock mux is connected to the clock buffer input. The expanded clock is provided for the back-end GPU equipment

the External Clock Source on the motherboard and the Local Clock Source on the GPU board are simultaneously connected with the input end of a Clock selector Clock mux, the output end of the Clock mux is connected with the input end of a Clock buffer, and the output end of the Clock buffer is connected with 8 GPUs. GPUO to GPU7, respectively. The number of the GPUs protected by the embodiment of the invention is not limited to 8, and the number of the GPUs to be connected after expansion can be determined according to actual conditions.

The Clock selector Clock mux is connected with the Clock selection control module, and the Clock selection control module can be realized in a hardware mode or a chip control mode. Such as by hardware via configuration of a jump cap, software via CPLD output GPIO control, CPLD via write program output GPIO control of Clock selector Clock mux

When the Common refclk architecture is required. An external clock source is selected to access the clock mux by a clock selection control module that controls the clock mux. At this time, the clock sources of the CPU and the GPU are the same source clock. When the Independent refclk architecture is required. And selecting a local clock source to access the clock mux by controlling the control end of the clock mux. At this time, the clock sources of the CPU and the GPU are non-homologous clocks.

The utility model discloses an increase clock selection control device, can realize that CPU and GPU support Common refclk framework and Independent refclk framework. The defect that only the traditional scheme supports the Independent refclk architecture is overcome.

While the invention has been described in detail in connection with the drawings and examples, it will be understood by those skilled in the art that various changes may be made and equivalents may be substituted; all technical solutions and improvements thereof that do not depart from the spirit and scope of the present invention are covered by the scope of the present invention.

Claims

1. A clock control system in a GPU server is characterized by comprising a mainboard and a GPU board;

The mainboard comprises an external clock signal module;

2. The system according to claim 1, wherein the clock selection module is further connected to the clock selection control module.

3. The system of claim 2, wherein the clock selection control module is configured to preferentially configure a hop cap.

4. The system according to claim 1, wherein the Clock spreading module is a Clock buffer.

5. The system of claim 1, wherein the External clock signal module is an External clock Source.

6. The system of claim 1, wherein the Local Clock signal module is a Local Clock Source.

7. The system of claim 1, wherein the Clock selection module is a Clock selector Clock mux.

8. The system according to claim 7, wherein the Clock selector Clock mux is an alternative Clock selector Clock mux.