CN211628241U - PCIE bus structure switching topology through software - Google Patents

Abstract

The utility model provides a PCIE bus structure through software switching topology, the utility model discloses a BMC is as software control end, through the configuration information of UART change PCIE Switch, and then realizes topological switching, and PCIE Switch realizes two through changing configuration file and goes upward mouthful configuration, and every goes upward mouthful downstream equipment allocation that definition that the configuration can both be free corresponds, utilizes BMC to realize through UART and Switch interconnection that data transmission communication reaches the effect of accomplishing the configuration file update. The utility model discloses a BMC control key carries out topology switching, and supports PCIE4.0 equipment topology switching, and the operation is accomplished by software is automatic, does not need the physical connection change, and BMC can listen the bandwidth rate state of current topology in real time in addition, accurate location problem point.

Description

PCIE bus structure switching topology through software

Technical Field

The utility model relates to a server PCIE bus technical field, especially a PCIE bus structure through software switching topology.

Background

As customer requirements increase, server topologies become more complex, different customers have different requirements, and flexible design becomes more and more important for hardware design. The topology structure is a skeleton of a system, different topologies can realize different performance embodiments, especially for the AI server with high heat at present, the server often has the requirement of topology switching, and how to realize fast and convenient topology switching is a breakthrough point which needs to be solved at present.

The PCIE bus is an important component in the server, and the higher the speed and the higher the requirement, the more difficult the processing. PCIE4.0 speed is doubled compared to PCIE3.0 speed, and topology switching faces greater challenges. There are probably three schemes for existing topology switching:

the first scheme is as follows: the topology switching is realized by manually plugging and unplugging cables in a shutdown state;

scheme II: the topology switching is realized by replacing the back plates, a plurality of back plates are designed according to different scheme requirements during design, and the topology switching is realized by replacing the back plates in a shutdown state;

the third scheme is as follows: the logic switching chip can support one input and multiple outputs, and the topological relation is changed by switching different output links.

Topology switching the general scheme as described above, most of the occupation is to achieve the effect of topology change through physical connection change. According to the first scheme, topology switching is achieved through change of cable connection relations, cables are used to enable the inside of a whole server chassis to be disordered, dozens of lines are needed for a complex system architecture, the arrangement of the lines is complicated, topology switching is achieved through changing the cables, operation is conducted under the condition of complete power failure, then the chassis is opened, mutually interfered components are removed, other components are restored after the cables are adjusted, and starting-up test verification is conducted. The second scheme is similar to the first scheme, only the form of the operation object is changed, if the operation is completed manually by a client, time and labor are consumed, and the actual experience effect is very poor. And in the third scheme, a high-speed physical switch is used for switching a high-speed channel to achieve the switching of the physical channel, and the third scheme needs to additionally use a plurality of auxiliary switching zero devices, so that the cost is high and the stability is poor.

SUMMERY OF THE UTILITY MODEL

The utility model aims at providing a PCIE bus structure through software switching topology aims at solving among the prior art topology switching and has the complexity height, waste time and energy and with high costs poor stability's problem, realizes can realizing the topology switching through software, improves and switches efficiency, reduces the complexity.

In order to achieve the technical purpose, the utility model provides a through the PCIE bus structure of software switching topology, PCIE bus structure includes:

two CPUs, two PCIE switches, and eight GPU devices;

the CPU0 and the CPU1 are respectively connected to the PCIE Switch0 and the PCIE Switch1 through two PORTs 0 interfaces, the PCIE Switch0 and the PCIE Switch1 are respectively connected to the BMC through the UART, the PORTs 1 interfaces of the PCIE Switch0 and the PCIE Switch1 are connected to each other, and 4 GPU devices are respectively mounted under the PCIE Switch0 and the PCIE Switch 1.

Preferably, the two CPUs communicate with each other through UPI.

Preferably, the BMC stores a configuration file of the PCIE Switch.

Preferably, the topology switching can be performed by only changing the configuration file of one of the PCIE Switch in the configuration files.

Preferably, the configuration file comprises two parts:

configuring a first step: PORT0 is connected to CPU as the upstream interface, PORT1 is not available, 4 GPU devices are mounted under PORT 0;

configuring a second step: PORT1 is connected as an upstream interface to another PCIE Switch, PORT0 is not available, and 4 GPU devices are mounted under PORT 1.

Preferably, the PCIE bus structure switches between a Balance mode and a Cascade mode.

The effects provided in the contents of the present invention are only the effects of the embodiments, not all the effects of the present invention, and one of the above technical solutions has the following advantages or advantageous effects:

compared with the prior art, the utility model discloses a BMC changes PCIE Switch's configuration information through the UART as software control end, and then realizes topological switching, and PCIE Switch realizes two through changing the configuration file and goes up a mouthful configuration, and every goes up the downstream equipment allocation that the definition that mouthful configuration can both be free corresponds, utilizes BMC to realize through UART and Switch interconnection that data transmission communication reaches the effect of accomplishing the configuration file update. The utility model discloses a BMC control key carries out topology switching, and supports PCIE4.0 equipment topology switching, and the operation is accomplished by software is automatic, does not need the physical connection change, and BMC can listen the bandwidth rate state of current topology in real time in addition, accurate location problem point.

Drawings

Fig. 1 is a schematic diagram of a PCIE bus structure switching topology through software according to the present invention.

Detailed Description

In order to clearly illustrate the technical features of the present invention, the present invention is explained in detail by the following embodiments in combination with the accompanying drawings. The following disclosure provides many different embodiments, or examples, for implementing different features of the invention. In order to simplify the disclosure of the present invention, the components and arrangements of specific examples are described below. Furthermore, the present invention may repeat reference numerals and/or letters in the various examples. This repetition is for the purpose of simplicity and clarity and does not in itself dictate a relationship between the various embodiments and/or configurations discussed. It should be noted that the components illustrated in the figures are not necessarily drawn to scale. Descriptions of well-known components and processing techniques and processes are omitted so as to not unnecessarily limit the invention.

The following describes the PCIE bus structure with a software switching topology according to the present invention in detail with reference to the accompanying drawings.

As shown in fig. 1, the utility model discloses a through topological PCIE bus structure of software switch, PCIE bus structure includes:

the CPU0 and the CPU1 are respectively connected to the PCIE Switch0 and the PCIE Switch1 through two PORTs 0 interfaces, the PCIE Switch0 and the PCIE Switch1 are respectively connected to the BMC through the UART, the PORTs 1 interfaces of the PCIE Switch0 and the PCIE Switch1 are connected to each other, and 4 GPUs are respectively mounted under the PCIE Switch0 and the PCIE Switch 1.

The PCIE Switch is an indispensable part of the server system to meet the requirement of multiple boards. The utility model discloses a software configuration PCIE Switch realizes topological switching, and PCIE Switch realizes two through changing the configuration file and goes upward mouthful configurations, and every goes upward the downstream equipment distribution that the definition that mouthful configuration can both be free corresponds. The BMC is used as a main monitoring management chip of the mainboard, and achieves the effect of finishing updating the configuration file by realizing data transmission communication through UART and Switch interconnection.

The CPU0 and the CPU1 are respectively connected to the PCIE Switch0 and the PCIE Switch1 through two PORTs 0 interfaces, the PCIE Switch0 and the PCIE Switch1 are respectively connected to the BMC through the UART, and the POET1 interfaces of the PCIE Switch0 and the PCIE Switch1 are connected to each other. Under PCIE Switch0 and PCIE Switch1, 4 GPUs are mounted, namely, GPU0, GPU1, GPU2, and GPU3 are mounted under PCIE Switch0, GPU4, GPU5, GPU6, and GPU7 are mounted under PCIE Switch1, and CPU0 and CPU1 communicate through UPI.

The utility model discloses in, the CPU end is the Host of PCIE Switch as the input source of PCIE signal, and PCIE Switch is for expanding PCIE resource usage, and BMC passes through UART and PCIE Switch interconnection, accomplishes different PCIE Switch configurations according to the system's demand.

The configuration file of the PCIE Switch is placed in a storage Flash of a BMC, topology switching can be realized only by changing the configuration file of one Switch, and the configuration file comprises two parts:

configuring a first step: PORT0 is connected to CPU as an upstream interface, PORT1 is not available, and 4 GPU devices are mounted under PORT 0.

Configuring a second step: PORT1 is connected as the upstream interface PCIE Switch0, PORT0 is not available, and 4 GPU devices are mounted under PORT 1.

Taking PCIE Switch1 as an example, in the case of configuration one, PORT1 of PCIE Switch1 is not available, and PORT0 is connected to CPU1 as an uplink interface, because PORT1 is not available, there is no connection between PCIE Switch1 and PCIE Switch0, so GPU4, GPU5, GPU6, and GPU7 communicate with CPU1 side via PORT0 of PCIE Switch1, and GPU0, GPU1, GPU2, and GPU3 communicate with CPU0 side via PORT0 of PCIE Switch 0.

Taking the PCIE Switch1 as an example, in the case of configuration two, the PORT0 of the PCIE Switch1 is not available, and the PORT1 thereof is connected to the PCIE Switch0 as an uplink interface, so the PORT1 of the PCIE Switch0 is connected to the PORT0 of the PCIE Switch1 as a downlink interface. GPU4, GPU5, GPU6, and GPU7 communicate with CPU0 via PCIE Switch1 and PCIE Switch0, respectively.

When the configuration I is used, the Balance mode is adopted, the method is suitable for a high-performance operation environment, and the configuration two-dimensional Cascade mode is used, and is suitable for deep learning. The switching of the two configurations can be automatically completed by depending on the BMC, a switching key is arranged under a BMC interface, a user can perform topology switching operation by pressing a key system, the system needs to be restarted and takes effect after the switching is completed, the system automatically completes the related restarting action, if the switching fails, the system cannot be down, the configuration before updating can be continuously operated, and the stability of the system is ensured.

In addition, the BMC can also detect the change of the bandwidth rate of each connected device of the PCIE Switch in real time, and the BMC sets a unique Slot number to each PCIE device through the PCIE Switch, so that if there is a problem of card loss due to device speed reduction, a problem point can be accurately located in real time.

The utility model discloses a BMC changes the configuration information of PCIE Switch as software control end through the UART, and then realizes the switching of topology, and PCIE Switch realizes two through changing the configuration file and goes upward mouthful configuration, and every goes upward the downstream equipment allocation that the definition that mouthful configuration can both be free corresponds, utilizes BMC to realize through UART and Switch interconnection that data transmission communicates and reaches the effect of accomplishing the configuration file update. The utility model discloses a BMC control key carries out topology switching, and supports PCIE4.0 equipment topology switching, and the operation is accomplished by software is automatic, does not need the physical connection change, and BMC can listen the bandwidth rate state of current topology in real time in addition, accurate location problem point.

The above description is only exemplary of the present invention and should not be taken as limiting the scope of the present invention, as any modifications, equivalents, improvements and the like made within the spirit and principles of the present invention are intended to be included within the scope of the present invention.

Claims (2)

1. A PCIE bus structure that switches topology through software, the PCIE bus structure comprising:

two CPUs, two PCIE switches, and eight GPU devices;

the CPU0 and the CPU1 are respectively connected to the PCIE Switch0 and the PCIE Switch1 through two PORTs 0 interfaces, the PCIE Switch0 and the PCIE Switch1 are respectively connected to the BMC through the UART, the PORTs 1 interfaces of the PCIE Switch0 and the PCIE Switch1 are connected to each other, and 4 GPU devices are respectively mounted under the PCIE Switch0 and the PCIE Switch 1.

2. The PCIE bus structure according to claim 1, wherein the two CPUs communicate with each other through a UPI.

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