CN103970626A

CN103970626A - Redundant design of FLASH for FPGA configuration in server system

Info

Publication number: CN103970626A
Application number: CN201410196226.3A
Authority: CN
Inventors: 吴浩; 薛广营; 张燕群; 赵江
Original assignee: Inspur Electronic Information Industry Co Ltd
Current assignee: Inspur Electronic Information Industry Co Ltd
Priority date: 2014-05-12
Filing date: 2014-05-12
Publication date: 2014-08-06

Abstract

The invention discloses a novel redundant design of FLASH for FPGA configuration in a server system. An SPI interface signal of an FPGA is connected to the FLASH of two SPI interfaces through a SWITCH, and the gating state of the SWITCH is controlled by shifting a switch of the SWITCH or by a BMC or PCH through a GPIO signal. When the FLASH breaks down or the BMC or PCH fails in upgrading and updating an FPGA program to cause starting failure, gating of a redundant FLASH link can be achieved through a BUTTON of the SWITCH. FPGA configuration is conducted by means of the redundant FLASH, so that the server system continues to work normally. In this way, FLASH redundancy for FPGA configuration is realized, the risk that a server can not work when the FLASH goes wrong is reduced, and the reliability of the server system is improved greatly.

Description

FPGA configuration FLASH Redundancy Design in a kind of server system

technical field

the present invention relates to FPGA collocation method field, specifically FPGA configuration FLASH Redundancy Design in a kind of server system.

Background technology

Generally in common server system only by a FLASH, FPGA is configured, and FPGA bears the most basic start and works on power.The Cyclone IV family device that the FPGA introducing is herein altera corp.This family device uses SRAM unit store configuration data.Due to the volatibility of SRAM internal memory, after each device powers on, all must configuration data be downloaded in Cyclone IV device by FLASH.In the time that FLASH breaks down, whole server system cannot be worked, and FLASH fault can only return factory change chip, will cause very big loss to user.When user uses BMC or PCH to upgrade renewal to FPGA, as unexpected power-off or program download version mistake, cause FLASH can not correctly configure FPGA if there is abnormal conditions.The server system start that can not normally power on, client cannot carry out the renewal of FPGA program upgrade again.Must upgrade the FPGA version in FLASH with special cd-rom recorder by burning interface.Consequent server cannot be worked and also will be brought massive losses to user.Therefore the FPGA realizing in server system configures FLSAH Redundancy Design by improving greatly the reliability of server system, by the trend that is server future development.

Summary of the invention

The present invention proposes the configuration FLSAH Redundancy Design of the FPGA in a kind of new server system.The SPI interface signal of FPGA connects the FLSAH to two SPI interfaces by SWITCH, by stirring the switch of SWITCH or passing through the strobe state of GPIO signal controlling SWITCH by BMC, PCH.When FLASH breaks down or when the situation that FPGA procedure failure causes starting shooting is upgraded in BMC, PCH upgrading, can be by the FLASH link of the BUTTON button gating redundancy of SWITCH.Utilize the FLASH of redundancy to be configured FPGA, make server system continue normal work.

The invention has the beneficial effects as follows:

When server needs different FPGA configuration, or the BMC of different editions or PCH are while needing specific FPGA configuration.Can select different FLASH to complete the switching to FPGA application configuration by control signal, and without program downloads repeatedly, the convenience that improves debugging and use.The present invention has realized the configuration FLSAH redundancy of FPGA, reduces FLASH inoperable risk of server while going wrong, has improved greatly the reliability of server system.

Brief description of the drawings

Accompanying drawing 1 is architectural framework figure of the present invention.

Embodiment

the suitable embodiment of this design is as follows:

1. the normal work of burning initial version program guarantee server in the FLASH of redundancy.

2. the program that can upgrade upgrading redaction in the FLASH of acquiescence, meets version requirement.

3. switching redundancy FLASH guarantee server by SWITCH when the FLASH cisco unity malfunction of acquiescence normally works.

If the FLASH of acquiescence does not damage, in the time using redundancy FLASH work, upgrading acquiescence FLASH program is normal procedure.

Claims

1. a FPGA configuration FLASH Redundancy Design in server system, is characterized in that

A, when the FLASH of acquiescence goes wrong and can not configure FPGA, can be configured FPGA by change-over switch gating redundancy FLASH, server can normally be used;

B, when by BMC, while upgrading upgrading FPGA version, there are abnormal conditions in PCH, while causing normally powering on start, can switch use initial version program in redundancy FLASH to power on program version that start continued in acquiescence FLASH upgrades upgrade job.