CN102736941A - Method for automatically starting central processing unit (CPU) system by utilizing double flashes - Google Patents
Method for automatically starting central processing unit (CPU) system by utilizing double flashes Download PDFInfo
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- CN102736941A CN102736941A CN2012102256314A CN201210225631A CN102736941A CN 102736941 A CN102736941 A CN 102736941A CN 2012102256314 A CN2012102256314 A CN 2012102256314A CN 201210225631 A CN201210225631 A CN 201210225631A CN 102736941 A CN102736941 A CN 102736941A
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Abstract
The invention relates to a method for automatically starting a central processing unit (CPU) system by utilizing double flashes. Two flashes are adopted to start the CPU, when a main flash fails to start the CPU, a complex program logic device (CPLD) selects a reserved flash and outputs a reset signal to the CPU so as to enable the CPU to be started from the reserved flash. The flash is required to upgrade after the CPU is started, the CPU sets that only an authorized user can start the CPULD to upgrade the reading and writing of the main and the reserved flashes, and thus the error operation of the user can be avoided, and the product reliability can be greatly improved. Due to the adoption of the method, under the situation that one flash cannot be started, the reserved flash can be automatically switched to guide the normal starting of the CPU, the normal starting of the CPU can be automatically and intelligently completed without adding the manual switching way such as a shifting code switch or a button, the main and the reserved flashes are automatically and intelligent switched, simplicity in operation is realized, the controllability is strong, and the reliability is high.
Description
Technical field
The present invention relates to the embedded type CPU system domain, especially relate to a kind of method that realizes automatically two FLASH startup cpu systems.
Background technology
Common practice was to adopt single FLASH to start the mode that guiding CPU loads bootrom and application version during current embedded system was used, and this mode is widely used at the embedded platform of communication facilities especially.This single FLASH starts the method for CPU; All be when plant produced, boot bootrom is burned onto among this FLASH, start by this bootrom guiding application program then; This bootrom can pass through serial ports after the startup; Network interface and other interface thereof carry out online upgrading to bootrom and application program, will exist like this owing to following reason causes the system start-up failure, must just can deal with problems through time factory burning again: 1, when upgrading bootrom; When sudden power or other reason upgrading failure, cause boot error; 2, the own problem of FLASH chip, after certain read-write number of times, mistake appears in some zone of FLASH, causes the guiding failure; The bootrom program of staging error causes starting failure to FLASH.In case bootrom can't start,, cause significant trouble to the project implementation because the scene can't perhaps be recovered by rollback.
Summary of the invention
The object of the invention just provide a kind of simple to operate, controllability is strong, safe and reliable, and the automatically two FLASH of realization that can intelligence switch start the method for cpu systems.
The automatically two FLASH of realization of the present invention start the method for cpu system, may further comprise the steps:
Master FLASH1 and be equipped with all burning start-up code of FLASH2 when 1, dispatching from the factory; The CPLD internal reset began initialization after system powered on, and after the CPLD initialization was accomplished, CPLD selected CS# to switch to default conditions CS1# sheet; Promptly main FLASH1 is selected; CPLD output this moment reset signal is given CPU, after cpu reset is accomplished, begins from main FLASH reading of data and accomplishes initialization.
2, after the normal startup of CPU, export continuous WDO signal and give CPLD, after CPLD received the WDO signal, CPU loaded successfully, and whole process finishes; Do not receive the WDO signal that CPU provides like CPLD, suppose that CPU initialization completion needs 15 seconds, if do not send the WDO signal in 30 seconds behind the cpu reset to CPLD; Then CPLD assert the abnormal startup of CPU, opens subsequent use FLASH2, selects CS# to switch to CS2# sheet; Cpu system then resets; After cpu reset is accomplished, begin from be equipped with FLASH2 reading of data and accomplish initialization, after the CPLD output reset signal; Alarm signal is drawn high, the alarm led lamp is lighted informed with householder FLASH1 and be destroyed.
3, when the new start-up code of needs upgradings, the user must obtain manufacturer and authorize and obtain operational order and could pass through the start-up code among the CPU online upgrading program updates FLASH, by CPU output enable signal ENABLE#; Be about to ENABLE# and drag down, after CPLD detects ENABLE# and is low level, the change-over switch of sheet choosing is transferred to CPU control; This moment, CPLD detected the LOW/HIGHT signal, if CPU draws high the LOW/HIGHT signal, explained that CPU need operate main FLASH1; The sheet that CPLD sends CPU selects CS# to switch to CS1#, promptly chooses main FLASH1, and CPU carries out on-line software updating through order line to main FLASH1 then; After upgrading is accomplished ENABLE# drawn high and withdraw from upgrade step, through order line CPU is write the reseting register mode cpu system that resets, explanation is upgraded successfully if CPU can normally get up; If the upgrading back has started not; Explain that upgrade code has problem, CPLD will automatically switch to fully that FLASH2 starts, and repeat above-mentioned steps then and carry out main FLASH1 and upgrade; If CPU drags down the LOW/HIGHT signal; Explain that CPU need operate FLASH2 fully, the sheet that CPLD sends CPU selects CS# to switch to CS2#, promptly chooses FLASH2 fully; CPU carries out on-line software updating through order line to main FLASH1 then, and warm reset CPU was restarted system after upgrading was accomplished; Behind the system upgrade, the user needs cpu command is drawn high the LOW/HIGHT signal, and the sheet that CPLD sends CPU selects CS# to switch to CS1#, promptly chooses main FLASH1, and the CPLD cleared alarm drags down alarm signal then, the resuming default state.
The automatically two FLASH of realization of the present invention start the method for cpu system, two FLASH, CPU; CPLD (steering logic able to programme), after wherein main FLASH starts the CPU failure, said CPLD will confirm the normal start-up time of a regulation according to own timer own; Under normal circumstances CPU has accomplished initialization during this period of time, and sends the consecutive pulses square wave through feeding-dog signal WDO and give CPLD, if CPU is not after can starting through main leaf FLASH; CPU hangs up can not send the WDO signal; After exceeding schedule time, CPLD will back up FLASH and choose and export reset signal to CPU, let CPU start from backup FLASH.After if CPLD switches to backup FLASH, the outputting alarm signal is lighted external LED lamp notice and can't normally be started with householder FLASH.In addition,, CPU needs upgrading FLASH after starting, in order to prevent maloperation; CPU normally sends under the WDO RST after starting; CPU is provided with the user who has only mandate just can enable the read-write upgrading of CPLD startup to active and standby FLASH, otherwise CPLD will cut off the sheet choosing of FLASH, make CPU after starting operate as normal, can't visit FLASH; This mode has been avoided misoperation of users, has greatly improved reliability of products.
The automatically two FLASH of realization of the present invention start the method for cpu system; Can guarantee that therein automatically switching to backup FLASH guiding CPU under the situation that a FLASH can't start normally starts; Need not to add the just normal startup of ability automated intelligent completion CPU of manual switchover modes such as toggle switch or button, can also provide automatic alarm function to inform after starting by backup FLASH and start unusually the FLASH that the user can also upgrade and need upgrade through cpu instruction under authorization conditions with householder FLASH; Active and standby FLASH automated intelligent switches; Simple to operate, controllability is strong, and reliability is high.
Description of drawings
Fig. 1 is the whole logic diagram of realizing of the present invention;
Fig. 2 is part control of the present invention and alarm schematic diagram;
Fig. 3 is switching principle figure between 2 FLASH of the present invention.
Embodiment
Below in conjunction with accompanying drawing and instantiation the present invention is done further detailed description.
A kind of method that realizes automatically two FLASH startup cpu systems, two FLASH have start-up routine bootrom and the complete application program of total system in burnings of dispatching from the factory before.
As shown in Figure 2, the control schematic diagram of shaking hands between CPU that the present invention adopts and the CPLD, the RESET# among the figure are the reset reset signal of whole C PU system of CPLD; WDO is that cpu system starts the feeding-dog signal of exporting to CPLD after initialization is accomplished, can be the pulsating wave of cycle 1S.ENABLE# is that the user that obtains the authorization drags down this signal through order control CPU when needing upgrading FLASH and enables upgrade function, and CPLD confirms to select CS# to switch to CS1# or CS2# the CPU sheet through reading the LOW/HIGHT signal then; As shown in Figure 3, the suitable change-over switch of CPLD in Fig. 3 is if CPU is changed to high level (acquiescence) with LOW/HIGHT; CPLD links to each other CS# with CS1#, choose main FLASH, if CPU is changed to low level with LOW/HIGHT; CPLD links to each other CS# with CS2#; Choose FLASH fully, like this through the control between CPU and the CPLD, the user need can select the FLASH of upgrading as required.
The present invention adopts two FLASH: main FLASH be equipped with FLASH; Be FLASH1 and the FLASH2 in the accompanying drawing 3; FLASH1 is as main FLASH; The startup of CPU all is to accomplish from this sheet reading order to start generally speaking, promptly is equipped with FLASH guiding startup as if just switching to FLASH2 after the main leaf guiding CPU startup failure.These two FLASH are when production is dispatched from the factory, and the code that burning is the same guarantees that two mirror images among the FLASH are the same.
Concrete grammar is:
Master FLASH1 and be equipped with all V1.0 of burning start-up code versions of FLASH2 when 1, dispatching from the factory; The CPLD internal reset began initialization after system powered on, and after the CPLD initialization was accomplished, CPLD selected CS# to switch to default conditions CS1# sheet; Promptly main FLASH1 is selected; CPLD output this moment reset signal is given CPU, after cpu reset is accomplished, begins from main FLASH reading of data and accomplishes initialization.
2, after the normal startup of CPU, export continuous WDO signal and give CPLD, after CPLD received the WDO signal, CPU loaded successfully, and whole process finishes; Do not receive the WDO signal that CPU provides like CPLD, suppose that CPU initialization completion needs 15 seconds, if do not send the WDO signal in 30 seconds behind the cpu reset to CPLD; Then CPLD assert the abnormal startup of CPU, opens subsequent use FLASH2, selects CS# to switch to CS2# sheet; Cpu system then resets; After cpu reset is accomplished, begin from be equipped with FLASH2 reading of data and accomplish initialization, after the CPLD output reset signal; Alarm signal is drawn high, the alarm led lamp is lighted informed with householder FLASH1 and be destroyed.
3, when the new start-up code of needs upgradings, the user must obtain manufacturer and authorize and obtain operational order and could pass through the start-up code among the CPU online upgrading program updates FLASH, by CPU output enable signal ENABLE#; Be about to ENABLE# and drag down, after CPLD detects ENABLE# and is low level, the change-over switch of sheet choosing is transferred to CPU control; This moment, CPLD detected the LOW/HIGHT signal, if CPU draws high the LOW/HIGHT signal, explained that CPU need operate main FLASH1; The sheet that CPLD sends CPU selects CS# to switch to CS1#, promptly chooses main FLASH1, and CPU carries out on-line software updating through order line to main FLASH1 then; After upgrading is accomplished ENABLE# drawn high and withdraw from upgrade step, through order line CPU is write the reseting register mode cpu system that resets, explanation is upgraded successfully if CPU can normally get up; If the upgrading back has started not; Explain that upgrade code has problem, CPLD will automatically switch to fully that FLASH2 starts, and repeat above-mentioned steps then and carry out main FLASH1 and upgrade; If CPU drags down the LOW/HIGHT signal; Explain that CPU need operate FLASH2 fully, the sheet that CPLD sends CPU selects CS# to switch to CS2#, promptly chooses FLASH2 fully; CPU carries out on-line software updating through order line to main FLASH1 then, and warm reset CPU was restarted system after upgrading was accomplished; Behind the system upgrade, the user needs cpu command is drawn high the LOW/HIGHT signal, and the sheet that CPLD sends CPU selects CS# to switch to CS1#, promptly chooses main FLASH1, and the CPLD cleared alarm drags down alarm signal then, the resuming default state.
Claims (1)
1. realize that automatically two FLASH start the method for cpu system for one kind, it is characterized in that: it may further comprise the steps:
Master FLASH1 and be equipped with all burning start-up code of FLASH2 when (1), dispatching from the factory; The CPLD internal reset began initialization after system powered on; After the CPLD initialization is accomplished; CPLD selects CS# to switch to default conditions CS1# sheet; Promptly main FLASH1 is selected; CPLD output this moment reset signal is given CPU, and cpu reset begins from main FLASH, to read data and accomplish initialization after accomplishing;
(2), CPU is normal start after, export continuous WDO signal and give CPLD, after CPLD received the WDO signal, CPU loaded successfully, whole process end; Do not receive the WDO signal that CPU provides like CPLD, then CPLD assert the abnormal startup of CPU, opens subsequent use FLASH2; Select CS# to switch to CS2# sheet, the cpu system that resets then is after cpu reset is accomplished; Begin from be equipped with FLASH2 reading of data and accomplish initialization; After the CPLD output reset signal, alarm signal is drawn high, the alarm led lamp is lighted informed with householder FLASH1 and be destroyed;
(3), when the new start-up code of needs upgradings, the user must obtain manufacturer and authorize and obtain operational order and could pass through the start-up code among the CPU online upgrading program updates FLASH, by CPU output enable signal ENABLE#; Be about to ENABLE# and drag down, after CPLD detects ENABLE# and is low level, the change-over switch of sheet choosing is transferred to CPU control; This moment, CPLD detected the LOW/HIGHT signal, if CPU draws high the LOW/HIGHT signal, explained that CPU need operate main FLASH1; The sheet that CPLD sends CPU selects CS# to switch to CS1#, promptly chooses main FLASH1, and CPU carries out on-line software updating through order line to main FLASH1 then; After upgrading is accomplished, ENABLE# drawn high withdraw from upgrade step, CPU is write the reseting register mode cpu system that resets through order line; Explanation is upgraded successfully if CPU can normally get up; If upgrading back has started not, CPLD will automatically switch to fully that FLASH2 starts, and repeat above-mentioned steps then and carry out main FLASH1 and upgrade; If CPU drags down the LOW/HIGHT signal; Explain that CPU need operate FLASH2 fully, the sheet that CPLD sends CPU selects CS# to switch to CS2#, promptly chooses FLASH2 fully; CPU carries out on-line software updating through order line to main FLASH1 then, and warm reset CPU was restarted system after upgrading was accomplished; Behind the system upgrade, the user needs cpu command is drawn high the LOW/HIGHT signal, and the sheet that CPLD sends CPU selects CS# to switch to CS1#, promptly chooses main FLASH1, and the CPLD cleared alarm drags down alarm signal then, the resuming default state.
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Cited By (12)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN102880496A (en) * | 2012-10-18 | 2013-01-16 | 上海师范大学 | Embedded multisystem self-starting method |
| CN104035784A (en) * | 2014-06-30 | 2014-09-10 | 普联技术有限公司 | Device starting system and method |
| CN106325857A (en) * | 2016-08-11 | 2017-01-11 | 迈普通信技术股份有限公司 | Electronic equipment and electronic equipment control method |
| CN106775610A (en) * | 2016-03-22 | 2017-05-31 | 新华三技术有限公司 | A kind of electronic equipment starts method and a kind of electronic equipment |
| CN108427611A (en) * | 2017-02-14 | 2018-08-21 | 北京国基科技股份有限公司 | A kind of cloud terminal system dual redundant intelligent starting method and device |
| CN112084064A (en) * | 2020-08-05 | 2020-12-15 | 锐捷网络股份有限公司 | Master-slave BIOS switching method, board card and equipment |
| CN112181526A (en) * | 2020-09-30 | 2021-01-05 | 锐捷网络股份有限公司 | Equipment starting method and device |
| CN112346910A (en) * | 2020-11-12 | 2021-02-09 | 盛科网络（苏州）有限公司 | Starting backup method of CPU module, ATCA single board, equipment and storage medium |
| CN114003299A (en) * | 2020-07-27 | 2022-02-01 | 中车株洲电力机车研究所有限公司 | Starting method, device and system for central processing unit |
| CN114489817A (en) * | 2021-12-28 | 2022-05-13 | 深圳市腾芯通智能科技有限公司 | Processor starting method, device, equipment and storage medium |
| CN114528557A (en) * | 2022-02-28 | 2022-05-24 | 合肥中科爱观电子技术有限公司 | Self-adaptive starting method of embedded SOC chip |
| CN114661655A (en) * | 2022-05-25 | 2022-06-24 | 天津讯联科技有限公司 | FPGA (field programmable Gate array) program on-track reconstruction system and method for satellite-borne measurement and control data transmission all-in-one machine |
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| Publication number | Priority date | Publication date | Assignee | Title |
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| CN104035784A (en) * | 2014-06-30 | 2014-09-10 | 普联技术有限公司 | Device starting system and method |
| CN106775610A (en) * | 2016-03-22 | 2017-05-31 | 新华三技术有限公司 | A kind of electronic equipment starts method and a kind of electronic equipment |
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| CN108427611A (en) * | 2017-02-14 | 2018-08-21 | 北京国基科技股份有限公司 | A kind of cloud terminal system dual redundant intelligent starting method and device |
| CN114003299A (en) * | 2020-07-27 | 2022-02-01 | 中车株洲电力机车研究所有限公司 | Starting method, device and system for central processing unit |
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| CN112084064A (en) * | 2020-08-05 | 2020-12-15 | 锐捷网络股份有限公司 | Master-slave BIOS switching method, board card and equipment |
| CN112084064B (en) * | 2020-08-05 | 2023-03-31 | 锐捷网络股份有限公司 | Master-slave BIOS switching method, board card and equipment |
| CN112181526A (en) * | 2020-09-30 | 2021-01-05 | 锐捷网络股份有限公司 | Equipment starting method and device |
| CN112346910A (en) * | 2020-11-12 | 2021-02-09 | 盛科网络（苏州）有限公司 | Starting backup method of CPU module, ATCA single board, equipment and storage medium |
| CN114489817A (en) * | 2021-12-28 | 2022-05-13 | 深圳市腾芯通智能科技有限公司 | Processor starting method, device, equipment and storage medium |
| CN114528557A (en) * | 2022-02-28 | 2022-05-24 | 合肥中科爱观电子技术有限公司 | Self-adaptive starting method of embedded SOC chip |
| CN114661655A (en) * | 2022-05-25 | 2022-06-24 | 天津讯联科技有限公司 | FPGA (field programmable Gate array) program on-track reconstruction system and method for satellite-borne measurement and control data transmission all-in-one machine |
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Application publication date: 20121017 |