CN101697130A - Application method of watchdog of embedded system - Google Patents
Application method of watchdog of embedded system Download PDFInfo
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- CN101697130A CN101697130A CN200910193318A CN200910193318A CN101697130A CN 101697130 A CN101697130 A CN 101697130A CN 200910193318 A CN200910193318 A CN 200910193318A CN 200910193318 A CN200910193318 A CN 200910193318A CN 101697130 A CN101697130 A CN 101697130A
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- house dog
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Abstract
The invention provides an application method of a watchdog of an embedded system. A watchdog chip is controlled by a timer, wherein the timer corresponds to the needed time when the embedded system starts and controls the watchdog chip to stop sending a reset signal in the determined time. The application method of the watchdog of the embedded system can be realized by FPGA or CPLD; few FPGAs or CPLDs are needed and dozens of triggers are enough; and therefore, for the system which is provided with FPGA or CPLD, the flexible watchdog function is easy to realize.
Description
Technical field
The invention belongs to the startup and the safety technique field of embedded system, particularly relate to a kind of application method of watchdog of embedded system.
Background technology
General embedded device system software part all can be divided into several sections: boot (Bootloader), kernel (Kernel) and file system (File System).The order of starting of embedded operation system generally is such: after powering on, the system reset chip can reset whole hardware system, the address start of back CPU from acquiescence that finish resets, what deposited this address is boot, boot is mainly finished some necessary initialization such as peripheral hardware and internal memory, kernel can be imported to internal memory afterwards, if kernel be compress mode storage also need to carry out decompress(ion), begin to carry out kernel after decompression finishes, kernel is understood the carry file system at last.This start-up course is a quite loaded down with trivial details process, needs the cost regular hour.With regard to (SuSE) Linux OS, the kernel of common complexity generally needed for tens seconds to tens seconds, complicated, need carry more time of kernel needs of multimode just longer.
Can there be problem for having increased the system that house dog relates to so in order to ensure system stable operation, be exactly dog cycle of feeding of requiring of at present common watchdog chip all shorter, generally be to feed dog at least one time 2 seconds, otherwise watchdog chip will produce system reset.That is to say in order to ensure house dog can not produce system reset that will carry out dog feeding operation one time every 2 seconds in the time of os starting, this is very difficult the realization in os starting.Need carry out dog feeding operation one time after certain execution time of estimation, not include the error of evaluation time earlier, only update routine is just enough loaded down with trivial details.If the kernel that runs into compression is trouble more just.
Along with the reduction of FPGA/CPLD cost and the enhancing day by day of function, all can have FPGA/CPLD in the design of a lot of embedded devices, be used for doing some system's controls.So can utilize the advantage of FPGA/CPLD that house dog is improved, to overcome the defective of prior art.
Summary of the invention
The objective of the invention is to overcome the deficiencies in the prior art, a kind of band loaded down with trivial details dog feeding operation of hardware watchdog system in the time of os starting that reduce is provided, and the application method of watchdog of the embedded system that can not reset in start-up course.
In order to realize the foregoing invention purpose, the technical scheme of employing is as follows:
A kind of application method of watchdog of embedded system, by timer control watchdog chip is set, required time when the corresponding embedded system of described timer starts, and stop to send reset signal at the time inner control watchdog chip of determining.
The present invention controls the action of watchdog chip by timer is set, when os starting, timer is implemented in and starts in the required time, the control watchdog chip stops to send reset signal, that is to say, when starting, there is not dog feeding operation can not cause watchdog chip to reset yet, guaranteed the stability and the agility of system start-up.
In the technique scheme, the time of described timer can customize, and needs different durations to be suitable for when different embedded systems starts, and guarantees that house dog can not reset before startup finishes.Because different embedded systems, the start-up time of its operating system is also inequality, so by adopting the timer of customizable time, just can set different timing times according to different embedded systems, guarantees that the present invention can be applicable in the different systems.
Further, described timer also comprises second timer, and described second timer has customized the maximum time difference of adjacent twice dog feeding operation, and if do not have dog feeding operation in the time difference then control house dog to start reset operation in this maximum.
Described timer also comprises the 3rd timer, and described the 3rd timer has customized the time that watchdog reset comes into force, to satisfy the different demands of different embedded systems for the duration that resets.
Concrete operations of the present invention are: after embedded system powers on, can produce power-on reset signal, house dog carries out timing by timer after receiving this signal, and timer guarantees that os starting finishes, and application program is taken over house dog afterwards, if in the time that second timer is formulated, application program does not have dog feeding operation, and house dog will produce reset signal and remove resetting system, and reset time is by the decision of the 3rd timer, reset and come back to the electrification reset state again, repetitive operation after finishing.
The present invention can realize by FPGA or CPLD, needed FPGA or CPLD resource are considerably less, the resource of tens triggers is just enough, therefore for the system that has been equipped with FPGA or CPLD, realize this flexibly watchdog function be unusual nothing the matter feelings.
Description of drawings
Fig. 1 is an operational flowchart of the present invention.
Embodiment
The present invention is described further below in conjunction with accompanying drawing.
Operational flowchart of the present invention as shown in Figure 1.Adopt the Verilog logic programming language to realize that Fig. 1 represents the duty flow process of house dog, described and from the system power-on reset to the os starting, finish and the dog feeding operation flow process of application program after this.Being described below of various piece among the figure:
Timing 1: this time is customizable, and according to the different duration of system's employing of differing complexity, this timer can guarantee that house dog can resetting system before os starting finishes.
Timing 2: duration also is customizable, has customized the maximum time difference of adjacent twice dog feeding operation, and operating this time does not have dog feeding operation will cause watchdog reset to come into force system restart.
Timing 3: this timing duration equally can customize, and the time of having represented watchdog reset to come into force, different system has different demands for the duration that resets, and this also can be finished flexibly.
Being described below of the whole flow process of the present invention:
After system powers on, can produce electrification reset, house dog carries out timing (timing 1) after receiving this signal, timing 1 can guarantee that os starting finishes (in the time of timing 1, even if there is not dog feeding operation, house dog can not produce reset signal yet), application program is taken over house dog afterwards; If in the fixed time (timing 2), application program is fed dog, and house dog can produce reset signal and remove resetting system, determines by timing 3 reset time, resets to come back to the electrification reset state again after finishing, and repeats aforesaid operations then.
After using present technique, the os starting of band hardware watchdog system becomes simply, and the configuration of all multiparameters makes to use and becomes more flexible.
Claims (6)
1. the application method of watchdog of an embedded system, it is characterized in that by timer control watchdog chip is set, required time when the corresponding embedded system of described timer starts, and stop to send reset signal at the time inner control watchdog chip of determining.
2. application method of watchdog according to claim 1 is characterized in that the time of described timer can customize, and needs different durations to be suitable for when different embedded systems starts, and guarantees that house dog can not reset before startup finishes.
3. the application process of house dog according to claim 1 and 2, it is characterized in that described timer also comprises second timer, described second timer has customized the maximum time difference of adjacent twice dog feeding operation, and if do not have dog feeding operation in the time difference then control house dog to start reset operation in this maximum.
4. the application process of house dog according to claim 3, it is characterized in that described timer also comprises the 3rd timer, described the 3rd timer has customized the time that watchdog reset comes into force, to satisfy the different demands of different embedded systems for the duration that resets.
5. the application process of house dog according to claim 4, it is characterized in that concrete operations are: after embedded system powers on, can produce power-on reset signal, house dog carries out timing by timer after receiving this signal, timer guarantees that os starting finishes, application program is taken over house dog afterwards, if in the time that second timer is formulated, application program does not have dog feeding operation, house dog will produce reset signal and remove resetting system, reset time is by the 3rd timer decision, resets to come back to the electrification reset state again, repetitive operation after finishing.
6. the application process of house dog according to claim 1 is characterized in that described watchdog chip and timer are by FPGA or CPLD realization.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN200910193318A CN101697130A (en) | 2009-10-26 | 2009-10-26 | Application method of watchdog of embedded system |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN200910193318A CN101697130A (en) | 2009-10-26 | 2009-10-26 | Application method of watchdog of embedded system |
Publications (1)
| Publication Number | Publication Date |
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| CN101697130A true CN101697130A (en) | 2010-04-21 |
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| Application Number | Title | Priority Date | Filing Date |
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| CN200910193318A Pending CN101697130A (en) | 2009-10-26 | 2009-10-26 | Application method of watchdog of embedded system |
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Cited By (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN105897618A (en) * | 2016-04-01 | 2016-08-24 | 上海斐讯数据通信技术有限公司 | Reset circuit device of switch |
| CN106326055A (en) * | 2016-08-29 | 2017-01-11 | 四川九洲空管科技有限责任公司 | Method for software and hardware crashing detection and resetting of airborne collision avoidance system |
| CN107133119A (en) * | 2017-05-02 | 2017-09-05 | 郑州云海信息技术有限公司 | A kind of method that hardware watchdog function is realized by CPLD |
| CN112783070A (en) * | 2021-01-20 | 2021-05-11 | 深圳市雷能混合集成电路有限公司 | Singlechip power-on processing method and device |
-
2009
- 2009-10-26 CN CN200910193318A patent/CN101697130A/en active Pending
Cited By (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN105897618A (en) * | 2016-04-01 | 2016-08-24 | 上海斐讯数据通信技术有限公司 | Reset circuit device of switch |
| CN106326055A (en) * | 2016-08-29 | 2017-01-11 | 四川九洲空管科技有限责任公司 | Method for software and hardware crashing detection and resetting of airborne collision avoidance system |
| CN106326055B (en) * | 2016-08-29 | 2019-11-12 | 四川九洲空管科技有限责任公司 | A kind of hardware of airborne collision avoidance system crashes detection and repositioning method |
| CN107133119A (en) * | 2017-05-02 | 2017-09-05 | 郑州云海信息技术有限公司 | A kind of method that hardware watchdog function is realized by CPLD |
| CN112783070A (en) * | 2021-01-20 | 2021-05-11 | 深圳市雷能混合集成电路有限公司 | Singlechip power-on processing method and device |
| CN112783070B (en) * | 2021-01-20 | 2024-05-07 | 深圳市雷能混合集成电路有限公司 | Singlechip power-on processing method and device |
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Application publication date: 20100421 |