CN218974903U - Domestic server BIOS firmware backup device - Google Patents

Domestic server BIOS firmware backup device Download PDF

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CN218974903U
CN218974903U CN202223055819.7U CN202223055819U CN218974903U CN 218974903 U CN218974903 U CN 218974903U CN 202223055819 U CN202223055819 U CN 202223055819U CN 218974903 U CN218974903 U CN 218974903U
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bios
cpld
bmc
cpu
signal switcher
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王谦
郭晴晴
马小锋
陈艳飞
缪少军
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CETC 52 Research Institute
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CETC 52 Research Institute
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    • Y02D—CLIMATE CHANGE MITIGATION TECHNOLOGIES IN INFORMATION AND COMMUNICATION TECHNOLOGIES [ICT], I.E. INFORMATION AND COMMUNICATION TECHNOLOGIES AIMING AT THE REDUCTION OF THEIR OWN ENERGY USE
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Abstract

The utility model discloses a domestic server BIOS firmware backup device, which comprises a central processing module CPU, a baseboard management controller BMC, a complex editable logic module CPLD and a switching control module, wherein: the CRU_I2C interface of the CPU is connected with the BMC, the BMC is configured as a master device, and the CPU is configured as a slave device. The domestic server BIOS firmware backup device realizes the switching process of the main BIOS and the standby BIOS without manual intervention through the cooperation among the CPU, the CPLD and the BMC, automatically switches, sets the mirror image A and the mirror image B in each BIOS, reduces the possibility of BIOS damage through realizing the switching between the mirror image A and the mirror image B, and further ensures the normal operation of the whole system; the domestic server BIOS firmware backup device realizes the remote updating of the main BIOS or the standby BIOS with faults by sending SPI signals of the BIOS to the main BIOS or the standby BIOS, and realizes the elimination of the faults.

Description

Domestic server BIOS firmware backup device
Technical Field
The utility model belongs to the field of servers, and particularly relates to a domestic server BIOS firmware backup device.
Background
Along with the rapid development of domestic chips and domestic server products, the functions and the reliability of the domestic server products are continuously perfected and improved. BIOS (Basic Input/Output System) firmware is used as the most Basic program of a server motherboard, and the server needs to boot into the System through the BIOS after starting. Therefore, when the BIOS fails or is abnormal, the system cannot be started normally, and the reliable operation of the whole system can be seriously affected.
Disclosure of Invention
The utility model aims to solve the problems in the background technology and provides a domestic server BIOS firmware backup device.
In order to achieve the above purpose, the technical scheme adopted by the utility model is as follows:
the utility model provides a domestic server BIOS firmware backup device, which comprises a central processing module CPU, a baseboard management controller BMC, a complex editable logic module CPLD and a switching control module, wherein:
the CRU_I2C interface of the CPU is connected with the BMC, the BMC is configured as a master device, and the CPU is configured as a slave device.
The switching control module comprises an SPI signal switcher, a CS signal switcher, a main BIOS and a standby BIOS; the input end of the SPI signal switcher is respectively connected with SPI signals of the CPU and the BMC, and the output end of the SPI signal switcher is respectively connected with the input ends of the main BIOS, the standby BIOS and the CS signal switcher; the output end of the CS signal switcher is respectively connected with the main BIOS and the standby BIOS; the control ends of the SPI signal switcher and the CS signal switcher are respectively connected with the CPLD.
The SPI interface of BMC is connected to CPLD, is connected to SPI signal switch's input through CPLD.
The GPIO pins of the CPLD are respectively connected to the control ends of the SPI signal switcher and the CS signal switcher and respectively control the switching of the SPI signal switcher and the CS signal switcher.
The first I2C interface of the CPU is connected with the CPLD.
Preferably, the main BIOS and the standby BIOS each comprise an independent image A and an independent image B, and each image A and each image B are connected with the output end of the SPI signal switcher and the output end of the CS signal switcher.
Preferably, the CPU is further provided with a first LPC interface, and the first LPC interface is connected with the CPLD.
Preferably, the CPU is further provided with an scp_recovery interface, and the scp_recovery interface is connected to the CPLD.
Preferably, a second LPC interface is further arranged on the BMC, and the second LPC interface is connected with the CPLD.
Preferably, the BMC and the CPLD are both provided with a second I2C interface, and the two second I2C interfaces are mutually connected.
Preferably, the GPIO pin of the CPLD is also connected to the BMC.
Compared with the prior art, the utility model has the beneficial effects that:
1. the domestic server BIOS firmware backup device realizes the switching process of the main BIOS and the standby BIOS without manual intervention through the cooperation among the CPU, the CPLD and the BMC, automatically switches, sets the mirror image A and the mirror image B in each BIOS, reduces the possibility of BIOS damage through realizing the switching between the mirror image A and the mirror image B, and further ensures the normal operation of the whole system;
2. the domestic server BIOS firmware backup device realizes the remote updating of the main BIOS or the standby BIOS with faults by sending SPI signals of the BIOS to the main BIOS or the standby BIOS, and realizes the elimination of the faults.
Drawings
Fig. 1 is a block diagram of a backup device for BIOS firmware of a home server according to the present utility model.
Detailed Description
The following description of the technical solutions in the embodiments of the present application will be made clearly and completely with reference to the drawings in the embodiments of the present application, and it is apparent that the described embodiments are only some embodiments of the present application, not all embodiments. All other embodiments, which can be made by one of ordinary skill in the art without undue burden from the present disclosure, are within the scope of the present disclosure.
It will be understood that when an element is referred to as being "connected" to another element, it can be directly connected to the other element or intervening elements may also be present. Unless defined otherwise, all technical and scientific terms used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this application belongs. The terminology used herein in the description of the present application is for the purpose of describing particular embodiments only and is not intended to be limiting of the application.
As shown in fig. 1, a backup device for BIOS firmware of a domestic server includes a central processing module CPU, a baseboard management controller BMC, a complex editable logic module CPLD, and a switching control module, wherein:
the CRU_I2C interface of the CPU is connected with the BMC, the BMC is configured as a master device, and the CPU is configured as a slave device.
The switching control module comprises an SPI signal switcher, a CS signal switcher, a main BIOS and a standby BIOS; the input end of the SPI signal switcher is respectively connected with SPI signals of the CPU and the BMC, and the output end of the SPI signal switcher is respectively connected with the input ends of the main BIOS, the standby BIOS and the CS signal switcher; the output end of the CS signal switcher is respectively connected with the main BIOS and the standby BIOS; the control ends of the SPI signal switcher and the CS signal switcher are respectively connected with the CPLD.
The SPI interface of BMC is connected to CPLD, is connected to SPI signal switch's input through CPLD.
The GPIO pins of the CPLD are respectively connected to the control ends of the SPI signal switcher and the CS signal switcher and respectively control the switching of the SPI signal switcher and the CS signal switcher.
The first I2C interface of the CPU is connected with the CPLD.
Specifically, complex editable logic modules (CPLD, complex Programmable Logic Device), baseboard management controllers (BMC, baseboard Management Controller). In this embodiment, the number of CPUs is two, but the number is not limited, and the CPUs are all flying, and each CPU has a switching control module paired with the CPU. The CRU_I2C interface of the CPU is connected with the BMC, the BMC is used as a master device, the CPU initialization log can be obtained based on IPMB standard protocol communication, the alarm type of the CPU initialization failure is judged, and whether the CPLD controls and switches the SPI signal switcher and the CS signal switcher is indicated. The SPI signal of the BMC is connected to the CPLD, and the CPLD is connected to the input end of the SPI signal switcher, so that the BMC can remotely update BIOS firmware files of a plurality of CPUs by switching the SPI signal of the BMC to each BIOS of the plurality of CPUs through the CPLD. The CPLD controls the switching of the SPI signal switcher through the GPIO interface to realize that the SPI signal of the CPU or the BMC is sent to the main BIOS or the standby BIOS, and realizes that the SPI signal of the slave CPU or the slave BMC controls the read-write of the BIOS FLASH. And the CPLD controls the switching of the CS signal switcher through the GPIO interface, so that the CS signal is selected from the SPI signal of the CPU or the BMC and is output to the main BIOS or the standby BIOS. The first I2C interface of the CPU is connected with the CPLD, the CPLD can receive CPU starting information, judge whether the starting of each BIOS fails and the failure type, and judge whether the main BIOS or the standby BIOS needs to be switched.
In one embodiment, the main BIOS and the standby BIOS each comprise an independent mirror image A and an independent mirror image B, and each mirror image A and each mirror image B are connected with the output end of the SPI signal switcher and the output end of the CS signal switcher.
Specifically, by setting the image a and the image B, when the image a fails, a signal can be sent to the image B, and when the image B fails, a signal can be sent to the image a.
In one embodiment, the CPU is further provided with a first LPC interface, and the first LPC interface is connected to the CPLD.
In one embodiment, a second LPC interface is further provided on the BMC, and the second LPC interface is connected to the CPLD.
Specifically, the CPLD connects the first LPC interface of the multiple CPUs through connecting the first LPC interface and the second LPC interface, so that the second LPC interface of the BMC can flexibly switch and connect the first LPC interface of the multiple CPUs, when a certain mirror image started by the BIOS is destroyed, the CPU may hang up in the starting process, in this process, the CPU starts up the postcode information through the first LPC interface (it is to be noted that the CPU starts up multiple nodes, each node corresponds to one postcode information, when the starting is unsuccessful, the last postcode information can be blocked, at this time, the transmitted postcode information can be known to be blocked at that stage and analyzed), the CPLD then sends the postcode information to the BMC or the BMC actively queries the postcode information, and then the BMC determines whether the mirror image needs to be switched according to the postcode information.
In one embodiment, the CPU is further provided with an scp_recovery interface, which is connected to the CPLD.
Specifically, if it is confirmed that the mirror image needs to be switched, the BMC performs the mirror image switching operation by notifying the CLPD to set the level state of the scp_RECTOVER, and the mirror image switching needs to power up and power down the CPU again, so that the standby mirror image can be restarted.
In one embodiment, the BMC and the CPLD are both provided with second I2C interfaces, and the two second I2C interfaces are connected to each other.
Specifically, the command issued by the BMC to the CPLD is via a second I2C interface interconnected between the BMC and the CPLD.
In one embodiment, the GPIO pin of the CPLD is also connected to the BMC.
Specifically, the CPLD is connected to the BMC through the GPIO (such as GPIO0, GPIO1, GPIO2 in fig. 1), receives a signal sent by the BMC, determines whether the operation of the BMC is abnormal, and controls the SPI signal switcher to select the CPU or the SPI signal of the BMC, so that the CPLD can be instructed to disregard the received signal sent by the BMC when the operation abnormality of the BMC is detected; when detecting that the BMC works normally, the CPLD can control the SPI signal switcher to acquire a CS signal from the SPI signal of the BMC or the CPU and send the CS signal to the CS signal switcher, and control the CS signal selector to select to switch to the main BIOS or the standby BIOS.
In one embodiment, the workflow of the domestic server BIOS firmware backup apparatus:
the CPLD controls the SPI signal switcher to select SPI signals of the CPU to send to the mirror image A of the main BIOS for starting the CPU module, controls the CS signal switcher to acquire CS signals from the SPI signals of the CPU, and sends the CS signals to the mirror image A of the main BIOS. After the power-on, the CPU performs operations such as initialization and the like, and sends the postcode information to the BMC through the first LPC interface and the CPLD, or the BMC actively inquires the postcode information by reading the first LPC interface, and then the BMC judges whether the mirror image needs to be switched according to the postcode information. When detecting the failure of the mirror image A of the main BIOS, the BMC sends a message to the CPLD, informs the CPLD to set the level state of the SCP_RECOVERY interface, and electrifies and de-electrifies the CPU again, and restarts the CPU by using the mirror image B of the main BIOS. Thereby enabling the switching of mirror a and mirror B of the main BIOS.
After the CPU is initialized, in the process of reading the contents of each BIOS, each BIOS runs to one node, and sends out a corresponding code to the CPLD through a first I2C interface of the CPU, and the CPLD sets a corresponding register marking bit. The BMC reads the register of the CPLD, judges whether the current BIOS is the main BIOS or the standby BIOS, and analyzes the starting condition of the CPU module according to the state of the current main BIOS or the standby BIOS. If the main BIOS is abnormal, an abnormal message is recorded, information is sent to the CPLD, the CPLD resets the server after a period of time, the CS signal switcher is controlled to select the standby BIOS, and the CPU is started from the standby BIOS after being electrified. Thereby enabling a switch between the main BIOS and the standby BIOS.
And after the CPU is successfully started by the standby BIOS, a message is sent to the CPLD, and the CPLD controls the SPI signal switcher input end to be connected to the CPLD and is connected to the SPI signal of the BMC by the CPLD through an internal program. Thus, the BMC can remotely update the main BIOS or the standby BIOS with faults, and the faults are eliminated. Meanwhile, the CPLD is connected to the BMC through the GPIO interface, monitors the working condition of the BMC in real time through the watchdog timer, and disregards commands sent by the BMC when detecting abnormal work of the BMC.
The domestic server BIOS firmware backup device realizes the switching process of the main BIOS and the standby BIOS without manual intervention through the cooperation among the CPU, the CPLD and the BMC, automatically switches, sets the mirror image A and the mirror image B in each BIOS, reduces the possibility of BIOS damage through realizing the switching between the mirror image A and the mirror image B, and further ensures the normal operation of the whole system; the domestic server BIOS firmware backup device realizes the remote updating of the main BIOS or the standby BIOS with faults by sending SPI signals of the BIOS to the main BIOS or the standby BIOS, and realizes the elimination of the faults.
The technical features of the above-described embodiments may be arbitrarily combined, and all possible combinations of the technical features in the above-described embodiments are not described for brevity of description, however, as long as there is no contradiction between the combinations of the technical features, they should be considered as the scope of the description.
The above-described embodiments are merely representative of the more specific and detailed embodiments described herein and are not to be construed as limiting the claims. It should be noted that it would be apparent to those skilled in the art that various modifications and improvements could be made without departing from the spirit of the present application, which would be within the scope of the present application. Accordingly, the scope of protection of the present application is to be determined by the claims appended hereto.

Claims (7)

1. A domestic server BIOS firmware backup device is characterized in that: the domestic server BIOS firmware backup device comprises a central processing module CPU, a baseboard management controller BMC, a complex editable logic module CPLD and a switching control module, wherein:
the CRU_I2C interface of the CPU is connected with a BMC, the BMC is configured as a master device, and the CPU is configured as a slave device;
the switching control module comprises an SPI signal switcher, a CS signal switcher, a main BIOS and a standby BIOS; the input end of the SPI signal switcher is respectively connected with SPI signals of the CPU and the BMC, and the output end of the SPI signal switcher is respectively connected with the input ends of the main BIOS, the standby BIOS and the CS signal switcher; the output end of the CS signal switcher is respectively connected with the main BIOS and the standby BIOS; the control ends of the SPI signal switcher and the CS signal switcher are respectively connected with the CPLD;
the SPI interface of the BMC is connected to the CPLD and is connected to the input end of the SPI signal switcher through the CPLD;
the GPIO pins of the CPLD are respectively connected to the control ends of the SPI signal switcher and the CS signal switcher and respectively control the switching of the SPI signal switcher and the CS signal switcher;
and a first I2C interface of the CPU is connected with the CPLD.
2. The home server BIOS firmware backup apparatus of claim 1, wherein: the main BIOS and the standby BIOS respectively comprise an image A and an image B which are mutually independent, and each image A and each image B are connected with the output end of the SPI signal switcher and the output end of the CS signal switcher.
3. The home server BIOS firmware backup apparatus of claim 1, wherein: and the CPU is also provided with a first LPC interface, and the first LPC interface is connected with the CPLD.
4. The home server BIOS firmware backup apparatus of claim 1, wherein: the CPU is also provided with an SCP_RECTIVEY interface, and the SCP_RECTIVEY interface is connected with the CPLD.
5. The home server BIOS firmware backup apparatus of claim 1, wherein: and a second LPC interface is further arranged on the BMC and is connected with the CPLD.
6. The home server BIOS firmware backup apparatus of claim 1, wherein: and the BMC and the CPLD are both provided with second I2C interfaces, and the two second I2C interfaces are mutually connected.
7. The home server BIOS firmware backup apparatus of claim 1, wherein: the GPIO pin of the CPLD is also connected with the BMC.
CN202223055819.7U 2022-11-17 2022-11-17 Domestic server BIOS firmware backup device Active CN218974903U (en)

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Application Number Priority Date Filing Date Title
CN202223055819.7U CN218974903U (en) 2022-11-17 2022-11-17 Domestic server BIOS firmware backup device

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CN218974903U true CN218974903U (en) 2023-05-05

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