CN101299200A - Processor system, equipment and fault handling method - Google Patents
Processor system, equipment and fault handling method Download PDFInfo
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- CN101299200A CN101299200A CNA2008101146255A CN200810114625A CN101299200A CN 101299200 A CN101299200 A CN 101299200A CN A2008101146255 A CNA2008101146255 A CN A2008101146255A CN 200810114625 A CN200810114625 A CN 200810114625A CN 101299200 A CN101299200 A CN 101299200A
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Abstract
The present invention discloses a processor system, equipment and fault handling method, including: a first address signal pin, a second address signal pin, and a controller, wherein the first address signal pin and the second address signal pin are respectively used to connect with the CPU management system and the FLASH through address signal wires; the controller is respectively connected with the first address signal pin and the second address signal pin; the controller is used to send out a reset pulse to the CPU management system, when the controller has not received a normal work indicating information in a setting time or receives a restart command. The application of the invention can completely avoid the problem that the old design cannot normally start when the startup code is damaged.
Description
Technical field
The present invention relates to data processing equipment, particularly a kind of processor system, CPU management system, fault treating apparatus and fault handling method.
Background technology
Following elder generation describes the key concept that relates to.
The FLASH storer claims flash memory again, is a kind of nonvolatile memory that can onlinely repeatedly wipe, and promptly data can not lost and are typical memory device in the embedded system after the power down.The start-up code and the data that generally are used for storage system work in the embedded system.
A kind of NOR FLASH that is called again of parallel FLASH:FLASH storer, owing to carry out on the parallel FLASH support code sheet, application program and start-up code can directly be moved on FLASH, so generally are used for the start-up code of storage system in the embedded system.
Fig. 1 is the mount structure synoptic diagram of parallel FLASH (NOR FLASH), as shown in the figure, and wherein:
RESET is the reseting pin of chip;
CE is the chip selection signal pin of chip;
WE is the write signal pin of chip;
OE is the read signal pin of chip;
VCC is the power supply input pin of chip;
VSS is the ground pin of chip;
BYTE is the working mode selection pin of chip, and BYTE connects high chip operation 16 mode of operations, and chip operation is 8 mode of operations during BYTE ground connection;
WP/ACC is the write-protect pin of chip, and WP connects low level, and chip does not allow to be modified (write-protect of a look-alike disk is arranged);
DQ0 to DQ7 is the data-signal pin of chip operation under 8 bit patterns;
DQ8 to DQ15 is the data-signal pin of chip operation under 16 bit patterns;
A0A1A2 to A20 is operated in 16 mode of operation address wire pins for parallel FLASH;
A-1A0A1 to A20 is operated in 8 address wire pins under the mode of operation for parallel FLASH.
Parallel FLASH device generally comprises the address signal pin, data-signal pin and read-write control signal pin, and CPU (processor) reads or writes the FLASH content by above three kinds of signal wires.
Address signal line: be used for the signal wire of transport addresses information, concrete, link to each other address wire difference, the content difference that reads with pins such as A0A1 among Fig. 1;
Data signal line: data signal line is to be used for the signal wire of transmitting data information, links to each other with pins such as DQ0-DQ7 among Fig. 1;
Read-write control signal line: be used for the signal wire of control information transmission, such as information such as read-write selections.
Power on some input pins of configuration: CPU are by making CPU be operated in different mode of operations in the different level signal combination of these pins inputs.
The start-up course of CPU: general general processor all is to begin run time version after particular address from the parallel FLASH that is connected to specific signal line reads start-up code when powering on, and can be the chip selection signal line such as this specific signal line;
Fig. 2 is a NOR FLASH syndeton synoptic diagram in the processor system, as shown in the figure, comprise: management system 201, parallel FLASH202, CPLD (Complex Programmable Logic Device, CPLD) 203, serial ports 204, wherein:
CPLD representative be a kind of programmable logic device (PLD), it can be after manufacturing is finished defines its logic function by the user according to oneself needs, generally is used to realize some simple user customized logics in electronic system.
RST: the input pin that resets of management system, if RST has the pulse of low level signal, then management system resets, total system is restarted work.
Start-up code: in the electronic system, the code that CPU is performed the earliest is the most basic code of electronic system energy operate as normal.
Management system 201: finish the control of total system, comprise the read-write operation of initiation to FLASH202.
CPLD203: by the input that resets of pin control management system 201, if the various situations of the operate as normal by bus and management system 201 interactive systems are system's malfunction then initiate reset operation to whole management system 201.
Management system resets and imports RST: if the reseting pin of management system receives reset pulse from high to low, then management system just begins to restart, and reaffirms the pattern of working on power, and initiates the read-write to parallel FLASH202 again.
The CPLD Global reset: if the reseting pin of CPLD203 receives reset pulse from high to low, then CPLD just begins to restart, and all states of the inside of CPLD all return to initial state, and the state machine of CPLD inside just restarts running.
Parallel FLASH202: start-up code that storage system is working properly and data, the read write command that the receiving management system sends.Fig. 3 is a FLASH deposit data form synoptic diagram, as shown in the figure, has stored guidance code on the address 301 of FLASH, and 302 have stored application program in the address, 303 other data of storage in the address.
The write signal line: when management system will be carried out write operation to FLASH, this signal wire was a low level.
When the write-protect pin is directly connected to high level, allow the write operation behavior of management system, high level generally is meant the voltage of 3.3V.
Serial ports 204: management system 201 is by the duty of serial ports 204 output systems.
But legacy system has the following disadvantages:
1, when having the behavior of wrong operation start code, the start-up code that may destroy system causes system to start;
2, some unartificial faults can cause the destroyed system that causes of start-up code of system to start, and may cause loss of data because of quality problem such as the FLASH that stores start-up code.
3, because system does not have redundant start-up code design, in case unique start-up code is destroyed, system just can't operate as normal.
Summary of the invention
The invention provides a kind of processor system, CPU management system, fault treating apparatus and fault handling method, in order to solve when mistake appears in start-up code, can identify mistake, further, solve the problem that processor system can not normally restart when breaking down.
The invention provides a kind of fault treating apparatus of processor system, comprising: the first address signal pin, the second address signal pin, also comprise controller, wherein:
The first address signal pin, the second address signal pin are respectively applied for by address signal line and are connected with CPU management system, FLASH;
Controller links to each other with the first address signal pin, the second address signal pin respectively;
Controller, be used in setting-up time, not receiving normal work indicating information or receive restart order after, send reset pulse to the CPU management system.
Preferably, controller comprises:
Timer is used for not receiving normal work indicating information in setting-up time, then triggers the reset pulse transmitter unit;
The reset pulse transmitter unit, be used for be timed device trigger or receive restart order after, send reset pulse to the CPU management system.
Preferably, controller further comprises:
Switch unit is used for when being timed the device triggering, will switch to the second memory address signal by the first memory address signal that the second address signal pin sends;
Described timer is further used for not receiving normal work indicating information in setting-up time, then triggers switch unit.
Preferably, controller further comprises:
The failure identification unit is used for after being timed the device triggering, and there is fault in the start-up code that sign FLASH stores on current first memory address that reads;
Timer is further used for not receiving normal work indicating information in setting-up time, then triggers the failure identification unit.
Preferably, controller further comprises:
Number of starts statistic unit is used for when starting, and the number of times that current second memory address that reads is started adds one.
Preferably, controller further comprises:
Whether the upgrading identify unit is used to identify the CPU management system and start-up code is upgraded.
Described switch unit is further used for will switching to the second memory address signal by the first memory address signal that the second address signal pin sends being timed that device triggers and upgrading when identifying not set;
Described failure identification unit is further used for being timed that device triggers and upgrading when identifying not set, and there is fault in the start-up code that sign FLASH stores on current first memory address that reads;
Described number of starts statistic unit is further used for starting and upgrades when identifying not set, and the number of times that current second memory address that reads is started adds one.
The present invention also provides a kind of processor system, comprising:
FLASH links to each other with controller by address signal line, storage start-up code data file on first memory address, backup start-up code data file on second memory address;
The CPU management system, link to each other with controller by address signal line, start according to the start-up code data file that reads from FLASH, send normal work indicating information in the normal back that starts to controller, and behind the reset pulse that receives the controller transmission, restart;
Controller connects the address signal line of CPU management system and the address signal line of FLASH, be used in setting-up time, not receiving normal work indicating information or receive restart order after, send reset pulse to the CPU management system.
Preferably, controller further comprises:
The failure identification unit is used for after being timed the device triggering, and there is fault in the start-up code that sign FLASH stores on current first memory address that reads;
Timer is further used for not receiving normal work indicating information in setting-up time, then triggers the failure identification unit;
The CPU management system further comprises:
First recovery unit, be used for after the CPU management system starts, after determining that there is fault in the start-up code of storing on first or second memory address, there is the memory address of fault in the start-up code that the start-up code data file on another memory address is returned to storage.
Preferably, controller further comprises:
Number of starts statistic unit, when being used to start, the number of times that current second memory address that reads is started adds one;
The CPU management system further comprises:
Second recovery unit is used for after the CPU management system starts, and when definite number of times that starts from first or second memory address surpasses threshold value, the start-up code data file on another memory address is returned to the memory address that the number of starts surpasses threshold value.
Preferably, controller further comprises:
Whether the upgrading identify unit is used to identify the CPU management system and start-up code is upgraded;
The sign set that is further used for to upgrade before the starting and upgrading code of CPU management system.
The invention provides a kind of fault handling method of processor system, comprise the steps:
Controller does not receive normal work indicating information or receives and restarts order in setting-up time, send reset pulse to the CPU management system.
To switch to the second memory address signal by the first memory address signal that the second address signal pin sends, and there is fault in the start-up code that sign FLASH stores on current first memory address that reads.
Preferably, also comprise:
After the CPU management system starts, the start-up code on another memory address is returned to the memory address of fault.
Preferably, further comprise:
When starting, the number of times that will start from second memory address that current FLASH reads adds one;
After the CPU management system starts, the start-up code on the normal memory address of the number of starts is returned to the number of starts surpass on the memory address of threshold value.
Beneficial effect of the present invention is as follows:
Whether the present invention can detection system normally start, thereby has avoided old design fully under the ruined situation of start-up code, can not discern wrong problem to occur, further can also separate the problem that must not normally restart.
Description of drawings
Fig. 1 is the mount structure synoptic diagram of parallel FLASH described in the background technology;
Fig. 2 is a NOR FLASH syndeton synoptic diagram in the processor system described in the background technology;
Fig. 3 is the form of FLASH deposit data described in a background technology synoptic diagram;
Fig. 4 is a processor system structural representation described in the embodiment of the invention;
Fig. 5 is the deposit data form synoptic diagram of FLASH described in the embodiment of the invention on memory address;
Fig. 6 is that address logic described in the embodiment of the invention switches synoptic diagram;
Fig. 7 is the CPU management system structural representation of processor system described in the embodiment of the invention;
Fig. 8 is the fault treating apparatus structural representation of processor system described in the embodiment of the invention;
Fig. 9 is the synoptic diagram of processor system implementing procedure described in the embodiment of the invention;
Figure 10 is the fault handling method implementing procedure synoptic diagram of processor system described in the embodiment of the invention;
Figure 11 causes starting the solution implementing procedure synoptic diagram of failure for upgrading described in the embodiment of the invention.
Embodiment
Below in conjunction with accompanying drawing the specific embodiment of the present invention is described.
The inventor notices in the invention process:
The operation that parallel FLASH writes in the conditional electronic system generally exists in following several situations:
1, starting and upgrading code is equivalent to the BIOS (Basic Input/Output System, Basic Input or Output System (BIOS)) of PC;
2, upgrading master routine, WINDOWS operating system is equivalent to upgrade;
3, record trouble information, PC misregistration diary when being equivalent in using the PC process, make mistakes at ordinary times;
4, information-setting by user, the parameter of similar modification BIOS.
More than four kinds operation is general only is used in certain condition, when calling on these theory of operation is known determining, still because artificial or some other unforeseen odjective cause also can cause these operations by wrong calling.Such as:
Because system designer's carelessness, when some should not write FLASH, call and write the FLASH operation, that is to say that write operation calls should not be invoked the time;
System is by the following electricity of mistake in upgrading or when revising code, similarly cuts off the power supply in half process of WIDOWS operating system is installed;
The system start-up code and the master routine that below either way might cause are destroyed, cause the system can't operate as normal.
It will cause following situation:
Legacy system normal boot-strap operating process is as follows:
1, system powers on;
2, CPLD receives the Global reset pulse signal, and the CPLD internal logic returns to original state;
3, CPLD sends reset pulse to the CPU management system by pin, and starts the detection to CPU management system working condition;
4, the CPU management system starts from parallel FLASH; The CPU management system reads parallel FLASH content, and system begins to start.System's operate as normal, management system sends operate as normal information to CPLD by bus.
But, when the start-up code on occurring in FLASH is destroyed, then can occur:
5, because the FLASH start-up code goes wrong, and the CPU management system can't normally start, the CPU management system can't normal timing be sent the system works normal information;
6, CPLD does not receive the sign of the operate as normal of management system in certain time interval, just often the 3rd step work above CPLD repeats, promptly, CPLD sends reset pulse to the CPU management system by pin, and starts the detection to CPU management system working condition;
Then, just constantly repeat top normal the 3rd, 4,5,6 job step, system can't operate as normal.
This shows because traditional parallel FLASH storage system is not owing to there is redundant start-up code, so in case the destroyed processor system that just causes of the start-up code of FLASH can't normally start.Given this, mainly avoid processor system problems in the prior art in the invention process, the problem includes: above problem by the following aspects, thus the reliability of raising processor system.
One, by the two parts of start-up code of different two addresses storages in the FLASH of prior art storage system, when avoiding the main start-up code of processor system destroyed, system does not have operable start-up code;
Two, by in circuit, adding start-up code address switchover unit, when system can't normally start, switch to the address space of backup FLASH, system is started from the address space of the FLASH of redundancy;
Three, also further adopted the scheme of recovering startup,, after starting, after startup is finished, recovered ruined FLASH by processor system by normal FLASH by when processor system can't normally start.
According to above-mentioned thinking, to how specifically to implement describe below.
Fig. 4 is the processor system structural representation, as shown in the figure, can comprise in processor system: FLASH401, CPU management system 402, controller 403, wherein:
FLASH401 links to each other with controller 403 by address signal line, is used to store the start-up code data file; Stored normal start-up code of system works and data on the FLASH, the read write command that the receiving management system sends, concrete, can on first memory address, store the start-up code data file, backup start-up code data file on second memory address.
In the enforcement, with two memory addresss of having stored the start-up code data file is that example describes, wherein, name by boot sequence, claim that then the preferential memory address that starts is first memory address, standby memory address is second memory address, know easily, relation between the two is mutually redundant relation, such as: when second memory address from present name started, then first memory address had then become the slack storage address of second memory address.Simultaneously, in order to be convenient to statement in force, at first reading startup data file from first memory address when starting among the embodiment starts, therefore on second memory address, back up the start-up code data file, in concrete the enforcement, the address signal line of controller links to each other with address signal line pin on the FLASH, but but can be implemented on the same address signal line from same address signal line pin control CPU management system reading of data on different memory addresss by some technological means.Such as: because a plurality of memory addresss are arranged on FLASH, it is to decide according to the level signal of carrying from address signal line to read memory address, therefore also can be controlled at different memory addresss and read start-up code, equally also can back up the start-up code data file in different memory addresss by the level signal that control is carried from address signal line; It should be noted that, utilize level signal to be controlled at that reading of data is a kind of means commonly used on the different memory addresss, what emphasize in the invention process is switching controls to memory address, if being arranged, other can control the means that the data on the different memory addresss are read, so by realizing that on controller these function means then also can reach the purpose of level signal control, obtain the same technique effect.Fig. 5 is the deposit data form synoptic diagram of FLASH on memory address, as shown in the figure, stored the start-up code data file in first memory address, on second memory address, stored backup start-up code data file, stored other data in the 3rd memory address, stored application program in the 4th memory address.This figure only is used for example, and those skilled in the art know easily concrete which kind of data of storage can come to determine as required on each memory address of FLASH.
CPU management system 402 links to each other with controller 403 by address signal line, start according to the start-up code data file that reads from memory address by the address signal line traffic control, sending normal work indicating information in the normal back that starts to controller 403, and restarting receiving behind the reset pulse that controller 403 sends; As shown in Figure 4, when the CPU management system when the memory address that reads by the address signal line traffic control reads start-up code, this address signal line has comprised the address signal line of 403 of CPU management system 402 and controllers and the address signal line between controller 403 and the FLASH401 in force, for the CPU management system, it is transparent reading start-up code, just can control the CPU management system by controller to the switching of memory address in the enforcement and data be read on different memory addresss by same data signal line.
Concrete, can comprise in the controller:
Timer is used for not receiving normal work indicating information in setting-up time, then triggers the reset pulse transmitter unit;
The reset pulse transmitter unit, be used for be timed device trigger or receive restart order after, send reset pulse to the CPU management system.
Further, timer can also be further used for not receiving normal work indicating information in setting-up time, then triggers switch unit; Under this scheme, can also comprise switch unit in the controller, be used for when being timed the device triggering, to switch to the second memory address signal by the first memory address signal that the second address signal pin sends, the second memory address level signal is carried in the concrete first memory address level signal of carrying to the second address signal pin can being switched to; Like this, controller just can switch to the required memory address that reads start-up code data file place as required by the level signal of carrying is controlled on address wire.
In the enforcement, controller can adopt CPLD to realize, adopt this kind programmable logic device (PLD) to realize, just can be after its manufacturing is finished define its logic function according to oneself needs, in electronic system, be used to realize some simple user customized logics by the user.
By above-mentioned enforcement as can be seen the connection of system improve and to be:
In the old processor system design: the address signal of parallel FLASH is directly supplied with by the CPU management system;
In the new processor system of embodiment: the address signal of parallel FALSH is supplied with by controller, and the address signal line of FLASH directly is not connected with the CPU management system in the new system.Because controller can switch the memory address that reads the start-up code data file by the change of the level signal of carrying from address signal line, therefore just can control the CPU management system to FLASH the reading of right startup data file on different memory addresss by the selection of control level signal.
In concrete the enforcement, timer can be used for not receiving normal work indicating information in setting-up time, then triggers the reset pulse transmitter unit; Timer can adopt the operate as normal register in implementing, and is used to write down the time interval of twice management system notification controller system operate as normal, if timer overflows, the logic of notification controller begins to restart.Further, can also be provided with: if in the specific time, receive the operate as normal sign that the CPU management system is sent, this timer automatic clear 0.
The reset pulse transmitter unit, be used for be timed device trigger or receive restart order after, send reset pulse to the CPU management system; It can adopt a reseting logic to realize, its CPU management system that is used to reset.
The switch unit that further comprises is used for after being timed the device triggering, will switch to the first memory address level signal that the second address signal pin is carried and carry the second memory address level signal.Can adopt an address switchover logic to realize, be used to select to start or start from second memory address from first memory address of parallel FLASH.Fig. 6 switches synoptic diagram for address logic, as shown in the figure, can adopt one of following two kinds of combinations:
The unification of logic switch groups:
The controller address line sends the first memory address level signal;
Then the CPU management system starts from first memory address of parallel FLASH.
Logic suits combination two:
The controller address line sends the second memory address level signal;
Then the CPU management system starts from second memory address of parallel FLASH.
In the enforcement, the address signal line of CPU management system is connected to controller, by controller the connection of memory address is switched, and just can actually reach control CPU management system and read start-up code from different memory addresss and start.
Further, in controller 403, can also comprise:
The failure identification unit is used for after being timed the device triggering, and the start-up code that sign FLASH stores on first memory address of the first memory address level signal correspondence of carrying when the forward direction second address signal pin has fault; Under this scheme, timer can also be further used for not receiving normal work indicating information in setting-up time, then triggers the failure identification unit.
The failure identification unit can write down the failure identification of second memory address, in the process of system start-up, if system can't start from the memory address that current level signal is selected, then controller is at state of internal record, identify the start-up code of storing on this memory address and have fault, use for follow-up system and controller internal logic and judge.
In like manner, the failure identification unit further writes down the failure identification of first memory address, in the start-up course of system, if system can't start from parallel FLASH first memory address, then controller is at state of internal record, the start-up code of storing on parallel FLASH first memory address of sign has fault, judges for follow-up system and controller internal logic.
In the enforcement, exist CPU management system or other devices to send to controller and restart order, controller does not think in this case that to the situation of CPU management system transmission reset pulse start-up code breaks down, promptly do not switch, decline failure identification, only send reset pulse.
In this embodiment, the CPU management system may further include:
First recovery unit is used for after the CPU management system starts, and after there is fault in the start-up code of determining the storage of the FLASH last first or second memory address, the start-up code data file on another memory address is returned to the memory address of fault.
After breaking down, there is the memory address of fault in the start-up code that first recovery unit just can identify storage by top failure identification, recovers thereby can carry out corresponding file.In the enforcement, can be after recovery with failure identification zero setting, so that reuse when breaking down later on.
Further, can also comprise in the controller:
Number of starts statistic unit, when being used to start, the number of times that current second memory address that reads is started adds one;
In this embodiment, the CPU management system further comprises:
Second recovery unit is used for after the CPU management system starts, and when definite number of times from FLASH first or the startup of second memory address surpasses threshold value, the start-up code data file on another memory address is returned to the memory address that the number of starts surpasses threshold value.
After the CPU management system reads the start-up code data file and starts,, therefore when receive normal work indicating information, just can determine system's normally startup if working properlyly then can send normal work indicating information.
Controller can further include: whether the upgrading identify unit is used to identify the CPU management system and start-up code is upgraded; Then, the CPU management system sign set that can be further used for to upgrade before the starting and upgrading code.
The effect of upgrading sign is: put when the upgrading sign under 0 the situation, if timer overflows, send out reset pulse, the sign of switching, place obstacles, then with memory address number of times+1 of startup;
Upgrading sign is put under 1 the situation, if timer overflows or receives reset command, then only sends out reset pulse, will upgrade to identify and put back 0;
In the concrete enforcement for upgrading identify unit, number of starts statistic unit, can be as follows:
Number of starts statistic unit can write down the number of starts as second memory address of backup, when starting once, add one in this numeral, for avoiding occurring error logging from second memory address, in the time of can being arranged on controller and receiving the Global reset pulse, should be worth zero setting.This number of times is to be used for judging at subsequent process whether system normally starts use.
In like manner, number of starts statistic unit can also write down the number of starts as first memory address of backup, starts once from first memory address, add one in this numeral, for avoiding occurring error logging, in the time of can being arranged on controller and receiving the Global reset pulse, should be worth zero setting.This number of times is to be used for judging at subsequent process whether system normally starts use.
When carrying out the start-up code upgrading, system will upgrade and identify set (as being changed to 1), if upgrade successfully, the CPU management system will be upgraded to identify and be reset to 0.In concrete the enforcement, when receiving the restarting order or timer and be triggered of CPU, put 1, then only need be sent reset pulse, added one or failure identification is set and need not to switch memory address, the number of starts if determine the upgrading sign.After sending reset pulse, the sign of will upgrading is reset to 0.By upgrading sign is set, what make that upgrading causes can't send normal work indicating information and can not be mistaken as fault and switch, thereby causes finishing restarting after the upgrading.
In addition, also exist in the enforcement from certain memory address startup situation repeatedly, at this kind situation, second recovery unit determines that the purpose whether number of starts surpasses threshold value is, if it is unusual that system's appearance, thinks then that start-up code occurs from the situation that this memory address repeatedly starts, therefore, when the number of starts of statistics exceeds preset threshold, also need carry out the recovery of startup file.
The present invention also provides a kind of CPU management system of processor system and a kind of fault treating apparatus of processor system, below its embodiment is described.
Fig. 7 is the CPU management system structural representation of processor system, as shown in the figure, can comprise in the CPU management system: first recovery unit 701 and/or second recovery unit 702, wherein:
Fig. 8 is the fault treating apparatus structural representation of processor system, as shown in the figure, can comprise in the fault treating apparatus: the first address signal pin 801, the second address signal pin 802, controller 403, wherein:
The first address signal pin 801, the second address signal pin 802 are respectively applied for by address signal line and are connected with CPU management system, FLASH;
Can comprise in the controller:
Reset pulse transmitter unit 4033, be used for be timed device trigger or receive restart order after, send reset pulse to the CPU management system.
Further, timer can also be further used for not receiving normal work indicating information in setting-up time, then triggers switch unit; Then, controller further can also comprise: switch unit 4032 is used for when being timed the device triggering, will switch to the second memory address signal by the first memory address signal that the second address signal pin sends;
This is implemented down, and the level signal that controller can utilize change to carry by address wire realizes the switching to the memory address that is read.
When being connected with external unit, concrete enforcement can for: can connect the CPU management system by address signal line with the first address signal pin 801, the second address signal pin 802 connects the FLASH that stores the start-up code data file by address signal line.
Then, after controller is receiving the Global reset pulse, when in setting-up time, not receiving normal work indicating information, after sending reset pulse, just can be by controlling level signal control CPU management system the reading of exporting on the address signal line that connects with FLASH to the start-up code data file on the different memory addresss.
In concrete the enforcement, controller 403 can comprise: timer 4031, reset pulse transmitter unit 4033, can also comprise switch unit 4032, wherein:
Reset pulse transmitter unit 4033, be used for be timed device 4031 trigger or receive restart order after after, send reset pulse;
In fault treating apparatus, can further include: failure identification unit 804, after being used to be timed device and triggering, there is fault in the start-up code that sign FLASH stores on current first memory address that reads.In this embodiment, timer also is further used for not receiving normal work indicating information in setting-up time, then triggers the failure identification unit.
Can further include in the fault treating apparatus:
Number of starts statistic unit 806 is used for when starting, and the number of times that current second memory address that reads is started adds one.
Can further include in the controller: whether upgrading identify unit 805 is used to identify the CPU management system and start-up code is upgraded.
In the enforcement, switch unit will switch to the signal of second memory address by first memory address that the second address signal pin sends being timed that device triggers and upgrading when identifying not set, and first memory address that is about to reading of data switches to second memory address; The failure identification unit then is being timed that device triggers and upgrading when identifying not set, and there is fault in the start-up code that sign FLASH stores on current first memory address that reads; Number of starts statistic unit is starting and upgrading when identifying not set, and the number of times that current second memory address that reads is started adds one.
Below in the enforcement of an embodiment in order to explanation said system and device, Fig. 9 is a processor system implementing procedure synoptic diagram, as shown in the figure, can see how technical solution problem of this implementing procedure thing, this embodiment middle controller adopts CPLD to implement.
Step 901, system power on;
Step 902, CPLD receive the Global reset pulse signal, and the CPLD internal logic returns to original state;
Step 903, address switchover logic switch to from parallel FLASH first memory address and start, and parallel FLASH reading times adds one;
When system normally started, flow process was: CPLD sends reset pulse to management system by pin, and the operate as normal timer begins counting; Management system starts from parallel FLASH first memory address; Management system reads the content on parallel FLASH first memory address, and system begins to start, and management system is sent system's operate as normal sign by bus timing.
Below be the implementing procedure of system can't normally start the time, promptly, because the start-up code data file of storing on parallel FLASH first memory address is destroyed, management system can't read normal code, and management system can't regularly be sent normal work indicating information; Then following steps are:
Step 904, CPLD do not receive normal work indicating information in setting-up time;
Step 905, CPLD switch logic handover management system start from FLASH second memory address; The CPLD set FLASH first memory address failure identification position that walks abreast;
Step 906, the CPLD management system that resets again;
Step 907, management system start from FLASH second memory address, read code;
Step 908, management system read the parallel FLASH first memory address fault by bus at CPLD and indicate position and second memory address fault sign position, confirm that parallel FLASH first memory address breaks down;
Step 909, management system initiate to recover the code of the startup on parallel FLASH first memory address.
By above-mentioned enforcement as seen, in the enforcement by on original circuit, having done slight change, or on original software action, done slight change, can not only detection system whether normally start, can also switch to normal FLASH when system goes wrong starts, further, recover the content of ruined FLASH in the time of can also be in system normal, thus the problem of having avoided old design under the ruined situation of start-up code, can't normally start fully.As seen embodiment of the present invention change in design little, but effect is obvious.
The present invention also provides a kind of fault handling method of processor system, and the concrete enforcement to this method describes below.
Figure 10 is the fault handling method implementing procedure synoptic diagram of processor system, as shown in the figure, can comprise the steps: when implementing fault handling method
There is fault in the start-up code of storing on step 1006, controller identifier first memory address, and at this moment, the CPU management system is from the first memory address reading of data when carrying the first memory address level signal;
In concrete the enforcement, controller is also added up the number of times that starts from the current memory address that reads of CPU management system after sending reset pulse, as adding one from the number of times that current memory address starts;
Under this embodiment, the CPU management system is after startup in the step 1009, when definite number of times that starts from first or second memory address surpasses threshold value, the start-up code data file that backs up on another memory address is returned to the memory address that the number of starts surpasses threshold value.
A lot of reasons is to occur in starting and upgrading code and upgrading during master routine because system breaks down, so solve the embodiment that causes starting because of upgrading so that the specific embodiment of the present invention is further described for one.
Figure 11 causes starting the solution implementing procedure synoptic diagram of failure for upgrading, for concrete solution is failed because of the startup that upgrading brings, can increase the upgrading sign in the enforcement, be used for the behavior that tag system upgrading once took place and revises FLASH, this sign can be recorded when any software modification FLASH is arranged, further, when can setting controller receiving the Global reset pulse, should be worth zero setting; This embodiment middle controller adopts CPLD to implement, and then as shown in the figure, can comprise the steps: in the enforcement
In the enforcement, management system may cannot initiatively be sent out after upgrading and restart order, does not still trigger timer by receiving the operate as normal flag in the setting-up time in the step 1104 in this case, sends out reset pulse;
Step 1108, because the operate as normal timer receives operate as normal sign, CPLD judgement system goes wrong;
Step 1111, management system start from second memory address of FLASH;
Step 1113, management system initiate to recover the code of the startup on FLASH first memory address.
By above-mentioned enforcement as can be seen, can not only detection system whether normally start in the invention process, can also when system goes wrong, switch on the normal memory address of FLASH and start, further, recover the content on the ruined memory address on the FLASH in the time of can also be in system normal, thus the problem of having avoided old design under the ruined situation of start-up code, can't normally start fully.
Obviously, those skilled in the art can carry out various changes and modification to the present invention and not break away from the spirit and scope of the present invention.Like this, if of the present invention these are revised and modification belongs within the scope of claim of the present invention and equivalent technologies thereof, then the present invention also is intended to comprise these changes and modification interior.
Claims (13)
1, a kind of fault treating apparatus of processor system comprises: the first address signal pin, the second address signal pin, it is characterized in that, and also comprise controller, wherein:
The first address signal pin, the second address signal pin are respectively applied for by address signal line and are connected with CPU management system, FLASH;
Controller links to each other with the first address signal pin, the second address signal pin respectively;
Controller, be used in setting-up time, not receiving normal work indicating information or receive restart order after, send reset pulse to the CPU management system.
2, fault treating apparatus as claimed in claim 1 is characterized in that, controller comprises:
Timer is used for not receiving normal work indicating information in setting-up time, then triggers the reset pulse transmitter unit;
The reset pulse transmitter unit, be used for be timed device trigger or receive restart order after, send reset pulse to the CPU management system.
3, fault treating apparatus as claimed in claim 2 is characterized in that, controller further comprises:
Switch unit is used for when being timed the device triggering, will switch to the second memory address signal by the first memory address signal that the second address signal pin sends;
Described timer is further used for not receiving normal work indicating information in setting-up time, then triggers switch unit.
4, fault treating apparatus as claimed in claim 3 is characterized in that, controller further comprises:
The failure identification unit is used for after being timed the device triggering, and there is fault in the start-up code that sign FLASH stores on current first memory address that reads;
Timer is further used for not receiving normal work indicating information in setting-up time, then triggers the failure identification unit.
5, fault treating apparatus as claimed in claim 3 is characterized in that, controller further comprises:
Number of starts statistic unit is used for when starting, and the number of times that current second memory address that reads is started adds one.
6, as the arbitrary described fault treating apparatus of claim 3 to 5, it is characterized in that controller further comprises: whether the upgrading identify unit is used to identify the CPU management system and start-up code is upgraded;
Described switch unit is further used for will switching to the second memory address signal by the first memory address signal that the second address signal pin sends being timed that device triggers and upgrading when identifying not set;
Described failure identification unit is further used for being timed that device triggers and upgrading when identifying not set, and there is fault in the start-up code that sign FLASH stores on current first memory address that reads;
Described number of starts statistic unit is further used for starting and upgrades when identifying not set, and the number of times that current second memory address that reads is started adds one.
7, a kind of processor system is characterized in that, comprising:
FLASH links to each other with controller by address signal line, storage start-up code data file on first memory address, backup start-up code data file on second memory address;
The CPU management system, link to each other with controller by address signal line, start according to the start-up code data file that reads from FLASH, send normal work indicating information in the normal back that starts to controller, and behind the reset pulse that receives the controller transmission, restart;
Controller connects the address signal line of CPU management system and the address signal line of FLASH, be used in setting-up time, not receiving normal work indicating information or receive restart order after, send reset pulse to the CPU management system.
8, system as claimed in claim 7 is characterized in that,
Controller further comprises:
The failure identification unit is used for after being timed the device triggering, and there is fault in the start-up code that sign FLASH stores on current first memory address that reads;
Timer is further used for not receiving normal work indicating information in setting-up time, then triggers the failure identification unit;
The CPU management system further comprises:
First recovery unit is used for after the CPU management system starts, and after determining that there is fault in the start-up code of storing on first or second memory address, the start-up code data file on another memory address is returned to the memory address of fault.
9, system as claimed in claim 7 is characterized in that,
Controller further comprises:
Number of starts statistic unit, when being used to start, the number of times that current second memory address that reads is started adds one;
The CPU management system further comprises:
Second recovery unit is used for after the CPU management system starts, and when definite number of times that starts from first or second memory address surpasses threshold value, the start-up code data file on another memory address is returned to the memory address that the number of starts surpasses threshold value.
10, as the arbitrary described system of claim 7 to 9, it is characterized in that controller further comprises:
Whether the upgrading identify unit is used to identify the CPU management system and start-up code is upgraded;
The sign set that is further used for to upgrade before the starting and upgrading code of CPU management system.
11, a kind of fault handling method of processor system is characterized in that, comprises the steps:
Controller does not receive normal work indicating information or receives and restarts order in setting-up time, send reset pulse to the CPU management system;
To switch to the second memory address signal by the first memory address signal that the second address signal pin sends, and there is fault in the start-up code that sign FLASH stores on current first memory address that reads.
12, method as claimed in claim 11 is characterized in that, also comprises:
After the CPU management system starts, the start-up code on another memory address is returned to the memory address of fault.
13, method as claimed in claim 11 is characterized in that, further comprises:
When starting, the number of times that will start from second memory address that current FLASH reads adds one;
After the CPU management system starts, the start-up code on the normal memory address of the number of starts is returned to the number of starts surpass on the memory address of threshold value.
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| CNA2008101146255A CN101299200A (en) | 2008-06-11 | 2008-06-11 | Processor system, equipment and fault handling method |
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| CNA2008101146255A CN101299200A (en) | 2008-06-11 | 2008-06-11 | Processor system, equipment and fault handling method |
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Cited By (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN101620885B (en) * | 2009-08-07 | 2012-01-25 | 福建星网锐捷网络有限公司 | Operational method and apparatus for guiding systems on FLASH |
| CN104820624A (en) * | 2015-05-21 | 2015-08-05 | 南车株洲电力机车研究所有限公司 | NOR Flash protection circuit |
| CN106227620A (en) * | 2016-07-20 | 2016-12-14 | 中国航空工业集团公司航空动力控制系统研究所 | Recoverable Flash data storage method |
| CN107908490A (en) * | 2017-11-09 | 2018-04-13 | 郑州云海信息技术有限公司 | GPU registers reliability verification method and system in a kind of server DC tests |
| CN109522241A (en) * | 2018-11-15 | 2019-03-26 | 锐捷网络股份有限公司 | A kind of Write-protection method based on Flash, device and circuit |
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2008
- 2008-06-11 CN CNA2008101146255A patent/CN101299200A/en active Pending
Cited By (8)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN101620885B (en) * | 2009-08-07 | 2012-01-25 | 福建星网锐捷网络有限公司 | Operational method and apparatus for guiding systems on FLASH |
| CN104820624A (en) * | 2015-05-21 | 2015-08-05 | 南车株洲电力机车研究所有限公司 | NOR Flash protection circuit |
| CN104820624B (en) * | 2015-05-21 | 2018-08-10 | 南车株洲电力机车研究所有限公司 | A kind of NOR Flash protections circuit |
| CN106227620A (en) * | 2016-07-20 | 2016-12-14 | 中国航空工业集团公司航空动力控制系统研究所 | Recoverable Flash data storage method |
| CN106227620B (en) * | 2016-07-20 | 2019-03-29 | 中国航空工业集团公司航空动力控制系统研究所 | Recoverable Flash data storage method |
| CN107908490A (en) * | 2017-11-09 | 2018-04-13 | 郑州云海信息技术有限公司 | GPU registers reliability verification method and system in a kind of server DC tests |
| CN107908490B (en) * | 2017-11-09 | 2021-02-05 | 苏州浪潮智能科技有限公司 | Method and system for verifying reliability of GPU (graphics processing Unit) register in server DC (direct Current) test |
| CN109522241A (en) * | 2018-11-15 | 2019-03-26 | 锐捷网络股份有限公司 | A kind of Write-protection method based on Flash, device and circuit |
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