CN109522241A - A kind of Write-protection method based on Flash, device and circuit - Google Patents
A kind of Write-protection method based on Flash, device and circuit Download PDFInfo
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- CN109522241A CN109522241A CN201811360116.0A CN201811360116A CN109522241A CN 109522241 A CN109522241 A CN 109522241A CN 201811360116 A CN201811360116 A CN 201811360116A CN 109522241 A CN109522241 A CN 109522241A
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F12/00—Accessing, addressing or allocating within memory systems or architectures
- G06F12/02—Addressing or allocation; Relocation
- G06F12/0223—User address space allocation, e.g. contiguous or non contiguous base addressing
- G06F12/023—Free address space management
- G06F12/0238—Memory management in non-volatile memory, e.g. resistive RAM or ferroelectric memory
- G06F12/0246—Memory management in non-volatile memory, e.g. resistive RAM or ferroelectric memory in block erasable memory, e.g. flash memory
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F12/00—Accessing, addressing or allocating within memory systems or architectures
- G06F12/14—Protection against unauthorised use of memory or access to memory
- G06F12/1416—Protection against unauthorised use of memory or access to memory by checking the object accessibility, e.g. type of access defined by the memory independently of subject rights
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Abstract
The invention discloses a kind of Write-protection method based on Flash, device and circuits, to solve the technical issues of guidance code in Flash existing in the prior art is easily written over or destroys.This method comprises: obtaining controller is sent to the partial address signal of Flash and the first write control signal of controller output；Wherein, when partial address signal is access Flash, the address signal in addition to it can access the significant address signal of boot partition of Flash；And partial address signal and the first write control signal are subjected to specified logical operation, obtain the second write control signal；Wherein, the validity for specifying logical operation to be used to that partial address signal to be made to limit the first write control signal；Later, it according to the second write control signal, controls Falsh and does not receive controller to the write operation of boot partition.
Description
Technical field
The present invention relates to electronic fields, more particularly, to a kind of Write-protection method based on Flash, device and circuit.
Background technique
Since flash memory (Flash Memory) is in the case where not powered, data will not lose, so often by as one
Kind is capable of the storage medium of store data long term, is widely used in electronic equipment.
Due to Flash, it has the function that (execute In Place) is executed in chip, allows application program straight
It connects and is run in flash, without running application program after code is read in system RAM, so Flash is often used as depositing
Store up the storage medium of application program.The application program being stored in flash is generally divided into guidance code and normal codes, wherein drawing
It leads code to be stored in the boot partition of flash, if the guidance code in boot partition is destroyed or rewritten, will lead to peace
It has filled the electronic equipment exception of application program, cannot start.
In the prior art, the mode of software redundancy or hardware redundancy is generallyd use to prevent the guidance for being stored in Flash
Guidance code in subregion is destroyed or rewrites.But with software redundancy also be only capable of delay guidance code be destroyed or rewrite when
Between, and hardware redundancy will increase cost.
In consideration of it, how effective and inexpensive guidance code prevented in Flash is written over or destroys, become one urgently
Technical problem to be solved.
Summary of the invention
The present invention provides a kind of Write-protection method based on Flash, device and circuit, exists in the prior art to solve
Flash in guidance code the technical issues of being easily written over or destroy.
In a first aspect, in order to solve the above technical problems, a kind of write-protect side based on Flash provided in an embodiment of the present invention
The technical solution of method is as follows:
It obtains controller and is sent to the partial address signal of Flash and the first write control signal of controller output；
Wherein, the partial address signal is when accessing the Flash, except the effective address for the boot partition that can access the Flash
Address signal except signal；
The partial address signal and first write control signal are subjected to specified logical operation, second is obtained and writes control
Signal；Wherein, the specified logical operation is for making the partial address signal limit the effective of first write control signal
Property；
According to second write control signal, controls the Falsh and do not receive the controller to the boot partition
Write operation.
The partial address signal of Flash and the first write control signal of controller output are sent to by obtaining controller
Afterwards, partial address signal and the first write control signal are subjected to specified logical operation, obtain the second write control signal, makes partly
After location signal limits the validity of the first write control signal, according to the second write control signal, controls Falsh and do not receive controller
To the write operation of boot partition；Wherein, when partial address signal is access Flash, except having for the boot partition that can access Flash
The address signal except address signal is imitated, write-protect is carried out to the guidance code stored in the boot partition of Flash to realize
Technical effect.
Optionally, the partial address signal and first write control signal are subjected to specified logical operation, obtain the
Two write control signals, comprising:
Or non-operation is carried out to the binary data of the corresponding each address wire of the partial address signal, obtains intermediate control
Binary data；
The intermediate binary data binary data corresponding with first write control signal that controls is carried out or transported
It calculates, obtains second write control signal.
Optionally, the partial address signal and first write control signal are subjected to specified logical operation, obtain the
Two write control signals, comprising:
Inverse is carried out and then to institute to the corresponding binary data of each address wire in the partial address signal
Some inverse results carry out and operation, obtain intermediate control binary data；
The intermediate binary data binary data corresponding with first write control signal that controls is carried out or transported
It calculates, obtains second write control signal.
Optionally, it according to second write control signal, controls the Falsh and does not receive the controller to the guidance
The write operation of subregion, comprising:
Using second write control signal as the write control signal for carrying out write operation to the Flah；
When the address signal of controller output is the address signal being addressed to the boot partition, institute is determined
Stating the second write control signal is invalid write control signal, and the Falsh is made not receive the controller to the boot partition
Carry out write operation；
When the address signal of controller output is the ground being addressed to the memory space except the boot partition
When the signal of location, determines that second write control signal is effective write control signal, the Falsh is made to receive the controller pair
Memory space except the boot partition carries out write operation.
Second aspect, the embodiment of the invention provides a kind of for the write protector based on Flash, comprising:
Acquiring unit, for obtain controller be sent to Flash partial address signal and controller output the
One write control signal；Wherein, the partial address signal is when accessing the Flash, except the guidance point that can access the Flash
Address signal except the significant address signal in area；
Logical unit, for the partial address signal and first write control signal to be carried out specified logic fortune
It calculates, obtains the second write control signal；Wherein, the specified logical operation is for making the partial address signal limitation described first
The validity of write control signal；
Control unit, for controlling the Falsh and not receiving the controller to institute according to second write control signal
State the write operation of boot partition.
Optionally, the logical unit, is specifically used for:
Or non-operation is carried out to the binary data of the corresponding each address wire of the partial address signal, obtains intermediate control
Binary data；
The intermediate binary data binary data corresponding with first write control signal that controls is carried out or transported
It calculates, obtains second write control signal.
Optionally, the logical unit, is specifically used for:
Inverse is carried out and then to institute to the corresponding binary data of each address wire in the partial address signal
Some inverse results carry out and operation, obtain intermediate control binary data；
The centre is controlled into binary data binary data progress corresponding with the write control signal or operation, is obtained
Obtain second write control signal.
Optionally, described control unit is specifically used for:
Using second write control signal as the write control signal for carrying out write operation to the Flah；
When the address signal of controller output is the address signal being addressed to the boot partition, institute is determined
Stating the second write control signal is invalid write control signal, and the Falsh is made not receive the controller to the boot partition
Carry out write operation；
When the address signal of controller output is the ground being addressed to the memory space except the boot partition
When the signal of location, determines that second write control signal is effective write control signal, the Falsh is made to receive the controller pair
Memory space except the boot partition carries out write operation.
The third aspect, the embodiment of the invention provides a kind of logical operation circuits, comprising:
Nor gate, the nor gate have N number of input terminal, N number of input terminal and access Flash boot partition except
The corresponding address wire input terminal of partial address signal connect one by one, for the address wire input terminal except the boot partition
The binary data received carries out or non-operation；Wherein, N is total port of the address wire input terminal of the partial address signal
Number；
Or door, the write control signal output end of the first write control signal of described or door the input terminal and controller connect
It connects, another described or door input terminal is connect with the output end of the nor gate, for the operation knot to the or non-operation
The binary data of fruit and first control signal output end output carries out or operation；
Described or door output end and writing for the boot partition control and receive end connection, and the Flash is made not receive institute
It states controller and write operation is carried out to the boot partition.
Fourth aspect, the embodiment of the invention provides a kind of logical operation circuits, comprising:
The input terminal of N number of NOT gate, a NOT gate is corresponding with the partial address signal except the boot partition of access Flash
One address wire input terminal connection；Wherein, N is total port number of the address wire input terminal of the partial address signal；
With N+1 input terminal with door, it is described to be connect with the input terminal of door with the output end of N number of NOT gate；
Or door, described or door the input terminal are connect with described with the output end of door, another described or door input
End is connect with the write control signal output end of the first write control signal of the controller；
Described or door output end and writing for the boot partition control and receive end connection, and the Flash is made not receive institute
It states controller and write operation is carried out to the boot partition.
The technical solution in said one or multiple embodiments through the embodiment of the present invention, the embodiment of the present invention at least have
There is following technical effect:
In embodiment provided by the invention, the partial address signal and the control that are sent to Flash by obtaining controller
After first write control signal of device output, partial address signal and the first write control signal are subjected to specified logical operation, obtained
Second write control signal after so that partial address signal is limited the validity of the first write control signal, writes control letter according to second
Number, control Falsh does not receive controller to the write operation of boot partition；Wherein, it when partial address signal is access Flash, removes
The address signal except the significant address signal of the boot partition of Flash can be accessed.To realize in the boot partition of flash
The guidance code of storage carries out the technical effect of write-protect.
Detailed description of the invention
Fig. 1 is a kind of flow chart of the Write-protection method based on Flash provided in an embodiment of the present invention；
Fig. 2 is the data/address bus of Flash provided in an embodiment of the present invention a kind of and the schematic diagram of address bus；
Fig. 3 is the schematic diagram that controller is connect with Flash in the prior art；
Fig. 4 is a kind of memory space schematic diagram of Flash provided in an embodiment of the present invention；
Fig. 5 is a kind of structural schematic diagram one of logical operation circuit provided in an embodiment of the present invention；
Fig. 6 is a kind of structural schematic diagram two of logical operation circuit provided in an embodiment of the present invention；
Fig. 7 is a kind of structural schematic diagram of the write protector based on Flash provided in an embodiment of the present invention.
Specific embodiment
Implementation column of the present invention provides a kind of Write-protection method based on Flash, device and circuit, to solve in the prior art
The technical issues of guidance code in existing Flash is easily written over or destroys.
In order to solve the above technical problems, general thought is as follows for technical solution in the embodiment of the present application:
There is provided a kind of Write-protection method based on Flash, comprising: obtain the partial address letter that controller is sent to Flash
Number with controller output the first write control signal；Wherein, when partial address signal is access Flash, except can access Flash's
Address signal except the significant address signal of boot partition；And partial address signal and the first write control signal are specified
Logical operation obtains the second write control signal；Wherein, specify logical operation for making partial address signal limitation first write control
The validity of signal；Later, it according to the second write control signal, controls Falsh and does not receive controller to the write operation of boot partition.
Due in the above scheme, be by obtain controller be sent to Flash partial address signal and controller it is defeated
After the first write control signal out, partial address signal and the first write control signal are subjected to specified logical operation, obtain second
Write control signal, after making partial address signal limit the validity of the first write control signal, according to the second write control signal, control
Falsh processed does not receive controller to the write operation of boot partition；Wherein, when partial address signal is access Flash, removing can be accessed
Address signal except the significant address signal of the boot partition of Flash.To realize to storing in the boot partition of Flash
The technical effect of guidance code progress write-protect.
In order to better understand the above technical scheme, below by attached drawing and specific embodiment to technical solution of the present invention
It is described in detail, it should be understood that the specific features in the embodiment of the present invention and embodiment are to the detailed of technical solution of the present invention
Thin explanation, rather than the restriction to technical solution of the present invention, in the absence of conflict, the embodiment of the present invention and embodiment
In technical characteristic can be combined with each other.
Referring to FIG. 1, the embodiment of the present invention provides a kind of Write-protection method based on Flash, the treatment process of this method
It is as follows.
Step 101: acquisition controller is sent to the partial address signal of Flash and the first of controller output writes control letter
Number；Wherein, partial address signal be access the Flash when, except the boot partition that can access Flash significant address signal it
Outer address signal.
Step 102: partial address signal and the first write control signal being subjected to specified logical operation, second is obtained and writes control
Signal；Wherein, the validity for specifying logical operation to be used to that partial address signal to be made to limit the first write control signal.
Step 103: according to the second write control signal, controlling Falsh and do not receive controller to the write operation of boot partition.
Fig. 2 is referred to, is 2M with a memory capacity, there are a 21 bit address buses (A0~A20), 15 bit data bus (DQ0~
DQ14 for Flash).The spy of Flash is written by the address bus of access Flash by controller by data/address bus for data
Determine in memory space, controller will to the boot partition of Flash be written data need by the DQ0 in access address bus~
DQ14, and low level signal is also sent in Fig. 3Keep the write-in to Flash effective.
Wherein, the memory space of the corresponding Flash of address wire A0~A15 in address bus is to store drawing for guidance code
Subregion is led, address wire A16~A20 except address wire A0~A15 in address bus is referred to as partial address line, passes through portion
The address signal that controller that the corresponding each address wire of sub-address line receives is sent be in the embodiment of the present invention partly
Location signal,The signal received is the second write control signal described in the embodiment of the present invention.
In the prior art,It is the write control signal of direct received controller, it is specific to control
The connection schematic diagram of device and Flash refer to Fig. 3.
Specifically, by the partial address signal of other subregions except the corresponding boot partition of the guidance code of flash with
First write control signal of controller output carries out specified logical operation, obtains the second write control signal, can pass through following two
Kind mode is realized:
First way: the binary data of each address wire first corresponding to partial address signal carries out or non-operation, obtains
Obtain intermediate control binary data；Again by centre corresponding with the first write control signal binary data of control binary data into
Capable or operation obtains the second write control signal.
For example, the corresponding address wire of partial address signal is A16~A20, then right still by taking 2M Flash above-mentioned as an example
The binary data of the corresponding each address wire of partial address signal, which carries out or non-operation, to be expressed asWherein, any of A16~A20 address wire is corresponding
It is 0 or 1 for binary data ,+represent in logical operation or operation, AdRepresent intermediate control binary data.
Work as AdWhen=0, represents controller and the corresponding memory space of the boot partition of Flash is operated；Work as AdWhen=1,
Controller is represented to operate the corresponding memory space of other subregions except the boot partition of Flash.
Enabled output end is write due to controllerThe signal of output (is claimed in embodiments of the present invention
Be the first write control signal) be that low level is effective, the input write enable signal end of FlashIt receives
Signal is that low level is effective；So to realize to guidance code (the i.e. failsafe code and normal in boot partition
Code protection) actually carries out write protection to the boot partition of storage guidance code.Therefore work as AdWhen=0, that is, grasp
When accomplishing 0xFFFF or address space below, no matter the write control signal of controller is high level or low level, Flash
Input write enable signal endIt will be high level, forbid write operation；And work as AdWhen=1, operation is arrived
The memory space of 0xFFFF or more, the input write enable signal end of FlashThe signal received should and be controlled
Device processed writes enabled output endThe signal of output is synchronous, i.e., controller can be to the 0xFFFF or more of Flash
Memory space carry out write operation.In this way, controller can be made when carrying out write operation to Flash, prevent from drawing Flash
It leads subregion and carries out write operation, so that the guidance code stored in boot partition be protected not to be written over or destroy.The storage of Flash
Space schematic diagram, refers to Fig. 4.
To realize above-mentioned function, thenWith AdWithThree signals corresponding two into
There should be logical relation as shown in Table 1 between data processed:
Table 1
Table 1 is according to available after karnaugh method:
Wherein ,+in logical operation or operation is represented,Indicate AdIt negates, C1Represent controller
The signal (the first write control signal i.e. in the embodiment of the present invention) of output, C2Represent Flash'sIt receives
Signal (the second write control signal i.e. in the embodiment of the present invention).
By the deformation of formula (1) within the scope of the embodiment of the present invention, such as the formula (2) being explained below.
The second way: first to the corresponding binary data of each address wire in partial address signal carry out inverse it
Afterwards, then to all inverse result progress and operation, intermediate control binary data is obtained；Later, by centre control two into
Data processed binary data corresponding with the first write control signal carries out or operation, obtains the second write control signal.
For example, still by taking the example in the first situation as an example, expression formula can be with are as follows:
Wherein, & represents in logical operation and operation, due to the principle of expression formula (2) and principle, the symbol of expression formula (1)
Number meaning is identical, and details are not described herein.
After obtaining the second write control signal by above two mode, it can be controlled according to the second write control signal
Flash does not receive controller and carries out write operation to the boot partition of Flash.
Particularly, using the second write control signal as the write control signal for carrying out write operation to Flah；When controller is defeated
When address signal out is the address signal being addressed to boot partition, determine that the second write control signal writes control for invalid
Signal makes Falsh not receive controller and carries out write operation to boot partition；When the address signal of controller output is to guidance point
When the address signal that the memory space except area is addressed, determines that the second write control signal is effective write control signal, make
Falsh receives controller and carries out write operation to the memory space except the boot partition.
For example, still by taking 2M Flash above-mentioned as an example, when the address signal of controller output is that (0x is represented 0x010001
16 binary datas, 16 binary datas represent 4 binary data, the corresponding address wire of a binary data), first
Control signal is 0 (i.e. low level signal).As can be seen from FIG. 2, the corresponding data of the address wire of boot partition are address signal
" 0001 " (i.e. low 16 bit binary data in address signal 0x010001) in 0x010001, and the portion except boot partition
Sub-address line corresponding data is " 01 " (i.e. most-significant byte binary system in address signal 0x010001 in address signal 0x010001
Data 01).According to the specified logic in aforementioned expression (1) or expression formula (2), to partial address signal corresponding data (01) and
After the corresponding data of first control signal (0) carry out operation, obtaining second control signal as 0 (is effectively to write for Flash
Control signal), i.e. Flash receives controller and carries out write operation to the address (0x010001) of non-guide subregion.
When the address signal of controller output is 0x000FFF, first control signal is 0 (i.e. low level signal).According to figure
2 it is found that the corresponding data of the address wire of boot partition are " 0FFF " (i.e. address signal in address signal 0x000FFF
Low 16 bit binary data in 0x000FFF), and the partial address line corresponding data except boot partition is address signal
" 00 " (i.e. most-significant byte binary data 00 in address signal 0x000FFF) in 0x000FFF.According to aforementioned expression (1) or
Specified logic in expression formula (2), to partial address signal corresponding data (00) and the corresponding data of first control signal (0) into
After row operation, obtaining second control signal is 1 (being invalid write control signal for Flash), i.e., Flash does not receive control
Device carries out write operation to the address (0x000FFF) of boot partition.
It can also be realized by actual hardware circuit for above-mentioned expression formula (1), expression formula (2), it below will be respectively
It is introduced.
For the hardware circuit implementation of expression formula (1), following introduction is referred to.
Based on the same inventive concept, it is provided in one embodiment of the invention a kind of for the logic fortune based on Flash write-protect
Circuit is calculated, the concrete principle of the guard method of the circuit can be found in the description of embodiment of the method part, and overlaps will not be repeated,
Fig. 5 is referred to, which includes:
Nor gate 501, nor gate 501 have N number of input terminal, N number of input terminal and access Flash52 boot partition except
The corresponding address wire input terminal of partial address signal connect one by one, for except boot partition address wire input terminal receive
The binary data arrived carries out or non-operation；Wherein, N is total port number of the address wire input terminal of partial address signal；
Or the write control signal output of the first write control signal of an input terminal and controller 51 for door 502 or door 502
The output end connection of another input terminal AND OR NOT gate 501 of end connection or door 502, for the operation result to or non-operation
With the binary data progress or operation of the output of first control signal output end；
Or door 502 output end and boot partition write control and receive end connection, so that Flash52 is not received controller 51 right
The boot partition of Flash52 carries out write operation.
In Fig. 5, when data are written to Flash603 in controller 52, have by one in logical operation circuit 50
The nor gate 502 of N number of input terminal, the address signal exported to controller 51 are filtered, and controller 51 is made to be intended to access
When Flash52 stores the boot partition corresponding address space of guidance code, the or non-operation result of generation and controller 51
First write control signal carries out or operation, and then right by the or non-operation result (i.e. second control signal) that nor gate 51 generates
The validity of first write control signal of controller 51 is controlled, with prevent controller 51 to the boot partition of Flash52 into
Row write operation, so that the guidance code stored in the boot partition of Flash52 be protected not to be written over or destroy.
It should be noted that in Fig. 5, the Ai in controller 51 and Flash52 is represented between controller 51 and Flash52
Address bus in i-th of address wire, respectively correspond controller 51 and i-th of address port of Flash52；A (i+1) is represented
I+1 address wire in address bus respectively corresponds controller 51 and the i+1 address port of Flash52；A (i+2) generation
The i-th+2 address wires in table address bus respectively correspond controller 51 and the i-th+2 address ports of Flash52；A(i+3)
The i-th+3 address wires in address bus are represented, controller 51 and the i-th+3 address ports of Flash52 are respectively corresponded；A(i+
N i-th+N number of address wire in address bus) is represented, the i-th+N number of address port of controller 51 and Flash52 are respectively corresponded；Its
In, i and N are natural number.
For the hardware circuit implementation of expression formula (2), following introduction is referred to.
Based on the same inventive concept, a kind of logic for the write-protect based on Flash is provided in one embodiment of the invention
Computing circuit, the concrete principle of the guard method of the circuit can be found in the description of embodiment of the method part, and it is no longer superfluous to repeat place
It states, refers to Fig. 6, which includes:
Partial address except N number of NOT gate 601, the input terminal of a NOT gate 601 and the boot partition of access Flash62 is believed
Number corresponding address wire input terminal connection；Wherein, N is total port number of the address wire input terminal of partial address signal；
With N+1 input terminal with door 602, connect with the input terminal of door 602 with the output end of N number of NOT gate 601；
Or an input terminal of door 603 or door is connect with the output end with door or another input terminal and controller of door
The write control signal output end of 61 the first write control signal connects；
Or door 603 output end and boot partition write control and receive end connection, so that Flash62 is not received controller 61 right
The boot partition of Flash62 carries out write operation.
In Fig. 6, when data are written to Flash62 in controller 61, pass through N number of NOT gate in logical operation circuit 60
601 and one it is with N+1 input terminal with door 62, the address signal of the output of controller 61 is filtered, controller 64 is made
In the corresponding address space of boot partition of Flash62 to be accessed storage guidance code, by by the non-fortune of N number of NOT gate 601
Calculate result send with door 602 generate with operation result (i.e. the second write control signal), to the first write control signal of controller 61
Validity controlled, to prevent controller 61 from carrying out write operation to the boot partition of Flash62, to protect
The guidance code stored in the boot partition of Flash62 is not written over or destroys.
It is to be appreciated that in actual use, NOT gate 601 can be N number of non-gating element；It is also possible to have N number of non-
One electronic component of door, such as: the NOT gate with N number of input terminal and N+1 output end, and the corresponding output of an input terminal
End；NOT gate either by several with multi input end and multi output end such as has the electronic component of 4 NOT gates, if desired N=
8, then need 2 electronic components, specific NOT gate 601 be several electronic components it is not limited here.
It should be noted that in Fig. 6, the Ai in controller 61 and Flash62 is represented between controller 61 and Flash62
Address bus in i-th of address wire, respectively correspond controller 61 and i-th of address port of Flash62；A (i+1) is represented
I+1 address wire in address bus respectively corresponds controller 61 and the i+1 address port of Flash62；A (i+2) generation
The i-th+2 address wires in table address bus respectively correspond controller 61 and the i-th+2 address ports of Flash62；A(i+3)
The i-th+3 address wires in address bus are represented, controller 61 and the i-th+3 address ports of Flash62 are respectively corresponded；A(i+
N i-th+N number of address wire in address bus) is represented, the i-th+N number of address port of controller 61 and Flash62 are respectively corresponded；Its
In, i and N are natural number.
It is above-mentioned based on the Write-protection method of Flash except through electronic component be made circuit board (i.e. logical operation circuit) it
Outside, it can also be realized in programmable logic controller (PLC), such as field programmable gate array (Field Programmable Gate
Array, FPGA), Complex Programmable Logic Devices (Complex Programmable Logic Device, CPLD).
Based on the same inventive concept, it provides a kind of for the write protector based on Flash in one embodiment of the invention, answers
For in programmable logic circuit, the concrete principle of the guard method of the device to can be found in the description of embodiment of the method part, weight
Multiple place repeats no more, and refers to Fig. 7, which includes:
Acquiring unit, for obtain controller be sent to Flash partial address signal and controller output the
One write control signal；Wherein, the partial address signal is when accessing the Flash, except the guidance point that can access the Flash
Address signal except the significant address signal in area；
Logical unit, for the partial address signal and first write control signal to be carried out specified logic fortune
It calculates, obtains the second write control signal；Wherein, the specified logical operation is for making the partial address signal limitation described first
The validity of write control signal；
Control unit, for controlling the Falsh and not receiving the controller to institute according to second write control signal
State the write operation of boot partition.
Optionally, the logical unit, is specifically used for:
Or non-operation is carried out to the binary data of the corresponding each address wire of the partial address signal, obtains intermediate control
Binary data；
The intermediate binary data binary data corresponding with first write control signal that controls is carried out or transported
It calculates, obtains second write control signal.
Optionally, the logical unit, is specifically used for:
Inverse is carried out and then to institute to the corresponding binary data of each address wire in the partial address signal
Some inverse results carry out and operation, obtain intermediate control binary data；
The centre is controlled into binary data binary data progress corresponding with the write control signal or operation, is obtained
Obtain second write control signal.
Optionally, described control unit is specifically used for:
Using second write control signal as the write control signal for carrying out write operation to the Flah；
When the address signal of controller output is the address signal being addressed to the boot partition, institute is determined
Stating the second write control signal is invalid write control signal, and the Falsh is made not receive the controller to the boot partition
Carry out write operation；
When the address signal of controller output is the ground being addressed to the memory space except the boot partition
When the signal of location, determines that second write control signal is effective write control signal, the Falsh is made to receive the controller pair
Memory space except the boot partition carries out write operation.
In embodiment provided by the invention, the partial address signal and the control that are sent to Flash by obtaining controller
After first write control signal of device output, partial address signal and the first write control signal are subjected to specified logical operation, obtained
Second write control signal after so that partial address signal is limited the validity of the first write control signal, writes control letter according to second
Number, control Falsh does not receive controller to the write operation of boot partition；Wherein, it when partial address signal is access Flash, removes
The address signal except the significant address signal of the boot partition of Flash can be accessed.To realize in the boot partition of Flash
The guidance code of storage carries out the technical effect of write-protect.
It should be understood by those skilled in the art that, the embodiment of the present invention can provide as the production of method, system or computer program
Product.Therefore, in terms of the embodiment of the present invention can be used complete hardware embodiment, complete software embodiment or combine software and hardware
Embodiment form.Moreover, it wherein includes computer available programs generation that the embodiment of the present invention, which can be used in one or more,
The meter implemented in the computer-usable storage medium (including but not limited to magnetic disk storage, CD-ROM, optical memory etc.) of code
The form of calculation machine program product.
The embodiment of the present invention be referring to according to the method for the embodiment of the present invention, equipment (system) and computer program product
Flowchart and/or the block diagram describe.It should be understood that can be realized by computer program instructions in flowchart and/or the block diagram
The combination of process and/or box in each flow and/or block and flowchart and/or the block diagram.It can provide these calculating
Processing of the machine program instruction to general purpose computer, special purpose computer, Embedded Processor or other programmable data processing devices
Device is to generate a machine, so that being generated by the instruction that computer or the processor of other programmable data processing devices execute
For realizing the function of being specified in one or more flows of the flowchart and/or one or more blocks of the block diagram
Device.
These computer program instructions, which may also be stored in, is able to guide computer or other programmable data processing devices with spy
Determine in the computer-readable memory that mode works, so that it includes referring to that instruction stored in the computer readable memory, which generates,
Enable the manufacture of device, the command device realize in one box of one or more flows of the flowchart and/or block diagram or
The function of being specified in multiple boxes.
These computer program instructions also can be loaded onto a computer or other programmable data processing device, so that counting
Series of operation steps are executed on calculation machine or other programmable devices to generate computer implemented processing, thus in computer or
The instruction executed on other programmable devices is provided for realizing in one or more flows of the flowchart and/or block diagram one
The step of function of being specified in a box or multiple boxes.
Obviously, various changes and modifications can be made to the invention without departing from essence of the invention by those skilled in the art
Mind and range.In this way, if these modifications and changes of the present invention belongs to the range of the claims in the present invention and its equivalent technologies
Within, then the present invention is also intended to include these modifications and variations.
Claims (10)
1. a kind of Write-protection method based on Flash characterized by comprising
It obtains controller and is sent to the partial address signal of Flash and the first write control signal of controller output；Wherein,
The partial address signal be access the Flash when, except the boot partition that can access the Flash significant address signal it
Outer address signal；
The partial address signal and first write control signal are subjected to specified logical operation, second is obtained and writes control letter
Number；Wherein, the validity that the specified logical operation is used to that the partial address signal to be made to limit first write control signal；
According to second write control signal, controls the Falsh and do not receive the controller and behaviour is write to the boot partition
Make.
2. the method as described in claim 1, which is characterized in that by the partial address signal and first write control signal
Specified logical operation is carried out, the second write control signal is obtained, comprising:
Or non-operation is carried out to the binary data of the corresponding each address wire of the partial address signal, obtain intermediate control two into
Data processed；
The centre is controlled into binary data binary data progress corresponding with first write control signal or operation, is obtained
Obtain second write control signal.
3. the method as described in claim 1, which is characterized in that by the partial address signal and first write control signal
Specified logical operation is carried out, the second write control signal is obtained, comprising:
Inverse is carried out and then to all to the corresponding binary data of each address wire in the partial address signal
Inverse result carries out and operation, obtains intermediate control binary data；
The centre is controlled into binary data binary data progress corresponding with first write control signal or operation, is obtained
Obtain second write control signal.
4. the method as described in any claim of claim 1-3, which is characterized in that according to second write control signal, control
The Falsh does not receive the controller to the write operation of the boot partition, comprising:
Using second write control signal as the write control signal for carrying out write operation to the Flah；
When the address signal of controller output is the address signal being addressed to the boot partition, described the is determined
Two write control signals are invalid write control signal, so that the Falsh is not received the controller and carry out to the boot partition
Write operation；
When the address signal of controller output is that the address being addressed to the memory space except the boot partition is believed
Number when, determine that second write control signal is effective write control signal, the Falsh made to receive the controller to described
Memory space except boot partition carries out write operation.
5. a kind of write protector based on flash characterized by comprising
Acquiring unit, for obtaining, controller is sent to the partial address signal of Flash and the controller exports first writes
Control signal；Wherein, the partial address signal is when accessing the Flash, except the boot partition that can access the Flash
Address signal except significant address signal；
Logical unit, for the partial address signal and first write control signal to be carried out specified logical operation,
Obtain the second write control signal；Wherein, the specified logical operation is for writing the partial address signal limitation described first
Control the validity of signal；
Control unit controls the Falsh and does not receive the controller and draw to described for according to second write control signal
Lead the write operation of subregion.
6. device as claimed in claim 5, which is characterized in that the logical unit is specifically used for:
Or non-operation is carried out to the binary data of the corresponding each address wire of the partial address signal, obtain intermediate control two into
Data processed；
The centre is controlled into binary data binary data progress corresponding with first write control signal or operation, is obtained
Obtain second write control signal.
7. device as claimed in claim 5, which is characterized in that the logical unit is specifically used for:
Inverse is carried out and then to all to the corresponding binary data of each address wire in the partial address signal
Inverse result carries out and operation, obtains intermediate control binary data；
The centre is controlled into binary data binary data progress corresponding with the write control signal or operation, obtains institute
State the second write control signal.
8. the device as described in any claim of claim 5-7, which is characterized in that described control unit is specifically used for:
Using second write control signal as the write control signal for carrying out write operation to the Flah；
When the address signal of controller output is the address signal being addressed to the boot partition, described the is determined
Two write control signals are invalid write control signal, so that the Falsh is not received the controller and carry out to the boot partition
Write operation；
When the address signal of controller output is that the address being addressed to the memory space except the boot partition is believed
Number when, determine that second write control signal is effective write control signal, the Falsh made to receive the controller to described
Memory space except boot partition carries out write operation.
9. a kind of logical operation circuit characterized by comprising
Nor gate, the nor gate have N number of input terminal, N number of input terminal and the portion except the boot partition of access Flash
The corresponding address wire input terminal of sub-address signal connects one by one, for receiving to the address wire input terminal except the boot partition
The binary data arrived carries out or non-operation；Wherein, N is total port number of the address wire input terminal of the partial address signal；
Or door, the write control signal output end of the first write control signal of described or door the input terminal and controller connect,
Another described or door input terminal is connect with the output end of the nor gate, for the or non-operation operation result with
The binary data of the first control signal output end output carries out or operation；
Described or door output end and writing for the boot partition control and receive end connection, and the Flash is made not receive the control
Device processed carries out write operation to the boot partition.
10. a kind of logical operation circuit characterized by comprising
N number of NOT gate, the input terminal and the partial address signal except the boot partition of access Flash of a NOT gate are one corresponding
The connection of address wire input terminal；Wherein, N is total port number of the address wire input terminal of the partial address signal；
With N+1 input terminal with door, it is described to be connect with the input terminal of door with the output end of N number of NOT gate；
Or door, described or door the input terminal are connect with described with the output end of door, another described or door input terminal with
The write control signal output end of first write control signal of controller connects；
Described or door output end and writing for the boot partition control and receive end connection, and the Flash is made not receive the control
Device processed carries out write operation to the boot partition.
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| CN201811360116.0A CN109522241A (en) | 2018-11-15 | 2018-11-15 | A kind of Write-protection method based on Flash, device and circuit |
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| CN201811360116.0A CN109522241A (en) | 2018-11-15 | 2018-11-15 | A kind of Write-protection method based on Flash, device and circuit |
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| CN1222885C (en) * | 2002-08-05 | 2005-10-12 | 华为技术有限公司 | FLASH data protecting method and its FLASH curcuit |
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