CN107621998A - A kind of High Availabitity FLASH system and method based on storage system - Google Patents
A kind of High Availabitity FLASH system and method based on storage system Download PDFInfo
- Publication number
- CN107621998A CN107621998A CN201710912356.6A CN201710912356A CN107621998A CN 107621998 A CN107621998 A CN 107621998A CN 201710912356 A CN201710912356 A CN 201710912356A CN 107621998 A CN107621998 A CN 107621998A
- Authority
- CN
- China
- Prior art keywords
- switching control
- flash
- control chip
- pch
- bios program
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Landscapes
- Stored Programmes (AREA)
Abstract
The invention discloses a kind of High Availabitity FLASH system and method based on storage system, including PCH, switching control chip and multiple FLASH, each FLASH internal memories to contain identical bios program；The first end of PCH output end connection switching control chip, reads signal to switching control chip, and read the bios program of switching control chip return for sending；When the bios program read is wrong, switch-over control signal is sent to switching control chip；The end of multichannel second of switching control chip connects each FLASH respectively, after receiving switch-over control signal, controls the connecting path at itself the second end to switch to and is turned on other FLASH.The present invention designs multiple FLASH as standby, improves the reliability and high availability of storage system.
Description
Technical field
The present invention relates to High Availabitity technical field, more particularly to a kind of High Availabitity FLASH systems based on storage system
And its method.
Background technology
With the development of big data, cloud, smart city etc., the development to storage also brings very big opportunity.In order to strengthen
The development of big data, cloud, smart city, the stability of storage device are most important, it may be said that are related to the stabilization of whole system
Property and development space.If storage device is unstable or itself will limit the big data epoch if capacity is restricted
Development.
In the design of some storage systems, usual PCH (Platform Controller Hub, in platform controller
The heart) by the plug-in FLASH of spi bus, deposit bios program.Bios program is very important for whole system, rises
Start guiding and some important parameter configurations are all stored in the FL ASH chips, if abnormal shape occurs in FLASH chip
State or problem, then whole storage system can be caused to collapse, serious situation can even cause the loss of data.To current big
Data can be described as the lifeline of the lifeline of an information firm, even big data for data age, so being not allow
Perhaps there is the mistake of any point in storage device.
Therefore, how to provide a kind of high High Availabitity FLASH system and method based on storage system of reliability is this
Art personnel need to solve the problems, such as at present.
The content of the invention
It is an object of the invention to provide a kind of High Availabitity FLASH system and method based on storage system, design are multiple
FLASH improves the reliability and high availability of storage system as standby.
In order to solve the above technical problems, the invention provides a kind of High Availabitity FLASH systems based on storage system, including
PCH, switching control chip and multiple FLASH, each FLASH internal memories contain identical bios program；
The output end of the PCH connects the first end of the switching control chip, is cut for sending reading signal to described
Control chip is changed, and reads the bios program that the switching control chip returns；When the bios program read is wrong, send
Switch-over control signal is to the switching control chip；
The end of multichannel second of the switching control chip connects each FLASH respectively, for receiving the switching control
After signal processed, control the connecting path at itself the second end to switch to and turned on other FLASH.
Preferably, the output end of the PCH is connected by spi bus with the first end of the switching control chip.
Preferably, the output end of the PCH passes through spi bus and GPIO buses and the switching control chip respectively
First end connects；
Wherein, the spi bus is used to transmit the reading signal and reads bios program, and the GPIO buses are used for
Send switch-over control signal.
Preferably, the end of every road second of the switching control chip connects corresponding FLASH by spi bus respectively.
Preferably, the switching control chip is specially CPLD CPLDs.
Preferably, include in the switching control chip：
Multiple SPI interface modules, one of them described SPI interface module are led to as the first end of the switching control chip
Cross spi bus to communicate with the PCH, remaining described SPI interface module is led to as the two-way at the end of switching control chip second
Road interface is communicated with each FLASH respectively；
Cache module, for caching the bios program read out of described FLASH；
Switching control module, after receiving the switch-over control signal, the connecting path at itself the second end is controlled to switch
Extremely turned on other FLASH.
In order to solve the above technical problems, present invention also offers a kind of High Availabitity FLASH methods based on storage system, base
In the system as described in any of the above item, methods described includes：
PCH, which is sent, reads signal to switching control chip；
The BIOS in the FLASH of current connecting path conducting is read after the switching control chip reception reading signal
Program is cached；
The PCH reads the bios program that the switching control chip returns and detects whether it wrong, is cut if so, sending
Control signal is changed to the switching control chip；
After the switching control chip receives the switch-over control signal, the connecting path at itself the second end is controlled to switch to
Turned on other FLASH.
The invention provides a kind of High Availabitity FLASH system and method based on storage system, PCH is cut by one
Change control chip and connect multiple FLASH, each FLASH internal memories contain identical bios program, a FLASH as main FLASH,
Remaining FLASH is as standby, and when problem occurs for the bios program in main FLASH, then PCH is cut by switching control chip controls
A standby FLASH for changing rear end uses as main FLASH.By means of the invention it is possible to reducing FLASH chip there is abnormality
When caused storage system can not normal use situation, improve the reliability of storage system, ensure that the height of storage system can
The property used.
Brief description of the drawings
Technical scheme in order to illustrate the embodiments of the present invention more clearly, below will be to institute in prior art and embodiment
The accompanying drawing needed to use is briefly described, it should be apparent that, drawings in the following description are only some implementations of the present invention
Example, for those of ordinary skill in the art, on the premise of not paying creative work, can also be obtained according to these accompanying drawings
Obtain other accompanying drawings.
Fig. 1 is a kind of structural representation of the High Availabitity FLASH systems based on storage system provided by the invention；
Fig. 2 is a kind of flow chart of the process of the High Availabitity FLASH methods based on storage system provided by the invention.
Embodiment
The core of the present invention is to provide a kind of High Availabitity FLASH system and method based on storage system, and design is multiple
FLASH improves the reliability and high availability of storage system as standby.
To make the purpose, technical scheme and advantage of the embodiment of the present invention clearer, below in conjunction with the embodiment of the present invention
In accompanying drawing, the technical scheme in the embodiment of the present invention is clearly and completely described, it is clear that described embodiment is
Part of the embodiment of the present invention, rather than whole embodiments.Based on the embodiment in the present invention, those of ordinary skill in the art
The every other embodiment obtained under the premise of creative work is not made, belongs to the scope of protection of the invention.
Shown in Figure 1 the invention provides a kind of High Availabitity FLASH systems based on storage system, Fig. 1 is the present invention
A kind of structural representation of the High Availabitity FLASH systems based on storage system provided；The system includes PCH1, switching control core
Piece 2 and multiple FLASH3, each FLASH3 internal memories contain identical bios program；
The first end of PCH1 output end connection switching control chip 2, signal is read to switching control chip for sending
2, and read BIOS (Basic Input Output System, basic input output system) journey of the return of switching control chip 2
Sequence；When the bios program read is wrong, switch-over control signal is sent to switching control chip 2；
The end of multichannel second of switching control chip 2 connects each FLASH3 respectively, after receiving switch-over control signal, control
The connecting path for making itself the second end is switched to and turned on other FLASH3.
As preferable, the second end of switching control chip 2 is typically provided two-way, that is, is used to connecting two FLASH3, and one
Individual FLASH3 is as main FLASH3, and another FLASH3 is as standby FLASH3.Certainly, specifically set several roads standby here
FLASH3 can be depending on self-demand, and this is not limited by the present invention.
Wherein, the function in the present invention in switching control chip 2 and PCH1 can be entered using VHDL hardware description languages
Row programming, certainly, this is not limited by the present invention.
It is understood that PCH1 refers to that is realized a standard Intel modules, it is outer to be mainly used in circumscribed USB, SATA disk etc.
And if for configuring some important parameters of whole system by reading BIOS configuration information, such as DDR reading speed
The use etc. of degree, NVDIMM.
In one embodiment, PCH1 output end is connected by spi bus with the first end of switching control chip 2.This
When, the reading signal and switch-over control signal of PCH1 outputs are sent to switching control chip 2 by the spi bus.
In another embodiment, PCH1 output end passes through spi bus and GPIO (General Purpose respectively
Input Output, universal input/output) bus is connected with the first end of switching control chip 2；
Wherein, SPI (Serial Peripheral Interface, Serial Peripheral Interface (SPI)) bus, which is used to transmit, reads letter
Number and read bios program, GPIO buses be used for send switch-over control signal.
It is further known that the end of every road second of switching control chip 2 connects corresponding FLASH3 by spi bus respectively.
Preferably, switching control chip 2 be specially CPLD (Complex Programmable Logic Device,
CPLD).
Specifically, include in switching control chip 2：
Multiple SPI interface modules, one of SPI interface module are total by SPI as the first end of switching control chip 2
Line communicates with PCH1, remaining SPI interface module as the end of switching control chip 2 second two-way access interface respectively with it is each
FLASH3 is communicated；
Cache module, for caching the bios program read out of FLASH3；
Switching control module, after receiving switch-over control signal, control itself the second end connecting path switch to
Other FLASH3 are turned on.
Wherein, the spi bus agreement of SPI interface module review mark here.
The invention provides a kind of High Availabitity FLASH systems based on storage system, PCH is passed through into a switching control core
Piece connects multiple FLASH, and each FLASH internal memories contain identical bios program, a FLASH as main FLASH, remaining
FLASH is as standby, when problem occurs for the bios program in main FLASH, then after PCH is switched by switching control chip controls
One standby FLASH at end uses as main FLASH.Occur leading during abnormality by means of the invention it is possible to reduce FLASH chip
The storage system of cause can not normal use situation, improve the reliability of storage system, ensure that the high availability of storage system.
Present invention also offers a kind of High Availabitity FLASH methods based on storage system, what it is based on such as any of the above item is
System, shown in Figure 2, Fig. 2 is a kind of flow of the process of the High Availabitity FLASH methods based on storage system provided by the invention
Figure.This method includes：
Step s1：PCH, which is sent, reads signal to switching control chip；
Step s2：The BIOS in the FLASH of current connecting path conducting is read after switching control chip reception reading signal
Program is cached；
Step s3：PCH reads the bios program that switching control chip returns and detects whether it wrong, is cut if so, sending
Control signal is changed to switching control chip；
Step s4：After switching control chip receives switch-over control signal, the connecting path at itself the second end is controlled to switch to
Turned on other FLASH.
The invention provides a kind of High Availabitity FLASH methods based on storage system, PCH is passed through into a switching control core
Piece connects multiple FLASH, and each FLASH internal memories contain identical bios program, a FLASH as main FLASH, remaining
FLASH is as standby, when problem occurs for the bios program in main FLASH, then after PCH is switched by switching control chip controls
One standby FLASH at end uses as main FLASH.Occur leading during abnormality by means of the invention it is possible to reduce FLASH chip
The storage system of cause can not normal use situation, improve the reliability of storage system, ensure that the high availability of storage system.
Described above is only embodiment of the present invention citing, and the invention is not restricted to above example.Relevant speciality technology people
The oher improvements and changes that member deduces out in the case where not departing from spirit of the invention and concept thereof, should be included in the protection of the present invention
Within the scope of.
It should also be noted that, in this manual, such as first and second or the like relational terms be used merely to by
One entity or operation make a distinction with another entity or operation, and not necessarily require or imply these entities or operation
Between any this actual relation or order be present.Moreover, term " comprising ", "comprising" or its any other variant meaning
Covering including for nonexcludability, so that process, method, article or equipment including a series of elements not only include that
A little key elements, but also the other element including being not expressly set out, or also include for this process, method, article or
The intrinsic key element of equipment.In the absence of more restrictions, the key element limited by sentence "including a ...", is not arranged
Except other identical element in the process including the key element, method, article or equipment being also present.
The foregoing description of the disclosed embodiments, professional and technical personnel in the field are enable to realize or using the present invention.
A variety of modifications to these embodiments will be apparent for those skilled in the art, as defined herein
General Principle can be realized in other embodiments without departing from the spirit or scope of the present invention.Therefore, it is of the invention
The embodiments shown herein is not intended to be limited to, and is to fit to and principles disclosed herein and features of novelty phase one
The most wide scope caused.
Claims (7)
1. a kind of High Availabitity FLASH systems based on storage system, it is characterised in that including PCH, switching control chip and more
Individual FLASH, each FLASH internal memories contain identical bios program；
The output end of the PCH connects the first end of the switching control chip, and signal is read to the switching control for sending
Coremaking piece, and read the bios program that the switching control chip returns；When the bios program read is wrong, switching is sent
Control signal is to the switching control chip；
The end of multichannel second of the switching control chip connects each FLASH respectively, for receiving the switching control letter
After number, control the connecting path at itself the second end to switch to and turned on other FLASH.
2. system according to claim 1, it is characterised in that the output end of the PCH passes through spi bus and the switching
The first end connection of control chip.
3. system according to claim 1, it is characterised in that the output end of the PCH respectively by spi bus and
GPIO buses are connected with the first end of the switching control chip；
Wherein, the spi bus is used to transmit the reading signal and reads bios program, and the GPIO buses are used to send
Switch-over control signal.
4. system according to claim 1 or 2, it is characterised in that the end of every road second difference of the switching control chip
Corresponding FLASH is connected by spi bus.
5. system according to claim 4, it is characterised in that the switching control chip is specially CPLD complex programmables
Logical device.
6. system according to claim 1, it is characterised in that include in the switching control chip：
Multiple SPI interface modules, one of them described SPI interface module pass through as the first end of the switching control chip
Spi bus communicates with the PCH, two-way path of remaining described SPI interface module as the end of switching control chip second
Interface is communicated with each FLASH respectively；
Cache module, for caching the bios program read out of described FLASH；
Switching control module, after receiving the switch-over control signal, control itself the second end connecting path switch to
Other FLASH are turned on.
A kind of 7. High Availabitity FLASH methods based on storage system, it is characterised in that based on such as any one of claim 1-6 institutes
The system stated, methods described include：
PCH, which is sent, reads signal to switching control chip；
The bios program in the FLASH of current connecting path conducting is read after the switching control chip reception reading signal
Cached；
The PCH reads the bios program that the switching control chip returns and detects whether it wrong, if so, sending switching control
Signal processed is to the switching control chip；
After the switching control chip receives the switch-over control signal, control the connecting path at itself the second end switch to and its
His FLASH is turned on.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201710912356.6A CN107621998A (en) | 2017-09-29 | 2017-09-29 | A kind of High Availabitity FLASH system and method based on storage system |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201710912356.6A CN107621998A (en) | 2017-09-29 | 2017-09-29 | A kind of High Availabitity FLASH system and method based on storage system |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| CN107621998A true CN107621998A (en) | 2018-01-23 |
Family
ID=61091064
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN201710912356.6A Pending CN107621998A (en) | 2017-09-29 | 2017-09-29 | A kind of High Availabitity FLASH system and method based on storage system |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN107621998A (en) |
Citations (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US20090240934A1 (en) * | 2008-03-21 | 2009-09-24 | Asustek Computer Inc. | Computer system with dual boot-program area and method of booting the same |
| CN102662905A (en) * | 2012-05-03 | 2012-09-12 | 天津市英贝特航天科技有限公司 | Connecting circuit of LPC (Low Pin Count) bus and NOR FLASH BIOS chip |
| CN103970626A (en) * | 2014-05-12 | 2014-08-06 | 浪潮电子信息产业股份有限公司 | Redundant design of FLASH for FPGA configuration in server system |
| CN105677416A (en) * | 2016-01-07 | 2016-06-15 | 上海斐讯数据通信技术有限公司 | Uboot upgrading control system and method |
| CN105700970A (en) * | 2014-11-25 | 2016-06-22 | 英业达科技有限公司 | Server system |
| CN106886441A (en) * | 2017-02-28 | 2017-06-23 | 郑州云海信息技术有限公司 | A kind of server system and FLASH collocation methods |
-
2017
- 2017-09-29 CN CN201710912356.6A patent/CN107621998A/en active Pending
Patent Citations (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US20090240934A1 (en) * | 2008-03-21 | 2009-09-24 | Asustek Computer Inc. | Computer system with dual boot-program area and method of booting the same |
| CN102662905A (en) * | 2012-05-03 | 2012-09-12 | 天津市英贝特航天科技有限公司 | Connecting circuit of LPC (Low Pin Count) bus and NOR FLASH BIOS chip |
| CN103970626A (en) * | 2014-05-12 | 2014-08-06 | 浪潮电子信息产业股份有限公司 | Redundant design of FLASH for FPGA configuration in server system |
| CN105700970A (en) * | 2014-11-25 | 2016-06-22 | 英业达科技有限公司 | Server system |
| CN105677416A (en) * | 2016-01-07 | 2016-06-15 | 上海斐讯数据通信技术有限公司 | Uboot upgrading control system and method |
| CN106886441A (en) * | 2017-02-28 | 2017-06-23 | 郑州云海信息技术有限公司 | A kind of server system and FLASH collocation methods |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| DE102004033363B4 (en) | Multi-standard protocol storage device | |
| CN102045608B (en) | Network device for optical communication and method thereof for automatically configuring exchange interface | |
| CN105955898A (en) | SAS hard disk and NVMe hard disk compatible hard disk backplane | |
| CN103500154B (en) | A kind of serial bus interface chip, serial bus transmission system and method | |
| JP2009259210A (en) | Method, apparatus, logic device and storage system for power-fail protection | |
| CN101763331A (en) | System and method for realizing I2C bus control | |
| US20160196232A1 (en) | Commissioning Method, Master Control Board, and Service Board | |
| US8296487B1 (en) | SATA pass through port | |
| CN102609376A (en) | Serial bus memory, serial bus transmission system and method | |
| CN101169673A (en) | Real-time timepiece chip interface circuit control method and real-time timepiece control circuit | |
| EP2674870A1 (en) | A circuit for memory sharing | |
| CN214337931U (en) | Network data transmission system and switch with built-in network data transmission system | |
| CN107621998A (en) | A kind of High Availabitity FLASH system and method based on storage system | |
| CN102855145B (en) | Starting method and starting system of embedding type electronic device | |
| WO2006055149A1 (en) | Systems and methods for monitoring and controlling binary state devices using a memory device | |
| CN104200148A (en) | Smart card redundancy switching method based on independently domestic redundancy server | |
| CN101739367B (en) | Method and device for storing and controlling various buses | |
| CN205608716U (en) | Multiunit optical module communication interface switching circuit | |
| CN110851393B (en) | USB conversion control board card with Aurora interface and method | |
| CN201936293U (en) | Numerical control program transmission device based on singlechip and USB flash disk | |
| CN206270952U (en) | A kind of card reader | |
| CN102968168A (en) | Method for enabling wire clip, management board and wire clip | |
| CN102789435B (en) | Serial storage and method and system for dividing storage regions | |
| CN202838091U (en) | Double bridge piece mainboard supporting SR 5690 redundancy design | |
| CN107636676A (en) | A kind of card reader |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| PB01 | Publication | ||
| PB01 | Publication | ||
| SE01 | Entry into force of request for substantive examination | ||
| SE01 | Entry into force of request for substantive examination | ||
| RJ01 | Rejection of invention patent application after publication |
Application publication date: 20180123 |
|
| RJ01 | Rejection of invention patent application after publication |