CN102662905A - Connecting circuit of LPC (Low Pin Count) bus and NOR FLASH BIOS chip - Google Patents
Connecting circuit of LPC (Low Pin Count) bus and NOR FLASH BIOS chip Download PDFInfo
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- CN102662905A CN102662905A CN2012101339517A CN201210133951A CN102662905A CN 102662905 A CN102662905 A CN 102662905A CN 2012101339517 A CN2012101339517 A CN 2012101339517A CN 201210133951 A CN201210133951 A CN 201210133951A CN 102662905 A CN102662905 A CN 102662905A
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Abstract
The invention discloses a connecting circuit of an LPC (Low Pin Count) bus and a NOR FLASH BIOS chip. The connecting circuit is characterized by comprising an LPC bus interface, a programmable device and an NOR FLASH BIOS chip interface, wherein the LPC bus interface is connected with the programmable device, the programmable device is connected with the NOR FLASH BIOS chip interface, the LPC bus interface is used for being connected with an X86 system, and the NOR FLASH BIOS chip interface is used for being connected with the NOR FLASH BIOS chip. The working temperature of the connecting circuit is in range of -4 DEG C to 85 DEG C.
Description
Technical field
The present invention relates to the computer starting circuit, be specially a kind of lpc bus and NOR FLASH BIOS chip CC.This circuit adopts programming device to realize being connected of lpc bus and NOR FLASH BIOS chip, is mainly used in industrial control field, the especially strict BIOS startup of industrial computer environment temperature.
Background technology
Along with information remote control high speed development, computing machine has obtained using widely in a lot of fields.Wherein particularly outstanding in business control and Industry Control, and these industries most important be stable, the reliable work of computing machine.It is stable to reach the startup BOIS that computing machine is stable, the most basic requirement of reliably working is exactly computing machine (basic input/output function).Traditional calculating machine startup BIOS function is connected on the corresponding interface BIOS chip through isa bus, spi bus and lpc bus and realizes; But start the chip (technical grade temperature :-40～+ 85 ℃) that isa bus in the BIOS chip bus, spi bus interface BIOS chip have the technical grade temperature at present; And the BIOS chip of lpc bus does not have the chip of technical grade temperature; Causing lpc bus to start the BIOS circuit can not be used on the Industry Control, so the problem that lpc bus startup BIOS chip functions can not be used on the Industry Control needs to be resolved hurrily.
Summary of the invention
Deficiency to prior art; The technical matters that quasi-solution of the present invention is determined is, a kind of lpc bus and NOR FLASH BIOS chip CC are provided, and this circuit adopts programming device to realize being connected of lpc bus and NOR FLASH BIOS chip; Have simple in structure; Reliable operation, applicability is strong, can be applicable to characteristics such as Industry Control.
The technical solution that the present invention solve the technical problem is: design a kind of lpc bus and NOR FLASH BIOS chip CC, it is characterized in that this CC comprises lpc bus interface, programming device and NOR FLASH BIOS chip interface; Said lpc bus interface is connected with programming device, and programming device is connected with NOR FLASH BIOS chip interface; Said lpc bus interface is used for being connected with the X86 system, and said NOR FLASH BIOS chip interface is used for being connected with NOR FLASH BIOS chip; The operating temperature range of CC is-40～+ 85 ℃.
Compared with prior art; Lpc bus of the present invention and NOR FLASH BIOS chip CC are owing to adopted programming device; Thereby can solve lpc bus and start the BIOS chip functions and can not be used in the problem on the Industry Control, guaranteed good compatibility, and had simple in structure; Reliable operation, characteristics such as applicability is strong.
Description of drawings
Fig. 1 is the electrical principle block diagram of lpc bus of the present invention and NOR FLASH BIOS chip CC.
Embodiment
Below in conjunction with embodiment and accompanying drawing thereof to further explain of the present invention.
The lpc bus and the NOR FLASH BIOS chip CC (referring to Fig. 1) of the present invention's design is characterized in that this CC comprises lpc bus interface 1, programming device 2 and NOR FLASH BIOS chip interface 3; Said lpc bus interface 1 is connected with programming device 2, and programming device 2 is connected with NOR FLASH BIOS chip interface 3; Said lpc bus interface 1 is used for being connected with the X86 system, and said NOR FLASH BIOS chip interface 3 is used for being connected with NOR FLASH BIOS chip; The operating temperature range of CC is-40～+ 85 ℃.
The lpc bus interface 1 of CC of the present invention is used to be connected to the X86 system, and operating temperature range is wide, can reach-40～+ 85 ℃, can satisfy the strict industrial environment of working temperature and use.
The described programming device 2 of CC of the present invention is used for the conversion of lpc bus and isa bus.Embodiment programming device 2 adopts the CPLD of technical grade programming device Altera.In lpc bus and NOR FLASH BIOS chip CC process; The information that programming device 2 is sent by the X86 system through 1 acceptance of lpc bus interface; And decode this information content; The information content of coming out decoding again is encoded into the isa bus agreement of standard, outputs to NOR FLASH BIOS chip through NOR FLASH BIOS chip interface 3; Or accept the information sent through NOR FLASH BIOS chip interface 3 by NOR FLASH BIOS chip; And decode the content of this information; The information content of coming out decoding again is encoded into the lpc bus agreement of standard, outputs to the X86 system through lpc bus interface 1.
The flow process of the information main software of programming device 2 decoding lpc bus is: when LFRAME# in the term of validity, judge beginning simultaneously or stop, when the invalid judgement of LFRAME# begins or stop to finish this operation, be 1 clock period; Judge type (I/O, memory, or the MDA) sending direction (Read or Write) that sends again, this is operating as 1 clock period; Judge and send the address, this is operating as 4 clock period or 8 clock period; Judge and send data, this is operating as 2 clock period; Judge again and send waiting status that judge and send the MDA passage, this is operating as 1 clock period; Judge again and send bus control signal; The flow process of the information main software of programming device 2 coding isa bus has not effectively at first judging IOCS16 or MEMCS16 signal; If wherein have one effectively then the data of isa bus are exactly that (SD0～SD15) is not if having effective then the data of isa bus are exactly 8bit (SD0～SD7) for 16bit; And then judge whether SMEMW or SMEMR signal be effective; If SMEMW is effective, which is interval effectively to judge SA0～SA19 address again, and then data through (SD0～SD7) or (SD0～SD15) signal output; If SMEMR is effective; Which is interval effectively to judge SA0～SA19 address again, and then data through (SD0～SD7) or (SD0～SD15) signal input, the flow process of foregoing description is whole process.CC of the present invention adopts programming device 2 to accomplish LPC changes ISA, has better flexibility.
The described NOR FLASH of CC of the present invention BIOS chip interface 3 is used for being connected with NOR FLASH BIOS chip, and NOR FLASH BIOS chip interface 3 is the isa bus interface.The operating temperature range that the BIOS chip of ISA interface is supported is wide, can reach-40～+ 85 ℃, can satisfy the strict industrial environment of working temperature and use.
The principle of work and the process of CC of the present invention are: at first; Programming device 2 is when X86 system start-up; Accept the information that the X86 system sends through lpc bus interface 1, go out the content of this information then according to the lpc bus protocol-decoding, become the output of isa bus agreement according to the content encoding that decodes information again; Be connected with NOR FLASH BIOS chip through NOR FLASH BIOS chip interface 3 at last, transmit the information that the X86 system sends to NOR FLASH BIOS chip; Perhaps programming device 2 is accepted the information that NOR FLASH BIOS chip sends and is decoded content through NOR FLASH BIOS chip interface 3, becomes the lpc bus form according to the lpc bus protocol code again, is sent to the X86 system through lpc bus interface 1; Promptly accomplish lpc bus and NOR FLASH BIOS chip CC, the software programming that needs in the design strictly observes lpc bus standard and isa bus standard, is compiled into general, standard interface protocol.
Above embodiment only is not to lpc bus of the present invention and the concrete example application of NOR FLASH BIOS chip CC, not, restriction the application claim.Every modification and non-intrinsically safe that on the application's claim technical scheme, carries out is improved, all within the application's claim protection domain.
The present invention does not address part and is applicable to prior art.
Claims (2)
1. lpc bus and NOR FLASH BIOS chip CC is characterized in that this CC comprises lpc bus interface, programming device and NOR FLASH BIOS chip interface; Said lpc bus interface is connected with programming device, and programming device is connected with NOR FLASH BIOS chip interface; Said lpc bus interface is used for being connected with the X86 system, and said NOR FLASH BIOS chip interface is used for being connected with NOR FLASH BIOS chip; The operating temperature range of CC is-40～+ 85 ℃.
2. according to said lpc bus of claim 1 and NOR FLASH BIOS chip CC, it is characterized in that said programming device adopts the CPLD of technical grade programming device Altera.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201210133951.7A CN102662905B (en) | 2012-05-03 | 2012-05-03 | Connecting circuit of LPC (Low Pin Count) bus and NOR FLASH BIOS chip |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201210133951.7A CN102662905B (en) | 2012-05-03 | 2012-05-03 | Connecting circuit of LPC (Low Pin Count) bus and NOR FLASH BIOS chip |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| CN102662905A true CN102662905A (en) | 2012-09-12 |
| CN102662905B CN102662905B (en) | 2015-02-11 |
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| Application Number | Title | Priority Date | Filing Date |
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| CN201210133951.7A Expired - Fee Related CN102662905B (en) | 2012-05-03 | 2012-05-03 | Connecting circuit of LPC (Low Pin Count) bus and NOR FLASH BIOS chip |
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Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN107621998A (en) * | 2017-09-29 | 2018-01-23 | 郑州云海信息技术有限公司 | A kind of High Availabitity FLASH system and method based on storage system |
Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN101630182A (en) * | 2009-08-19 | 2010-01-20 | 浪潮电子信息产业股份有限公司 | Computer system capable of configuring SIO |
| CN102053937A (en) * | 2009-10-30 | 2011-05-11 | 上海研祥智能科技有限公司 | Method and system for calling flash memory of SPI (serial peripheral interface) in LPC (low pin count) bus |
| CN202748783U (en) * | 2012-05-03 | 2013-02-20 | 天津市英贝特航天科技有限公司 | LPC (low pin count) bus and FLASH chip connecting circuit |
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2012
- 2012-05-03 CN CN201210133951.7A patent/CN102662905B/en not_active Expired - Fee Related
Patent Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN101630182A (en) * | 2009-08-19 | 2010-01-20 | 浪潮电子信息产业股份有限公司 | Computer system capable of configuring SIO |
| CN102053937A (en) * | 2009-10-30 | 2011-05-11 | 上海研祥智能科技有限公司 | Method and system for calling flash memory of SPI (serial peripheral interface) in LPC (low pin count) bus |
| CN202748783U (en) * | 2012-05-03 | 2013-02-20 | 天津市英贝特航天科技有限公司 | LPC (low pin count) bus and FLASH chip connecting circuit |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN107621998A (en) * | 2017-09-29 | 2018-01-23 | 郑州云海信息技术有限公司 | A kind of High Availabitity FLASH system and method based on storage system |
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| CN102662905B (en) | 2015-02-11 |
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