CN103594113B

CN103594113B - One prevents memory chip internal storage unit power-on and power-off to be written over circuit structure

Info

Publication number: CN103594113B
Application number: CN201310561969.1A
Authority: CN
Inventors: 张爱东; 金建明
Original assignee: WUXI PUYA SEMICONDUCTOR CO Ltd
Current assignee: Praran semiconductor (Shanghai) Co.,Ltd.
Priority date: 2013-11-13
Filing date: 2013-11-13
Publication date: 2016-08-17
Anticipated expiration: 2033-11-13
Also published as: CN103594113A

Abstract

The present invention relates to the safety Design of memory chip, being specially one prevents memory chip internal storage unit power-on and power-off to be written over circuit structure, its circuit structure is simple, low cost, the problem being written over when not havinging internal storage unit power-on and power-off, it includes reset circuit, reset circuit connects store control logic circuit and memory element, memory element passes through control line, address wire, data wire connects store control logic circuit, store control logic circuit connects chip interface circuit, it is characterized in that, reseting address control logic circuit is set on store control logic circuit.

Description

One prevents memory chip internal storage unit power-on and power-off to be written over circuit structure

Technical field

The present invention relates to the safety Design of memory chip, specially one prevents memory chip internal storage unit power-on and power-off to be written over circuit structure.

Background technology

The serial storage chips such as I2C, SPI, in upward and downward electric process, typically have internal reset circuit and carry out system reset, prevent chip misoperation in upward and downward electric process, it is to avoid internal storage unit is accidentally overwriten.But in actual applications, chip is when power-on and power-off, if the reset signal of inside has disappeared, but still in the case of being in under-voltage state, then the control circuit of chip internal can be operated under labile state, there is the possibility causing the memory element of chip internal to be written over.

Inside structure such as Fig. 1 that general memory chip is conventional, in upward and downward electric process, external power source reaches certain threshold value, but when being less than the minimum normal working voltage of chip, the reset signal of internal reset circuit meeting transmitting system, control logic and memory element can be reset therewith, ensure that memory element will not be accidentally operated, in foregoing circuit, when in chip, the voltage threshold of reset circuit is inclined the most in short-term for the resetting time on the low side or offer of reset unit, if external power source powers on slower, at the end of resetting, chip may also be in under-voltage, now chip internal control circuit action, but owing to voltage is relatively low, there is misoperation and possibility that storage element is written over.

In memory chip design at present, general way is minimum running voltage and the deviation of technique combining chip, as far as possible the lowest threshold voltage of reset unit is raised, guarantee that under this running voltage (namely reset circuit threshold voltage), the control part of chip can be operating normally, the most also have and wait the method that external voltage is stable resetting time by prolongation, but in the case of the startup time requirement that chip is had low voltage operating requirement or shorter, just can not improve reset threshold voltage and resetting time, there is foregoing problems.

Summary of the invention

In order to solve the problems referred to above, the invention provides one and prevent memory chip internal storage unit power-on and power-off to be written over circuit structure, its circuit structure is simple, low cost, the problem being written over when not havinging internal storage unit power-on and power-off.

Its technical scheme is such that it and includes reset circuit, described reset circuit connects store control logic circuit and memory element, described memory element connects store control logic circuit by control line, address wire, data wire, described store control logic circuit connects chip interface circuit, it is characterized in that, described store control logic circuit arranges reseting address control logic circuit.

It is further characterized by, and described memory element arranges exception address control logic circuit, and described reseting address control logic circuit connects described exception address control logic circuit.

After using the circuit of the present invention, reseting address control logic circuit is set on store control logic circuit, during power-on and power-off, reset circuit work carries out resetting and exports the exception address of memory element when operating, this address is non-effective address, for the non-existent address space of storage unit circuit, memory element is in by masked state, do not have the problem being written over, after the normal operating receiving chip structure circuit instructs, set becomes memory element normal operating address, and this address is effective address, returns to normal operating, this circuit structure is simple, low cost.

Accompanying drawing explanation

Fig. 1 is prior art construction schematic diagram；

Fig. 2 is present configuration schematic diagram；

Fig. 3 is operating process schematic diagram of the present invention.

Detailed description of the invention

As shown in Figure 2, one prevents memory chip internal storage unit power-on and power-off to be written over circuit structure, it includes reset circuit, reset circuit connects store control logic circuit and memory element, memory element connects store control logic circuit by control line, address wire, data wire, store control logic circuit connects chip interface circuit, and store control logic circuit arranges reseting address control logic circuit；Exception address control logic circuit is set in memory element, reseting address control logic circuit connects exception address control logic circuit, under the input of exception address, even if the erasable control signal of memory element exists, there will not be is to remember erasable action, better assures that the memory element of memory chip will not be written over.

Its operation principle is as described below: as shown in Figure 3, during memory chip power on operation, the magnitude of voltage of chip power Vcc is gradually increased, when Vcc exceedes reset output threshold voltage but is less than the minimum running voltage of chip, reset circuit sends reset signal, during the under-voltage work of memory chip, reseting address control logic circuit works, the exception address of output memory element, now memory element is in by masked state, erasable exercise void, until power on operation completes, it is ensured that there is not maloperation；After power on operation completes, after memory chip normally works, store control logic circuit works, and the normal address of output memory element, memory chip normally works；When memory chip has operated, under chip during electricity, when Vcc is to export threshold voltage less than resetting, reseting address control logic circuit works, the exception address of output memory element, and now memory element is in by masked state,, now there is not maloperation in erasable exercise void simultaneously.

Claims

1. one kind prevents memory chip internal storage unit power-on and power-off to be written over circuit structure, it includes reset circuit, described reset circuit connects store control logic circuit and memory element, described memory element connects store control logic circuit by control line, address wire, data wire, described store control logic circuit connects chip interface circuit, it is characterized in that, described store control logic circuit arranges reseting address control logic circuit；During memory chip power on operation, the magnitude of voltage of chip power Vcc is gradually increased, when Vcc exceedes reset output threshold voltage but is less than the minimum running voltage of chip, reset circuit sends reset signal, during the under-voltage work of memory chip, reseting address control logic circuit works, the exception address of output memory element, now memory element is in by masked state, erasable exercise void, until power on operation completes, it is ensured that there is not maloperation；After power on operation completes, after memory chip normally works, store control logic circuit works, and the normal address of output memory element, memory chip normally works；When memory chip has operated, under chip during electricity, when Vcc is to export threshold voltage less than resetting, reseting address control logic circuit works, the exception address of output memory element, and now memory element is in by masked state,, now there is not maloperation in erasable exercise void simultaneously.

One the most according to claim 1 prevents memory chip internal storage unit power-on and power-off to be written over circuit structure, it is characterized in that, arranging exception address control logic circuit in described memory element, described reseting address control logic circuit connects described exception address control logic circuit.