CN110716807A

CN110716807A - Embedded processing device

Info

Publication number: CN110716807A
Application number: CN201910936671.1A
Authority: CN
Inventors: 郑云华; 吕腾飞
Original assignee: Hefei Sijing Electronic Co Ltd
Current assignee: Hefei Sijing Electronic Co Ltd
Priority date: 2019-09-29
Filing date: 2019-09-29
Publication date: 2020-01-21

Abstract

The invention discloses an embedded processing device, which comprises a CPU core platform, a BOE bit operation engine device, a BUS, a built-in storage chip PRAM, an input/output port GPIO, a chip PBRIDGE and a chip EFM, wherein the CPU core platform, the BOE bit operation engine device and the BUS are sequentially connected, the BOE bit operation engine device monitors and decodes data of the CPU core platform, the CPU core platform is also connected with the input/output port GPIO, the BUS is also connected with the built-in storage chip PRAM, the chip PBRIDGE and the chip EFM, the built-in storage chip PRAM, the chip PBRIDGE and the chip EFM are all connected with the input/output port, and the built-in storage chip PRAM, the chip PBRIDGE and the chip EFM are also respectively externally connected with a storage chip RAM, an off-machine device and an NVM memory. The invention can effectively save CPU kernel platform and BUS BUS resources.

Description

Embedded processing device

The technical field is as follows:

the invention belongs to the technical field of embedded processing, and particularly relates to an embedded processing device.

Background art:

with the rise of internet of things in recent years, the application of embedded systems gradually goes into the visual field of people. In the development process of the application of the existing embedded single chip microcomputer, the external register and the in-chip RAM of the single chip microcomputer, namely an embedded processing device, are frequently required to be read and written. More operation instructions can be generated by utilizing the traditional C function operation or directly using address access and read-write, more CPU and bus resources are consumed, the power consumption of the single chip microcomputer is increased, and meanwhile, the operation efficiency of codes is low due to the complex execution process, so that the application cost of the embedded system program is improved invisibly, and the popularization of the application of the embedded single chip microcomputer is not facilitated.

The information disclosed in this background section is only for enhancement of understanding of the general background of the invention and should not be taken as an acknowledgement or any form of suggestion that this information forms the prior art already known to a person skilled in the art.

The invention content is as follows:

the present invention is directed to an embedded processing device, which overcomes the above-mentioned shortcomings of the prior art.

In order to achieve the purpose, the invention provides an embedded processing device which comprises a CPU core platform, a BOE bit operation engine device, a BUS BUS, a built-in storage chip PRAM, an input/output port GPIO, a chip PBRIDGE and a chip EFM, wherein the CPU core platform, the BOE bit operation engine device and the BUS BUS are sequentially connected, the BOE bit operation engine device monitors and decodes data of the CPU core platform, the CPU core platform is also connected with the input/output port GPIO, the BUS BUS is also connected with the built-in storage chip PRAM, the chip PBRIDGE and the chip EFM, the built-in storage chip PRAM, the chip PBRIDGE and the chip EFM are all connected with the input/output port GPIO, and the built-in storage chip PRAM, the chip PBRIDGE and the chip EFM are respectively connected with an external storage chip RAM, an external slave device and an external NVM memory.

An instruction encoding mode is defined in advance in the BOE bit operation engine device, AND the instruction comprises a bit AND AND, a bit OR, a bit XOR, a position 1LAS AND a bit clear LAC.

The embedded processing device is a 32-bit processing device.

The technical scheme of the invention has the following beneficial effects on one hand:

the invention adds a BOE position operation engine device between the CPU kernel platform and the BUS BUS, defines the instruction coding mode in the BOE position operation engine device in advance, controls the internal and external memories and the external equipment by the BUS after the instructions of all the CPU kernel platform are monitored and decoded by the BOE position operation engine device, and can effectively save the resources of the CPU kernel platform and the BUS BUS.

Description of the drawings:

FIG. 1 is a diagram of an embedded processing device according to the present invention;

the specific implementation mode is as follows:

the following detailed description of specific embodiments of the present invention is provided, but it should be understood that the scope of the present invention is not limited by the specific embodiments.

Throughout the specification and claims, unless explicitly stated otherwise, the word "comprise", or variations such as "comprises" or "comprising", will be understood to imply the inclusion of a stated element or component but not the exclusion of any other element or component.

As shown in fig. 1, the present invention provides an embedded processing device, which includes a CPU core platform, a BOE bit operation engine device, a BUS, a built-in storage chip PRAM, an input/output port GPIO, a chip PBRIDGE, and a chip EFM, wherein the CPU core platform, the BOE bit operation engine device, and the BUS are sequentially connected, the BOE bit operation engine device monitors and decodes data of the CPU core platform, the CPU core platform is further connected to the input/output port GPIO, the BUS is further connected to the built-in storage chip PRAM, the chip PBRIDGE, and the chip EFM, the built-in storage chip PRAM, the chip PBRIDGE, and the chip EFM are all connected to the input/output port GPIO, and the built-in storage chip PRAM, the chip PBRIDGE, and the chip EFM are further respectively connected to an external storage chip RAM, an external NVM device, and an NVM.

An instruction encoding mode is defined in advance in the BOE bit operation engine device, the instruction comprises a bit AND AND, a bit OR, a bit XOR, a position 1LAS AND a bit clear LAC, AND instruction functions in the BOE bit operation engine device are specifically defined as shown in the following table:

the embedded processing device is a 32-bit processing device.

When the CPU kernel platform reads AND writes data, the CPU kernel platform reads AND writes data of a PRAM (built-in memory chip), a PBRIDGE (chip PBRIDGE), an EFM (chip EFM), a RAM (memory chip), an auxiliary device AND an NVM (non-volatile memory) through a BUS (BUS) after completing bit AND, bit OR, bit XOR, position 1LAS AND bit clear LAC operations through a BOE bit operation engine device, so that the occupation of frequently repeated read AND write operations on CPU kernel platform resources can be reduced, AND the power consumption can be reduced AND the code operation efficiency can be improved.

The foregoing descriptions of specific exemplary embodiments of the present invention have been presented for purposes of illustration and description. It is not intended to limit the invention to the precise form disclosed, and obviously many modifications and variations are possible in light of the above teaching. The exemplary embodiments were chosen and described in order to explain certain principles of the invention and its practical application to enable one skilled in the art to make and use various exemplary embodiments of the invention and various alternatives and modifications as are suited to the particular use contemplated. It is intended that the scope of the invention be defined by the claims and their equivalents.

Claims

1. An embedded processing device, characterized by: the system comprises a CPU core platform, a BOE bit operation engine device, a BUS BUS, a built-in storage chip PRAM, an input/output port GPIO, a chip PBRIDGE and a chip EFM, wherein the CPU core platform, the BOE bit operation engine device and the BUS BUS are sequentially connected, the BOE bit operation engine device monitors and decodes data of the CPU core platform, the CPU core platform is further connected with the input/output port GPIO, the BUS BUS is further connected with the built-in storage chip PRAM, the chip PBRIDGE and the chip EFM, the built-in storage chip PRAM, the chip PBRIDGE and the chip EFM are all connected with the input/output port GPIO, and the built-in storage chip PRAM, the chip PBRIDGE and the chip EFM are further respectively connected with a storage chip RAM, an off-board device and an NVM memory.

2. An embedded processing device according to claim 1, wherein: an instruction encoding mode is defined in advance in the BOE bit operation engine device, AND the instruction comprises a bit AND AND, a bit OR, a bit XOR, a position 1LAS AND a bit clear LAC.

3. An embedded processing device according to claim 1, wherein: the embedded processing device is a 32-bit processing device.