CN210377438U

CN210377438U - Embedded processing device

Info

Publication number: CN210377438U
Application number: CN201921644326.2U
Authority: CN
Inventors: 郑云华; 吕腾飞
Original assignee: Hefei Sijing Electronic Co Ltd
Current assignee: Hefei Sijing Electronic Co Ltd
Priority date: 2019-09-29
Filing date: 2019-09-29
Publication date: 2020-04-21
Anticipated expiration: 2029-09-29

Abstract

The utility model discloses an embedded processing apparatus, including CPU kernel platform, BOE position operation engine device, BUS BUS, built-in storage chip PRAM, input/output port GPIO, chip PBRIDGE and chip EFM, CPU kernel platform, BOE position operation engine device and BUS BUS connect gradually, BOE position operation engine device monitors the data of CPU kernel platform and decodes, CPU kernel platform still is connected with input/output port GPIO, the BUS BUS still is connected with built-in storage chip PRAM, chip PBRIDGE and chip EFM, built-in storage chip PRAM, chip PBRIDGE and chip EFM all are connected with input/output port GPIO, built-in storage chip PRAM, chip PBRIDGE and chip EFM still connect outward respectively and store chip RAM, from off-board equipment, NVM memory. The utility model discloses can effectively practice thrift CPU kernel platform and BUS BUS resource.

Description

Embedded processing device

The technical field is as follows:

the utility model belongs to the technical field of embedded processing, in particular to embedded processing apparatus.

Background art:

with the rise of internet of things in recent years, the application of embedded systems gradually goes into the visual field of people. In the development process of the application of the existing embedded single chip microcomputer, the external register and the in-chip RAM of the single chip microcomputer, namely an embedded processing device, are frequently required to be read and written. More operation instructions can be generated by utilizing the traditional C function operation or directly using address access and read-write, more CPU and bus resources are consumed, the power consumption of the single chip microcomputer is increased, and meanwhile, the operation efficiency of codes is low due to the complex execution process, so that the application cost of the embedded system program is improved invisibly, and the popularization of the application of the embedded single chip microcomputer is not facilitated.

The information disclosed in this background section is only for enhancement of understanding of the general background of the invention and should not be taken as an acknowledgement or any form of suggestion that this information constitutes prior art already known to a person skilled in the art.

The utility model has the following contents:

an object of the utility model is to provide an embedded processing apparatus to overcome the defect among the above-mentioned prior art.

In order to realize the above object, the utility model provides an embedded processing apparatus, including CPU kernel platform, BOE position operation engine device, BUS BUS, built-in storage chip PRAM, input/output port GPIO, chip PBRIDGE and chip EFM, CPU kernel platform, BOE position operation engine device and BUS BUS connect gradually, BOE position operation engine device monitors the data of CPU kernel platform and decodes, CPU kernel platform still is connected with input/output port GPIO, the BUS BUS still with built-in storage chip PRAM, chip PBRIDGE and chip EFM connection, built-in storage chip PRAM, chip PBRIDGE and chip EFM all are connected with input/output port GPIO, built-in storage chip PRAM, chip PBRIDGE and chip EFM still respectively the outer memory chip RAM that links, follow external equipment, memory.

An instruction encoding mode is defined in advance in the BOE bit operation engine device, AND the instruction comprises a bit AND AND, a bit OR, a bit XOR, a position 1LAS AND a bit clear LAC.

The embedded processing device is a 32-bit processing device.

Adopt the technical scheme of the utility model the one hand following beneficial effect has:

the utility model discloses increase a BOE position operation engine device between CPU kernel platform and BUS BUS, define instruction coding mode in advance in BOE position operation engine device, the instruction of all CPU kernel platforms is decoded the back through BOE position operation engine device monitoring and is again by the interior outer memory of BUS BUS control and outer unit equipment, can effectively practice thrift CPU kernel platform and BUS BUS resource.

Description of the drawings:

fig. 1 is a schematic diagram of an embedded processing device according to the present invention;

the specific implementation mode is as follows:

the following detailed description of the embodiments of the present invention is provided, but it should be understood that the scope of the present invention is not limited by the embodiments.

Throughout the specification and claims, unless explicitly stated otherwise, the word "comprise", or variations such as "comprises" or "comprising", will be understood to imply the inclusion of a stated element or component but not the exclusion of any other element or component.

As shown in fig. 1, the utility model provides an embedded processing apparatus, including CPU kernel platform, BOE position operation engine device, BUS BUS, built-in storage chip PRAM, input/output port GPIO, chip PBRIDGE and chip EFM, CPU kernel platform, BOE position operation engine device and BUS BUS connect gradually, BOE position operation engine device monitors the data of CPU kernel platform and decodes, CPU kernel platform still is connected with input/output port GPIO, the BUS BUS still with built-in storage chip PRAM, chip PBRIDGE and chip EFM be connected, built-in storage chip PRAM, chip PBRIDGE and chip EFM all are connected with input/output port GPIO, built-in storage chip PRAM, chip PBRIDGE and chip EFM still respectively the outer memory chip RAM that links, follow external equipment, memory.

An instruction encoding mode is defined in advance in the BOE bit operation engine device, the instruction comprises a bit AND AND, a bit OR, a bit XOR, a position 1LAS AND a bit clear LAC, AND instruction functions in the BOE bit operation engine device are specifically defined as shown in the following table:

the embedded processing device is a 32-bit processing device.

When the CPU kernel platform reads AND writes data, the CPU kernel platform reads AND writes data of a PRAM (built-in memory chip), a PBRIDGE (chip PBRIDGE), an EFM (chip EFM), a RAM (memory chip), an auxiliary device AND an NVM (non-volatile memory) through a BUS (BUS) after completing bit AND, bit OR, bit XOR, position 1LAS AND bit clear LAC operations through a BOE bit operation engine device, so that the occupation of frequently repeated read AND write operations on CPU kernel platform resources can be reduced, AND the power consumption can be reduced AND the code operation efficiency can be improved.

The foregoing descriptions of specific exemplary embodiments of the present invention have been presented for purposes of illustration and description. It is not intended to limit the invention to the precise form disclosed, and obviously many modifications and variations are possible in light of the above teaching. The exemplary embodiments were chosen and described in order to explain certain principles of the invention and its practical application to enable one skilled in the art to make and use various exemplary embodiments of the invention and various alternatives and modifications as are suited to the particular use contemplated. It is intended that the scope of the invention be defined by the claims and their equivalents.

Claims

1. An embedded processing device, characterized by: the system comprises a CPU core platform, a BOE bit operation engine device, a BUS BUS, a built-in storage chip PRAM, an input/output port GPIO, a chip PBRIDGE and a chip EFM, wherein the CPU core platform, the BOE bit operation engine device and the BUS BUS are sequentially connected, the BOE bit operation engine device monitors and decodes data of the CPU core platform, the CPU core platform is further connected with the input/output port GPIO, the BUS BUS is further connected with the built-in storage chip PRAM, the chip PBRIDGE and the chip EFM, the built-in storage chip PRAM, the chip PBRIDGE and the chip EFM are all connected with the input/output port GPIO, and the built-in storage chip PRAM, the chip PBRIDGE and the chip EFM are further respectively connected with a storage chip RAM, an off-board device and an NVM memory.

2. An embedded processing device according to claim 1, wherein: an instruction encoding mode is defined in advance in the BOE bit operation engine device, AND the instruction comprises a bit AND AND, a bit OR, a bit XOR, a position 1LAS AND a bit clear LAC.

3. An embedded processing device according to claim 1, wherein: the embedded processing device is a 32-bit processing device.