CN101630182A - Computer system capable of configuring SIO - Google Patents
Computer system capable of configuring SIO Download PDFInfo
- Publication number
- CN101630182A CN101630182A CN200910017666A CN200910017666A CN101630182A CN 101630182 A CN101630182 A CN 101630182A CN 200910017666 A CN200910017666 A CN 200910017666A CN 200910017666 A CN200910017666 A CN 200910017666A CN 101630182 A CN101630182 A CN 101630182A
- Authority
- CN
- China
- Prior art keywords
- fpga
- chip
- interface
- configuration
- cpld
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 238000004891 communication Methods 0.000 claims description 3
- 238000005516 engineering process Methods 0.000 abstract description 4
- 230000005540 biological transmission Effects 0.000 description 2
- 230000009286 beneficial effect Effects 0.000 description 1
- 230000000295 complement effect Effects 0.000 description 1
- 238000010586 diagram Methods 0.000 description 1
- 230000000007 visual effect Effects 0.000 description 1
Images
Abstract
The invention discloses a computer system which is capable of configuring SIO, belonging to the technology of computer interface, comprising a computer mainboard, a South Bridge chip and a universal interface, wherein, the South Bridge chip and the universal interface are both arranged on the computer mainboard; the computer mainboard is added with an FPGA chip, an FPGA configured logic, an FPGA configured selection logic and a CPLD, wherein, the FPGA chip is an expandable SIO chip; the FPGA chip is connected with the universal interface; the FPGA chip is connected with the South Bridge chip on the computer mainboard through an LPC bus in a hooking way; the FPGA configured logic comprises a configuration file and a FLASH, wherein, the configuration file is stored in the FLASH which is connected with the CPLD; the FPGA configured selection logic is logically connected with the CPLD which is connected with the FPGA chip. The computer system which is capable of configuring SIO in the invention can ensure that the universal computer mainboard expands required interface according to requirements of practical work.
Description
Technical field
The present invention relates to a kind of Computer Interface Technology field, specifically the computer system of a kind of configurable SIO.
Background technology
On computer motherboard, SIO is SuperIO chip (a super I/O chip), generally is positioned at computer motherboard lower left or upper left side, and it provides the control and treatment function for the standard I/O interface on the mainboard.Processing capacities such as PS/2 keyboard, PS/2 mouse, serial ports COM, parallel port LPT interface that SIO is integrated, and these interfaces all are the equipment of I/O at a slow speed in the computing machine.The major function of SIO comprises to be responsible for handling from the next serial data of device transmission such as keyboard, mouse, serial line interface, they are converted into parallel data, also be responsible for simultaneously the transmission and the processing of parallel interface, floppy drive interface data, other high-speed equipment on they and the south bridge is complementary.
Yet the interface that general calculation machine mainboard tends to have in a lot of real works is not enough, and the interface that has use less than phenomenon, cause the very big wasting of resources.If at individual applications, make corresponding mainboard, production cost is increased greatly.
Summary of the invention
Technical assignment of the present invention provides a kind ofly guarantees that general calculation machine mainboard can expand the computer system of a kind of configurable SIO of required interface according to the real work needs.
Technical assignment of the present invention is realized in the following manner, comprises computer motherboard, South Bridge chip, general-purpose interface, and South Bridge chip and general-purpose interface all are arranged on the computer motherboard; On computer motherboard, increase fpga chip (FPGA is the abbreviation of Field-Programmable Gate Array, i.e. field programmable gate array), FPGA configuration logic, FPGA selection of configuration logic and CPLD (ComplexProgrammable Logic Device is a CPLD); Fpga chip is extendible SIO chip, is connected to general-purpose interface on the fpga chip, and fpga chip is hooked together by the South Bridge chip on lpc bus and the computer motherboard; The FPGA configuration logic comprises configuration file and FLASH, and configuration file stores is in FLASH, and FLASH connects CPLD; The FPGA configuration is selected then, and logic connects CPLD; CPLD connects fpga chip; Fpga chip can be configured the interface requirement that satisfies different general-purpose interfaces.
General-purpose interface comprises serial ports, parallel port, interface with floppy disk driver, mouse interface, keyboard interface.
The configurable step of fpga chip is:
(1), the general-purpose interface that needs of FPGA selection of configuration logical foundation real work, be configured model selection, describe its configuration mode by VHDL or VerilogHDL in the FPGA selection of configuration logic and after comprehensive, be downloaded among the CPLD;
(2), the configuration file stores of the various general-purpose interfaces of FPGA configuration logic in FLASH, FLASH and CPLD communicate each other;
(3), CPLD selects corresponding configuration file according to the configuration mode of describing in the FPGA selection of configuration logic from the FLASH of FPGA configuration logic, be downloaded in the fpga chip then;
(4), the configuration file of fpga chip by being downloaded into, thereby support the general-purpose interface that real work needs, fpga chip is hooked together by the South Bridge chip on lpc bus and the computer motherboard, finishes mutual communication.
The beneficial effect of the computer system of a kind of configurable SIO of the present invention is, substantially do not increasing under the situation of computer motherboard complexity, making the multi-purpose computer mainboard, visual real work situation difference, change the kind and the quantity of its interface, for real work facilitates; Reasonable in design, simple in structure, be easy to processing, easy to use; Thereby, have good value for applications.
Description of drawings
The present invention is further described below in conjunction with accompanying drawing.
Accompanying drawing 1 is the circuit structure block diagram of the computer system of a kind of configurable SIO.
Among the figure: 1, FPGA configuration logic, 2, FPGA selection of configuration logic, 3, CPLD, 4, fpga chip, 5, lpc bus, 6, South Bridge chip, 7, general-purpose interface, 8, computer motherboard.
Embodiment
Explain below the computer system work to a kind of configurable SIO of the present invention with reference to Figure of description and specific embodiment.
Embodiment:
The computer system of a kind of configurable SIO of the present invention, its structure comprise computer motherboard 8, South Bridge chip 6, general-purpose interface 7, and South Bridge chip 6 and general-purpose interface 7 all are arranged on the computer motherboard 8; On computer motherboard 8, increase fpga chip 4, FPGA configuration logic 1, FPGA selection of configuration logic 2 and CPLD3; Fpga chip 4 is extendible SIO chip, is connected to general-purpose interface 7 on the fpga chip 4, and fpga chip 4 is hooked together by the South Bridge chip 6 on lpc bus 5 and the computer motherboard 8; FPGA configuration logic 1 comprises configuration file and FLASH, and configuration file stores is in FLASH, and FLASH connects CPLD3; The FPGA configuration is selected then, and logic 2 connects CPLD3; CPLD3 connects fpga chip 4; Fpga chip 4 can be configured the interface requirement that satisfies different general-purpose interfaces 7.
General-purpose interface 7 comprises serial ports, parallel port, interface with floppy disk driver, mouse interface, keyboard interface.
The configurable step of fpga chip 4 is:
(1), FPGA selection of configuration logic 2 is according to the general-purpose interface 7 of real work needs, is configured model selection, describe its configuration mode by VHDL or VerilogHDL in the FPGA selection of configuration logic 2 and after comprehensive, be downloaded among the CPLD3;
(2), the configuration file stores of the various general-purpose interfaces of FPGA configuration logic 1 in FLASH, FLASH and CPLD3 communicate each other;
(3), CPLD3 selects corresponding configuration file according to the configuration mode of describing in the FPGA selection of configuration logic 2 from the FLASH of FPGA configuration logic 1, be downloaded into then in the fpga chip 4;
(4), the configuration file of fpga chip 4 by being downloaded into, thereby support the general-purpose interface 7 that real work needs, fpga chip 4 is hooked together by lpc bus 5 and South Bridge chip 6 on the computer motherboard 8, finishes mutual communication.
Except that the described technical characterictic of instructions, be the known technology of those skilled in the art.
Claims (3)
1, the computer system of a kind of configurable SIO, comprise computer motherboard, South Bridge chip, general-purpose interface, South Bridge chip and general-purpose interface all are arranged on the computer motherboard, it is characterized in that increasing on computer motherboard fpga chip, FPGA configuration logic, FPGA selection of configuration logic and CPLD; Fpga chip is extendible SIO chip, is connected to general-purpose interface on the fpga chip, and fpga chip is hooked together by the South Bridge chip on lpc bus and the computer motherboard; The FPGA configuration logic comprises configuration file and FLASH, and configuration file stores is in FLASH, and FLASH connects CPLD; The FPGA configuration is selected then, and logic connects CPLD; CPLD connects fpga chip; Fpga chip can be configured the interface requirement that satisfies different general-purpose interfaces.
2, the computer system of a kind of configurable SIO according to claim 1 is characterized in that general-purpose interface comprises serial ports, parallel port, interface with floppy disk driver, mouse interface, keyboard interface.
3, the computer system of a kind of configurable SIO according to claim 1 and 2 is characterized in that the configurable step of fpga chip is:
(1), the general-purpose interface that needs of FPGA selection of configuration logical foundation real work, be configured model selection, describe its configuration mode by VHDL or VerilogHDL in the FPGA selection of configuration logic and after comprehensive, be downloaded among the CPLD;
(2), the configuration file stores of the various general-purpose interfaces of FPGA configuration logic in FLASH, FLASH and CPLD communicate each other;
(3), CPLD selects corresponding configuration file according to the configuration mode of describing in the FPGA selection of configuration logic from the FLASH of FPGA configuration logic, be downloaded in the fpga chip then;
(4), the configuration file of fpga chip by being downloaded into, thereby support the general-purpose interface that real work needs, fpga chip is hooked together by the South Bridge chip on lpc bus and the computer motherboard, finishes mutual communication.
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
CN200910017666A CN101630182A (en) | 2009-08-19 | 2009-08-19 | Computer system capable of configuring SIO |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
CN200910017666A CN101630182A (en) | 2009-08-19 | 2009-08-19 | Computer system capable of configuring SIO |
Publications (1)
Publication Number | Publication Date |
---|---|
CN101630182A true CN101630182A (en) | 2010-01-20 |
Family
ID=41575313
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
CN200910017666A Pending CN101630182A (en) | 2009-08-19 | 2009-08-19 | Computer system capable of configuring SIO |
Country Status (1)
Country | Link |
---|---|
CN (1) | CN101630182A (en) |
Cited By (9)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
CN102193503A (en) * | 2010-03-15 | 2011-09-21 | 研祥智能科技股份有限公司 | Industrial control mainboard and method thereof for identifying external device |
CN102306107A (en) * | 2011-08-30 | 2012-01-04 | 四川和芯微电子股份有限公司 | Field-programmable gate array (FPGA) configuration device and configuration method |
CN102331960A (en) * | 2011-07-07 | 2012-01-25 | 曙光信息产业股份有限公司 | Interrupt debugging method for Loongson CPU-based (central processing unit-based) devices |
CN102662905A (en) * | 2012-05-03 | 2012-09-12 | 天津市英贝特航天科技有限公司 | Connecting circuit of LPC (Low Pin Count) bus and NOR FLASH BIOS chip |
CN103631750A (en) * | 2012-08-29 | 2014-03-12 | 联想(北京)有限公司 | Information processing method and electronic equipment |
CN104298936A (en) * | 2014-10-31 | 2015-01-21 | 成都朗锐芯科技发展有限公司 | FPGA encryption and parameter configuration system based on CPLD chip |
CN108197049A (en) * | 2018-01-02 | 2018-06-22 | 山东超越数控电子股份有限公司 | A kind of circuit and implementation method that function selection is realized using fpga chip |
CN112347017A (en) * | 2020-09-24 | 2021-02-09 | 天津市英贝特航天科技有限公司 | PS/2 keyboard dual-host plug-in system with LPC bus interface and switching method |
CN115586981A (en) * | 2022-11-25 | 2023-01-10 | 深圳华北工控股份有限公司 | Method, system, computer and storage medium for preventing SIO signal loss |
-
2009
- 2009-08-19 CN CN200910017666A patent/CN101630182A/en active Pending
Cited By (10)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
CN102193503A (en) * | 2010-03-15 | 2011-09-21 | 研祥智能科技股份有限公司 | Industrial control mainboard and method thereof for identifying external device |
CN102331960A (en) * | 2011-07-07 | 2012-01-25 | 曙光信息产业股份有限公司 | Interrupt debugging method for Loongson CPU-based (central processing unit-based) devices |
CN102306107A (en) * | 2011-08-30 | 2012-01-04 | 四川和芯微电子股份有限公司 | Field-programmable gate array (FPGA) configuration device and configuration method |
CN102662905A (en) * | 2012-05-03 | 2012-09-12 | 天津市英贝特航天科技有限公司 | Connecting circuit of LPC (Low Pin Count) bus and NOR FLASH BIOS chip |
CN102662905B (en) * | 2012-05-03 | 2015-02-11 | 天津市英贝特航天科技有限公司 | Connecting circuit of LPC (Low Pin Count) bus and NOR FLASH BIOS chip |
CN103631750A (en) * | 2012-08-29 | 2014-03-12 | 联想(北京)有限公司 | Information processing method and electronic equipment |
CN104298936A (en) * | 2014-10-31 | 2015-01-21 | 成都朗锐芯科技发展有限公司 | FPGA encryption and parameter configuration system based on CPLD chip |
CN108197049A (en) * | 2018-01-02 | 2018-06-22 | 山东超越数控电子股份有限公司 | A kind of circuit and implementation method that function selection is realized using fpga chip |
CN112347017A (en) * | 2020-09-24 | 2021-02-09 | 天津市英贝特航天科技有限公司 | PS/2 keyboard dual-host plug-in system with LPC bus interface and switching method |
CN115586981A (en) * | 2022-11-25 | 2023-01-10 | 深圳华北工控股份有限公司 | Method, system, computer and storage medium for preventing SIO signal loss |
Similar Documents
Publication | Publication Date | Title |
---|---|---|
CN101630182A (en) | Computer system capable of configuring SIO | |
CN203241876U (en) | Self-adaptive configuration PCIE expansion box | |
CN205959137U (en) | Big data service ware mainboard based on explain 1610 majestic treaters | |
CN103412834B (en) | The multiplexing method of a kind of single SOC and single SOC multi-operation mode | |
CN101329663A (en) | Apparatus and method for implementing pin time-sharing multiplexing | |
CN102262604B (en) | Concurrent access method, system and interface device | |
CN104933004A (en) | System and method for expanding CPU module by using SPI bus | |
CN104461660A (en) | Multi-mode dynamic loading method of heterogeneous system | |
CN202111685U (en) | Extensible switch matrix plate | |
CN102253844B (en) | Method and device for starting processor | |
CN205844977U (en) | A kind of computer based on 1500A processor of soaring controls mainboard and computer | |
CN1920806A (en) | Testing method for programmable equipment and programming method | |
CN102750214A (en) | Method for testing and programming by using device application interface | |
CN103064477B (en) | Method for designing server motherboard | |
CN204989875U (en) | Restructural test instrument based on FPGA | |
CN201444301U (en) | Device capable of unifying interfaces of multi-peripheral units to be one USB interface | |
CN202795364U (en) | Dynamically reconfigurable test measuring instrument | |
CN105718338A (en) | Information processing method and electronic device | |
CN104021103A (en) | Serial port expansion device for embedded microprocessor | |
CN105159859B (en) | Data handling system and method based on Interface Expanding | |
CN203149572U (en) | EDA comprehensive experimental platform based on FPGA chip | |
CN101594719B (en) | Offline control device | |
CN202495661U (en) | USB conversion device | |
CN103955559A (en) | Bidirectional IO multiplexing method and circuit for multi-module chip | |
CN103221922A (en) | Loading method, apparatus and system |
Legal Events
Date | Code | Title | Description |
---|---|---|---|
C06 | Publication | ||
PB01 | Publication | ||
C10 | Entry into substantive examination | ||
SE01 | Entry into force of request for substantive examination | ||
C12 | Rejection of a patent application after its publication | ||
RJ01 | Rejection of invention patent application after publication |
Open date: 20100120 |