CN101882209B - System on chip for integrating bar code decoding chip - Google Patents
System on chip for integrating bar code decoding chip Download PDFInfo
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- CN101882209B CN101882209B CN 201010189000 CN201010189000A CN101882209B CN 101882209 B CN101882209 B CN 101882209B CN 201010189000 CN201010189000 CN 201010189000 CN 201010189000 A CN201010189000 A CN 201010189000A CN 101882209 B CN101882209 B CN 101882209B
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Abstract
The invention provides a system on chip for integrating a bar code decoding chip, which is characterized by comprising a bar code decoding chip used for decoding an input bar code image and a processor system used for providing a control function for the system on chip, wherein the bar code decoding chip comprises a register group, a bar code decoding pipeline, a master control logic module and a bus interface, wherein the register group comprises a command register and a data register; the command register is used for temporarily storing commands, and the data register is used for temporarily storing data; the bar code decoding pipeline is used for processing the bar code image; the master control logic module acquires a processing command from the command register and transmits the bar code image to the bar code decoding pipeline according to the processing command for decoding; and the bar code decoding chip is electrically connected with the processor system through the bus interface. By the settings, the invention integrates the bar code decoding chip and the processor system, and thus, a processor can rapidly visit the bar code decoding chip, and thereby, the burden of research personnel is relieved. The system on chip has the advantages of convenient use, higher decoding speed and lower cost.
Description
[technical field]
The invention belongs to the barcode technology field, especially, relate to a kind of SOC (system on a chip) of integrating bar code decoding chip.
[background technology]
Barcode technology is an emerging technology that integrates coding, printing, identification, data acquisition and processing (DAP) that grows up at computer technology and Information Technology Foundation.Barcode technology is owing to its fast recognition, accurate, reliable and low cost and other advantages, be widely used in the fields such as commerce, taking care of books, storage, post and telecommunications, traffic and Industry Control, and certainly will the great effect of performance in " Internet of Things " that rise gradually used.
The bar code that is widely used at present comprises bar code and two-dimensional bar code.Bar code claims again linear bar code, is comprised of a plurality of " bars " that are arranged in parallel and " sky " unit, and bar code information is expressed by bar and empty different in width and position.Bar code is not then expressed any information in the vertical direction just in a direction (generally being horizontal direction) expressing information, so information capacity and space availability ratio are lower, and is None-identified after bar code is damaged.
Two-dimensional bar code is comprised of the chequered with black and white particular geometric figure that distributes at two-dimensional directional according to certain rules, its can be on two-dimensional directional expressing information, so information capacity and space availability ratio are higher, and have certain verifying function.Two-dimensional bar code can be divided into stack two-dimensional bar code and matrix two-dimensional barcode.The stack two-dimensional bar code is to form by the bar code of multirow cutting back is stacking, and representational stack two-dimensional bar code comprises PDF417, Code 49, Code 16K etc.Matrix two-dimensional barcode is comprised of black, the white module that is distributed in by pre-defined rule in the matrix, and representational matrix two-dimensional barcode comprises Codeone, Aztec, Data Matrix, OR code etc.
As a rule, the implementation of bar-code identification is, obtains bar code image by optical image sensor array, utilizing processor that bar code image is carried out image processes, to obtain code word, the code word of obtaining is decoded the information that is implied to obtain in the bar code according to certain encoding law.
It generally is to utilize the mode of software decode to realize that existing bar code decoding is processed, and need to write a series of software programs of realizing decoding algorithm in processor, and software program is reversed easily engineering and cracks; Since single processor can only be simultaneously for the processing of decoding of a kind of barcode standard of particular type, so decoding speed is slower, can not process the bar code of multiple format type; Moreover owing to realize that the software algorithm of bar code decoding is comparatively complicated, generally speaking the processor that therefore adopts is high-end processor (such as 32 bit processors), because high-end processor price is comparatively expensive, therefore causes cost to raise.
Generally speaking, if conventional equipment needs the integrating bar code decoding function, need to use manual routing's mode that barcode recognition equipment is linked to each other by various communication protocols with existing processor, as using I
2C(Inter-Integrated Circuit, internal integrated circuit) bus is with barcode recognition equipment and processor interconnection, and thus, the very big floor mop of meeting be researched and developed progress slowly, strengthens research staff's burden.
Therefore, above deficiency for the prior art existence, a kind of bar code decoding scheme that provides is provided badly, can carry out bar code decoding chip and processor system integrated, so that processor can be accessed rapidly bar code decoding chip, thereby alleviate research staff's burden, have more advantage easy to use, that decoding speed is faster, cost is lower.
[summary of the invention]
For cost increase, difficult wiring, the decoding process that overcomes the prior art existence is cracked easily, decoding speed waits shortcoming more slowly, the invention provides a kind of bus type decoding device based on bar code decoding chip, to overcome the problems referred to above.
The invention provides a kind of SOC (system on a chip) of integrating bar code decoding chip, comprise bar code decoding chip, be used for the bar code image of input is decoded; Processor system is used to SOC (system on a chip) that the control function is provided; Processor system comprises: bus provides data or control command transmission channel; Processor sees through bus control bar code decoding chip; Peripheral unit, be used for controlling outside link block, processor sees through total line traffic control peripheral unit, peripheral unit comprises tristate bus line controller, sdram controller, printer controller, display controller, timer, memory card controller, network controller, wireless controller, series bus controller, magnetic card/IC-card controller and interruptable controller, and outside link block comprises printer, display, magnetic card, IC-card, storage card, USB device, network interface and wireless telecommunications system; Bar code decoding chip comprises: the register group, comprise command register and data register, and command register is used for temporary order, and data register is used for temporal data, and order comprises that processing command, data comprise the bar code information of bar code image; By a plurality of bar code decoding pipeline that hardware logic is realized, a plurality of bar code decoding pipeline are carried out parallel decoding to bar code image; The master control logic module, the master control logic module is state machine, obtains processing command from command register, according to processing command bar code image is transferred to a plurality of bar code decoding pipeline and decodes, to obtain bar code information; Bus interface, bar code decoding chip obtains processing command by bus interface.
The preferred embodiment one of according to the present invention, bus interface comprises that basic input and output pin, command latch enable pin, address latch enable pin, sheet select pin, write enable pin and read enable pin.
The preferred embodiment one of according to the present invention, bar code decoding chip further comprises config memory, config memory is electrically connected with the register group, operational parameter and the data of tabling look-up when being used for the work of storage bar code decoding pipeline, bar code decoding pipeline is obtained operational parameter and the data of tabling look-up by master control logic module and register group from config memory.
The preferred embodiment one of according to the present invention, bar code decoding chip further comprises config memory, config memory is arranged on bar code decoding pipeline inside, operational parameter and the data of tabling look-up when being used for the work of storage bar code decoding pipeline.
Therefore, the SOC (system on a chip) of disclosed integrating bar code decoding chip can be connected in bar code decoding chip on the bus of ordinary processor, so that ordinary processor can be utilized and carry instruction set and access rapidly bar code decoding chip, thereby alleviate research staff's burden, have more advantage easy to use, that decoding speed is faster, cost is lower.
[description of drawings]
Fig. 1 is the circuit connection block diagram according to the SOC (system on a chip) of the integrating bar code decoding chip of first embodiment of the invention.
Fig. 2 is the circuit connection block diagram according to the SOC (system on a chip) of the integrating bar code decoding chip of second embodiment of the invention.
Fig. 3 is the circuit connection block diagram according to the bar code decoding chip of third embodiment of the invention.
Fig. 4 is the circuit connection block diagram according to the SOC (system on a chip) of the integrating bar code decoding chip of fourth embodiment of the invention.
[embodiment]
Relevant feature of the present invention and technology contents please refer to following detailed description and accompanying drawing, and accompanying drawing only provides reference and explanation, and the present invention is limited.
Fig. 1 is the circuit connection block diagram according to the SOC (system on a chip) of the integrating bar code decoding chip of first embodiment of the invention.As shown in Figure 1, the SOC (system on a chip) of this integrating bar code decoding chip comprises bus interface 109, register group 103, master control logic module 101, bar code decoding pipeline 102, optical image sensor array 105, processor system 117 and data-carrier store 104, wherein, bus interface 109, register group 103, master control logic module 101, bar code decoding pipeline 102, optical image sensor array 105 and data-carrier store 104 form bar code decoding chip 100.
In above-mentioned bar code decoding chip 100, bar code decoding pipeline 102 comprises that PDF417 bar code decoding pipeline, bar code decoded stream waterline and RSS(Reduced Space Symbology dwindle space code) bar code decoding pipeline, dissimilar bar code decoding pipeline is for the treatment of the bar code image of different barcode standards, and it utilizes hardware logic to realize.
Optical image sensor array 105 can be known CCD(Charge Coupled Device Charge Coupled Device (CCD) imageing sensor) or CMOS(Complementary Metal Oxide Semiconductor complementary metal oxide semiconductor (CMOS)) optical image sensor array, be used for obtaining bar code image, and the bar code image that obtains is transferred in the data-carrier store 104.
Data-carrier store 104 is used for the bar code image that storage is obtained by optical image sensor array 105, and it specifically can utilize RAM(random access memory random access memory) realize.
Master control logic module 101 can trigger particular event according to particular command, can be by triggering switch 107 is set or obtains bus line command from bus interface 109 and choose required state of a control of being electrically connected with master control logic module 101, as obtaining bar code image from data-carrier store 104, transmit it to bar code decoding pipeline 102 etc.Disclosed master control logic module 101 does not possess calculation function, but only triggers corresponding event according to certain condition, specifically can utilize known state machine to realize.
Bar code decoding chip 100 can be electrically connected with processor system 117 by bus interface 109, and particularly, the bus 112(that bus interface 109 can be connected in processor system 117 will describe in detail hereinafter).
Be provided with register group 103 between bus interface 109 and the master control logic module 101, register group 103 comprises a series of self-defining registers, comprise status register, data register and command register etc., status register is used for showing the duty of master control logic module 101, data register is used for temporal data, command register is used for temporary order, master control logic module 101 can be from the data register reading out data, from the order register read command, and make specific action according to particular command, wherein also can be from bus interface 109 input commands (being bus line command).Register group 103 is isolated bar code decoding pipeline 102 and external circuit with master control logic module 101, after can making things convenient for bar code decoding pipeline 102 is upgraded (as increasing the bar code decoding pipeline of processing the extended formatting type) more.
After optical image sensor array 105 obtains bar code image, this bar code image can store in the data-carrier store 104, master control logic module 101 receives in command register behind the processing command and bar code image can be transferred to the bar code decoding pipeline 102 from data-carrier store 104, carries out image pre-service, gray scale extraction, binaryzation, code word by 102 pairs of these bar code images of bar code decoding pipeline and reads, deciphers a series of bar code decoding such as processing and process operation.
In addition, bar code image also can input in the data register of register group 103 by bus interface 109, master control logic module 102 can be obtained bar code image from data register, and it is saved to data-carrier store 104, when master control logic module 102 reads processing command from the command register of register group 103, outside bar code image transmitting in the data-carrier store 104 can be processed to bar code decoding pipeline 102, bar code decoding pipeline 102 can be carried out the image pre-service to this bar code image, gray scale is extracted, binaryzation, code word reads, the a series of bar code decodings such as decoding processing are processed operation.
It should be noted that because bar code decoding pipeline 102 comprises the multiple bar code decoding pipeline for different barcode types such as PDF417 bar code decoding pipeline, bar code decoded stream waterline and RSS bar code decoding pipeline.Therefore, after obtaining bar code image, for example be bar code, this bar code image can transfer to simultaneously in above three kinds of bar code decoding pipeline and carry out parallel processing so, and is exported the correct bar code information of this bar code image by the bar code decoded stream waterline compatible with its form.A kind of bar code decoding pipeline of or other multiple formats also can be set certainly, as required.
Because incompatible with the bar code picture format, PDF417 bar code decoding pipeline and RSS bar code decoding pipeline can't be carried out respective handling after receiving this bar code image, and can't export correct bar code information.Similarly, bar code decoding pipeline 102 also can be carried out above-mentioned processing to PDF417 bar code image, RSS bar code image.Certainly, master control logic module 102 also can be processed the input bar code image according to the bar code streamline that user's selection is only controlled in a plurality of bar code streamlines.
In addition, if successively obtain three bar code image A from optical image sensor array 105 or bus interface 109, B, C is to data-carrier store 104, three bar code image A, B, respectively corresponding three kinds of dissimilar barcode standards of C: PDF417 bar code, RSS bar code and bar code, these three bar code images can provide to bar code decoding pipeline 102 from data-carrier store 104 by the precedence of obtaining so, under the same time, the PDF417 bar code decoding pipeline, bar code decoded stream waterline and RSS bar code decoding pipeline be parallel processing bar code image A at first, the result is: the PDF417 bar code decoding pipeline can handle accordingly to bar code image A, and export correct bar code information, other two bar code decoding pipeline then can't be processed bar code image A.If in the processing procedure of PDF417 bar code decoding pipeline to bar code image A, bar code decoded stream waterline and RSS bar code decoding pipeline have been confirmed to process A, then can attempt processing next bar code image B, wherein the RSS bar code decoding pipeline can be processed bar code image B, and exports correct bar code information.If in the process that PDF417 bar code decoding pipeline and RSS bar code decoding pipeline are processed bar code image A, B respectively, bar code decoded stream waterline has been confirmed to process bar code image B, then can continue to attempt next bar code image C is processed, and because form is corresponding, bar code decoded stream waterline can be processed C, and exports correct bar code information.
Just can process second bar code image owing to waiting for that first bar code image finished dealing with, and need not wait for that second bar code image finished dealing with and just can process the 3rd bar code and open image that therefore above parallel bar code image processing mode can greatly improve the speed of processing dissimilar bar code images.
The bar code information of bar code decoding pipeline 102 outputs can be stored to data-carrier store 104 by master control logic module 101, and is being stored to data register from data-carrier store 104 when needs are exported.Certainly, the bar code information of bar code decoding pipeline 102 outputs can directly be stored to data register by master control logic module 101.The bar code information that is stored to data register can transfer to bus 112 through bus interface 109.
Working method that it should be noted that above bar code decoding pipeline 102 is applicable to arbitrary embodiment of the present invention.
In the above embodiment of the present invention, because the bar code decoding pipeline 102 of having used the parallel type bar code decoding to process, so the comparable known software decode speed of decoding speed wants fast.
Fig. 2 is the circuit connection block diagram according to the SOC (system on a chip) of the integrating bar code decoding chip of second embodiment of the invention.But the processor system 117 of introducing in the tristate bus line controller 301 that illustrates among Fig. 2, sdram controller 302, printer controller 303, display controller 304, timer 311, memory card controller 312, ethernet controller 313, wireless controller 314, series bus controller 305, magnetic card/IC-card controller 306, interruptable controller 308, bus 112 and processor 310 composition diagrams 1.Wherein the tristate bus line controller 301, sdram controller 302, printer controller 303, display controller 304, timer 311, memory card controller 312, network controller 313, wireless controller 314, series bus controller 305, magnetic card/IC-card controller 306, interruptable controller 308 is peripheral unit, peripheral unit can be controlled outside link block, such as printer, display, magnetic card, IC-card, storage card, USB device, network interface, wireless telecommunications system etc., bus 112 can provide data or control command transmission channel, and processor 310 can be by bus 112 control peripheral units.Storage card comprises CF(Compact Flash) card, mmc card (MultiMedia Card), SD card (Secure Digital), Micro SD card, Min SD card and SM(Smart Media) card etc.Network interface comprises Ethernet interface, lan interfaces, wireless network interface etc.Wireless telecommunications system comprises GSM, CDMA, WIFI, bluetooth equipment etc.Serial bus interface can be connected in UART(Universal Asynchronous Receiver/Transmitter, the Universal Asynchronous Receiver ﹠ dispensing device), USB(Universal Serial BUS, USB (universal serial bus)), SPI(Serial Peripheral interface, Serial Peripheral Interface), I
2C(Inter-Integrated Circuit, internal integrated circuit) the one in the universal serial bus such as.The present invention does not do concrete the restriction to it.
Processor 310 sees through bus 112 access tristate bus line controllers 301, sdram controller 302, printer controller 303, display controller 304, timer 311, memory card controller 312, network controller 313, wireless controller 314, series bus controller 305, magnetic card/IC-card controller 306, interruptable controller 308 peripheral units such as grade, wherein, tristate bus line controller 301, sdram controller, printer controller 303, display controller 304, timer 311, memory card controller 312, network controller 313, wireless controller 314, series bus controller 305, magnetic card/IC-card controller 306, interruptable controller 308 is as the peripheral unit of processor 310, be mapped to a fixing memory address, this memory address that can be conducted interviews by the instruction set that processor 310 carries is with the control peripheral unit.
It should be noted that, tristate bus line controller 301, sdram controller 302, printer controller 303, display controller 304, timer 311, memory card controller 312, network controller 313, wireless controller 314, series bus controller 305, magnetic card/IC-card controller 306, interruptable controller 308 are not necessary by processor system 117, those skilled in the art can select or make corresponding additions and deletions according to actual needs, and the present invention does not limit this.
More show bar code decoding chip 100 among Fig. 2, wherein this bar code decoding chip 100 is introduced in Fig. 1 in detail, bar code decoding chip 100 can be connected on the bus 112 of processor system 117 by bus interface 109, therefore bar code decoding chip 100 also can be mapped to a fixing memory address, accesses this memory address with control bar code decoding chip 100 by the instruction set that processor 310 carries.
Processor system 117 is mainly used in providing certain control function for SOC (system on a chip), for example by printer controller 303 control printers, utilize series bus controller 305 and other processor communications, respond this look-at-me and make specific action thereby obtain look-at-me from interruptable controller 308, and utilize display controller 304 control outernal display units etc.In addition, the processor system of present embodiment can also provide the part auxiliary operation for the bar code decoding process.
In a preferred embodiment, bus interface 109 bus interface 309 that disclose among Fig. 1 comprise following pin: I/O
0-I/O
7, CLE, ALE, CS, WE, RE, wherein the function of each pin such as following table 1.1 introduction:
Table 1.1
Generally speaking, when pin ALE was effective, bus interface 109 was from pin I/O
0～I/O
7Receive address date, when pin CLE was effective, bus interface 109 was from pin I/O
0～I/O
7Receive order, and will order and keep in to the command register of register group 103, when the WE pin was effective, outside bar code image can be from the pin I/O of bus interface 109
0-I/O
7The data register of input register group 103, master control logic module 101 can be obtained outside bar code image from the data register of register group 103 according to mentioned order, and transfers to data-carrier store 104.In addition, when master control logic module 101 reads processing command from the command register of register group 103, the bar code image in the data-carrier store 104 can be transferred to bar code decoding pipeline 102 processing of decoding.
Bus interface 109 of the present invention can with bus 112 compatibilities of processor system 117, be very easy to development process.
The SOC (system on a chip) of the integrating bar code decoding chip that present embodiment discloses is integrated with processor system and bar code decoding chip height by bus interface, so the research staff need not carry out the manual routing, has improved efficiency of research and development, and has greatly dwindled equipment volume.In addition, the SOC (system on a chip) of this integrating bar code decoding chip has been owing to adopted bar code decoding to process special-purpose hardware decoded stream waterline, thus its to compare decoding speed faster with known software decode; In addition, the bar code decoding pipeline of pure hardware configuration can not be reversed engineering and crack, and security performance is very high, and decoding speed is faster, cost is lower, and can process the function of the bar code image of multiple different coding type.
Fig. 3 is the circuit connection block diagram according to the bar code decoding chip of third embodiment of the invention.Itself and embodiment shown in Figure 1 are basic identical, comprise equally bus interface 211, register group 203, master control logic module 201, bar code decoding pipeline 202, data-carrier store 204 and optical image sensor array 205.Improvement is, has adopted exposure control module 208 among the embodiment of Fig. 2, and exposure control module 208 is passed through I
2C(Inter-Integrated Circuit, internal integrated circuit) duty of total line traffic control optical image sensor array 205.
In addition, exposure control module 208 can be placed processing command in the command register of register group 203 according to the duty of optical image sensor array 205, master control logic module 201 is obtained processing command from the command register of register group 203 after, 202 pairs of optical image sensor array 205 bar code images that obtain of control bar code decoding pipeline are decoded.
In addition, master control logic module 201 can be obtained bus line command by bus interface 211, and it is stored in the command register of register group 203, and exposure control module 208 can be obtained this bus line command, thus the duty of control optical image sensor array 205.
Fig. 3 further shows scanning switch 206, can send scan command to master control logic module 201 by starting scanning switch 206, master control logic module 201 is temporary to command register with scan command, and startup optical image sensor array 205 was taken after exposure control module 208 was obtained scan command from command register.
The resolution of optical image sensor array 205 can select 752X 480 or 640X 480(the present invention is not construed as limiting this), it can or arrange switch 207 by bus line command and select different resolution, for example, by being set, switch 207 transmissions order is set to master control logic module 101, it is temporary to command register that master control logic module 201 will arrange order, and exposure control module 208 is obtained from command register and order is set so that the resolution of optical image sensor array 205 to be set.It should be noted that, switch 207 is set except the triggering master control logic module 201 described in having the first embodiment with bar code image from data-carrier store 204 is transferred to the effect of bar code decoding pipeline 202, also have the function of the resolution that optical image sensor array 205 is set.
It should be noted that switch 207 to be set and scanning switch 206 can arrange according to actual needs, can omit in case of necessity.
In addition, config memory 212 is electrically connected with register group 203, operational parameter when being used for 202 work of storage bar code decoding pipeline and the data of tabling look-up (such as the required code table of decoding computing), bar code decoding pipeline 202 can be obtained above data from config memory 212 by master control logic module 201 and register group 203, it must guarantee can obliterated data in the situation of outage, available known EEPROM(Electrically Erasable Programmable Read-Only Memory, EEPROM (Electrically Erasable Programmable Read Only Memo)) realizes, in some cases, config memory 212 can be set directly in the bar code decoding pipeline 202.
It should be noted that config memory 212 can be arranged among arbitrary embodiment of the present invention.
Fig. 4 is the circuit connection block diagram according to the SOC (system on a chip) of the integrating bar code decoding chip of fourth embodiment of the invention.The difference of present embodiment and the first embodiment shown in Figure 1 is, the optical sensing array is not set in the bar code decoding chip of present embodiment.Bar code image is inputted from bus interface by processor system.
More than with reference to the accompanying drawings of various preferred embodiments of the present invention, but only otherwise deviate from the spirit and scope of the invention, those skilled in the art can carry out modifications and changes on the various forms to it, all belongs to protection scope of the present invention.
Claims (4)
1. the SOC (system on a chip) of an integrating bar code decoding chip is characterized in that, comprising:
Bar code decoding chip is used for the bar code image of input is decoded;
Processor system is used to described SOC (system on a chip) that the control function is provided;
Described processor system comprises:
Bus provides data or control command transmission channel;
Processor sees through the described bar code decoding chip of described total line traffic control;
Peripheral unit, be used for controlling outside link block, described processor sees through the described peripheral unit of described total line traffic control, described peripheral unit comprises tristate bus line controller, sdram controller, printer controller, display controller, timer, memory card controller, network controller, wireless controller, series bus controller, magnetic card/IC-card controller and interruptable controller, and described outside link block comprises printer, display, magnetic card, IC-card, storage card, USB device, network interface and wireless telecommunications system;
Described bar code decoding chip comprises:
The register group comprises command register and data register, and described command register is used for temporary order, and described data register is used for temporal data, and described order comprises processing command, and described data comprise the bar code information of described bar code image;
By a plurality of bar code decoding pipeline that hardware logic is realized, described a plurality of bar code decoding pipeline are carried out parallel decoding to described bar code image;
The master control logic module, described master control logic module is state machine, obtains described processing command from described command register, according to described processing command described bar code image is transferred to described a plurality of bar code decoding pipeline and decodes, to obtain described bar code information;
Bus interface, described bar code decoding chip obtains described processing command by described bus interface.
2. the SOC (system on a chip) of integrating bar code decoding chip according to claim 1, it is characterized in that described bus interface comprises that basic input and output pin, command latch enable pin, address latch enable pin, sheet select pin, write enable pin and read enable pin.
3. the SOC (system on a chip) of integrating bar code decoding chip according to claim 1, it is characterized in that, described bar code decoding chip further comprises config memory, described config memory is electrically connected with described register group, operational parameter and the data of tabling look-up when being used for storing described bar code decoding pipeline work, described bar code decoding pipeline is obtained described operational parameter and the described data of tabling look-up by described master control logic module and described register group from described config memory.
4. the SOC (system on a chip) of integrating bar code decoding chip according to claim 1, it is characterized in that, described bar code decoding chip further comprises config memory, it is inner that described config memory is arranged on described bar code decoding pipeline, operational parameter and the data of tabling look-up when being used for storing described bar code decoding pipeline work.
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Address after: 350015 No. 1 Rujiangxi Road, Mawei District, Fuzhou City, Fujian Province Patentee after: NEWLAND DIGITAL TECHNOLOGY Co.,Ltd. Address before: 350015 New Continental Science Park No. 1 Rujiangxi Road, Mawei District, Fuzhou City, Fujian Province Patentee before: Fujian Newland Computer Co.,Ltd. |
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Granted publication date: 20130123 |
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| CF01 | Termination of patent right due to non-payment of annual fee |