CN102789435B - Serial storage and method and system for dividing storage regions - Google Patents
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Abstract
The embodiment of the invention discloses a serial storage and a method and a system for dividing storage regions. The serial storage is subjected to division of the storage regions by configuring switching control pins; and the switching of the storage regions is implemented by the switching control pins. The method disclosed by the embodiment of the invention comprises the following steps of: configuring m switching control pins to the serial storage and dividing the serial storage into k storage regions by the m switching control pins; and implementing the switching between the k storage regions by the switching control pins, wherein m is a positive integer greater than or equal to 1, k is a positive integer which is greater than or equal to 2 and less than or equal to 2m.
Description
Technical field
The present invention relates to communication technical field, be specifically related to serial storage and a kind of method and system dividing storage area.
Background technology
In start up system, microcontroller does not have enough large internal storage usually, at this moment must use external memory storage.And generally, less start up system uses with internal storage but do not have the microcontroller of outer address bus, so select external series storer.Serial storage is a kind of employing Serial Peripheral Interface (Serial Peripheral Interface, be called for short SPI) bus or IIC(Inter-Integrated Circuit) interface bus or System Management Bus (System ManagementBus, be called for short SMBus) memory device, wherein, comprise serial flash (Flash) or serial EEPROM (Electrically Erasable Programmable Read Only Memo) (Electrically Erasable Programmable Read-OnlyMemory is called for short EEPROM) etc.
Such as serial flash Flash is widely used in basic input/output (Basic Input Output System the is called for short BIOS) start-up routine storing processor in start up system.Particularly, BIOS start-up routine being stored in a slice serial flash Flash, reading BIOS start-up routine by accessing this serial flash Flash.If BIOS start-up routine cannot be read from this serial flash Flash, system will be caused normally to start.Therefore, normally store BIOS start-up routine with active and standby two panels serial flash Flash at present, if when cannot start from main serial flash Flash reading BIOS start-up routine, just by switching the mode of serial line interface, being switched to standby serial flash Flash reading BIOS start-up routine and starting.But using two panels serial flash Flash back-up BIOS start-up routine, cost is higher.
Summary of the invention
For above-mentioned defect, embodiments provide the method and system of a kind of serial storage and division storage area, can realize using a slice serial flash Flash back-up BIOS start-up routine, ensure successful start up system.
A kind of serial storage, comprising:
M switch control pin 110, wherein, described m be more than or equal to 1 positive integer;
Described m switches control pin 110 and serial storage is divided into k storage area, and realizes the switching between a described k storage area by described switching control pin 110, and wherein, described k for being more than or equal to 2, and is less than or equal to 2
mpositive integer.
Divide a system for storage area, comprise outside commutation circuit 310 and serial storage 320;
Described serial storage 320 comprise m switch control pin 110, described m switch control pin 110 serial storage is divided into k storage area, wherein, described m be more than or equal to 1 positive integer, described k for being more than or equal to 2, and is less than or equal to 2
mpositive integer;
Described outside commutation circuit 310 controls pin 110 with described serial storage 320 by the switching configured and is electrically connected; Described outside commutation circuit 310 sends switch-over control signal for controlling pin 110 to the switching of described serial storage 320;
Described serial storage 320 controls by switching the described switch-over control signal that pin 110 receives the transmission of outside commutation circuit 310.
Divide a method for storage area, comprising:
Control pin for serial storage configuration m switches, described m switches control pin and described serial storage is divided into k storage area;
The switching between a described k storage area is realized by described switching control pin;
Wherein, described m be more than or equal to 1 positive integer, described k for being more than or equal to 2, and is less than or equal to 2
mpositive integer.
As can be seen from technique scheme, the embodiment of the present invention has the following advantages:
In the embodiment of the present invention, serial storage is configured with m switching and controls pin, and described switching controls pin can be divided into 2 ~ 2 by serial storage
mindividual storage area, and by described switching control pin can realize this 2 ~ 2
mswitch between individual storage area.
Accompanying drawing explanation
In order to be illustrated more clearly in the technical scheme of the embodiment of the present invention, be briefly described to the accompanying drawing used required in the embodiment of the present invention below, apparently, accompanying drawing in the following describes is only some embodiments of the present invention, for those of ordinary skill in the art, under the prerequisite not paying creative work, other accompanying drawing can also be obtained according to these accompanying drawings.
A kind of Serial Storage Architecture schematic diagram that Fig. 1 provides for the embodiment of the present invention;
Another structural representation of a kind of serial storage that Fig. 2 provides for the embodiment of the present invention;
A kind of system architecture schematic diagram dividing storage area that Fig. 3 provides for the embodiment of the present invention;
A kind of start up system structural representation that Fig. 4 provides for the embodiment of the present invention;
Another structural representation of a kind of start up system that Fig. 5 provides for the embodiment of the present invention;
A kind of method flow diagram dividing storage area that Fig. 6 provides for the embodiment of the present invention;
A kind of another process flow diagram of method dividing storage area that Fig. 7 provides for the embodiment of the present invention.
Embodiment
Below in conjunction with the accompanying drawing of the embodiment of the present invention, be clearly and completely described the technical scheme in the embodiment of the present invention, obviously, described embodiment is only the present invention's part embodiment, instead of whole embodiments.Based on the embodiment in the present invention, those of ordinary skill in the art, not making the every other embodiment obtained under creative work prerequisite, belong to the scope of protection of the invention.
Embodiments provide a kind of serial storage, switched by configuration and control pin division storage area, simple and convenient; The embodiment of the present invention additionally provides a kind of method and system dividing storage area, switches control pin divide storage area and realize the switching between storage area by this switching control pin by configuration.Serial storage in the embodiment of the present invention comprises serial flash Flash, EEPROM (Electrically Erasable Programmable Read Only Memo) EEPROM etc., and the present invention is not construed as limiting this.Additionally, the interface of the serial storage in the embodiment of the present invention, comprise SPI interface, IIC interface and SMBus etc., the present invention is also not construed as limiting this.And be described for serial storage storage BIOS start-up routine in the embodiment of the present invention, be not limited to be applied in the scene storing BIOS start-up routine, also can be used for the scene storing other data or program, the present invention is not construed as limiting this.
A kind of Serial Storage Architecture schematic diagram that Fig. 1 provides for the embodiment of the present invention, as shown in Figure 1, this serial storage comprises:
M switch control pin 110, wherein, described m be more than or equal to 1 positive integer;
Described m switches control pin 110 and serial storage is divided into k storage area, and realizes the switching between a described k storage area by described switching control pin 110, and wherein, described k for being more than or equal to 2, and is less than or equal to 2
mpositive integer.
Wherein, this serial storage comprises m and switches control pin 110, serial storage can be divided into 2 ~ 2
mindividual storage area, can control the access to these storage areas by described m switching control pin 110.
Additionally, another structural representation of a kind of serial storage that Fig. 2 provides for the embodiment of the present invention, as shown in Figure 2, described serial storage inside comprises segment data line 240 in interface accessing controller 210, bus switch 220, inner total data line 230 and k bar;
Described interface accessing controller 210 is connected on described bus switch 220 by described inner total data line 230, described bus switch 220 is connected on the n-th storage area by n-th interior segment data line, and control pin 110 be connected with described switching, wherein, described n for being more than or equal to 1, and is less than or equal to the positive integer of k.
Wherein, this serial storage inside comprises interface accessing controller 210 and bus switch 220, interface accessing controller 210 is connected with bus switch 220 by inner total data line 230, and bus switch 220 is connected on storage area respectively by interior segment data line 240, such as pass through segment data line in the 1st to be connected with the 1st storage area, be connected with the 2nd storage area by segment data line in the 2nd, be connected with a kth storage area by segment data line in kth.Switch control pin 110 to be sent to after on bus switch 220, under bus switch 220 controls, inner total data line 230 is connected with segment data line 240 in the storage area of coupling, be communicated with interface accessing controller 210, achieve the switching of storage area.
A kind of system architecture schematic diagram dividing storage area that Fig. 3 provides for the embodiment of the present invention, as shown in Figure 3, this system comprises: outside commutation circuit 310 and the serial storage as shown in Fig. 1 or Fig. 2 of the present invention 320;
Described serial storage 320 comprise m switch control pin 110, described m switch control pin 110 serial storage is divided into k storage area, wherein, described m be more than or equal to 1 positive integer, described k for being more than or equal to 2, and is less than or equal to 2
mpositive integer;
Described outside commutation circuit 310 controls pin 110 with described serial storage 320 by the switching configured and is electrically connected; Described outside commutation circuit 310 sends switch-over control signal for controlling pin 110 to the switching of described serial storage 320;
Described serial storage 320 controls by switching the described switch-over control signal that pin 110 receives the transmission of outside commutation circuit 310.
Wherein, outside commutation circuit 310 controls pin 110 by the switching that serial storage 320 configures and connects, and outside commutation circuit 310 can send switch-over control signal by controlling pin 110 to switching, thus realizes the switching of storage area.And switch-over control signal can be high level or low level, or logical address.
Exemplary, the present invention's serial storage is as shown in Figure 1 or 2 applied in start up system, as shown in Figure 4, for a kind of start up system structural representation that the embodiment of the present invention provides, described system comprises: the outside commutation circuit 310 as shown in Fig. 3 of the present invention, the serial storage 320 as shown in Fig. 3 of the present invention, processor 410 and watchdog circuit 420;
Described serial storage 320 comprises m and switches control pin 110, described m switches control pin 110 and serial storage is divided into k storage area, each storage area all stores BIOS start-up routine, wherein, described m be more than or equal to 1 positive integer, described k for being more than or equal to 2, and is less than or equal to 2
mpositive integer;
Described processor 410 is connected on serial storage 320, and when system reset, for receiving the reset signal sent from watchdog circuit 420, then the storage area of reference string line storage 320 reads BIOS start-up routine start up system; Described outside commutation circuit 310 sends switch-over control signal for controlling pin 110 to the switching of described serial storage 320.Concrete, described outside commutation circuit 310 is when system reset, receive the reset signal sent from watchdog circuit 420, and to the effective edge counting in reset signal, count value is decoded into binary switch-over control signal and outputs on the switching control pin 110 of serial storage 320;
Described watchdog circuit 420, when system reset, sends reset signal to described processor 410 and outside commutation circuit 310.
Wherein, described processor 410 can be network processing unit (Network Processor is called for short NP) or central processor unit (Central Processing Unit is called for short CPU).
It should be noted that, processor 410 can be connected with serial storage 320 by SPI or IIC or SMBus, serial storage 320 controls pin 110 by the switching of configuration and is connected with outside commutation circuit 310, in each storage area of serial storage 320, back up identical BIOS start-up routine.When described start up system electrifying startup or after starting failure or power-down rebooting, watchdog circuit 420 is by identical reset signal input processor 410 and outside commutation circuit 310 respectively.Suppose that with reset signal rising edge be effective edge, there is counter outside commutation circuit 310 inside, after outside commutation circuit 310 receives reset signal, counter in outside commutation circuit 310 counts rising edge, and the switching outputting to serial storage 320 after count value is decoded into binary switch-over control signal controls on pin 110, and serial storage 320 is according to switch-over control signal, be communicated with the storage area that this switch-over control signal matches with processor 410, thus realize reading the startup of BIOS start-up routine from this storage area.
Below by the start up system basis shown in above-mentioned Fig. 4, introduce the switching control pin 110 that serial flash Flash is configured with varying number further, mark off the situation of the storage area of varying number.
Preferably, as shown in Figure 5, for another structural representation of a kind of start up system that the embodiment of the present invention provides, described serial flash Flash is configured with 1 and switches control pin SW0, described serial flash Flash is divided into 2 storage area A and B, and outside commutation circuit is connected with described serial flash Flash by SW0.
Such as, all placing two same BIOS start-up routines in A and B, is effective edge with the rising edge of reset signal.After reset, reset signal is inputted CPU and outside commutation circuit by watchdog circuit.Outside commutation circuit is after receiving reset signal, the rising edge of reset signal is counted, finally count value is decoded into switch-over control signal, output to SW0, SW0 is admitted on the bus switch of serial flash Flash inside, the switch-over control signal of bus switch received by SW0, as shown in table 1 or table 2, segment data line in the storage area matched with switch-over control signal is connected with inner total data line, thus be communicated with interface accessing controller, and then connecting upper processor, processor can access A or B.
For example, initiating switchup or after starting failure or power down system reset, reset for the 1st time, the count value of outside commutation circuit is 0, and is decoded into Binary Zero, and wherein, 0 can represent low level or presentation logic address.When representing low level, by low level output to SW0, SW0 is sent on the bus switch of serial flash Flash inside, bus switch is according to the low level signal on SW0, by connect A the 1st in segment data line be connected on inner total data line, thus CPU can access A, read the BIOS start-up routine start up system in A; When presentation logic address, the value 0 of logical address the 0th bit is exported to SW0, SW0 is sent on the bus switch of serial flash Flash inside, the bit value that bus switch reads on SW0 is reduced into binary logic address 0, according to the logical address after reduction, segment data line in the 1st of the A matched with this logical address the is connected on inner total data line, thus CPU can access A, read the BIOS start-up routine start up system in A.
When resetting for the 2nd time, watchdog circuit sends repositioning information notice CPU and outside commutation circuit, and the counter of outside commutation circuit counts rising edge, and calculated value is 1 and is decoded into binary one, and wherein, 1 represents high level or logical address.When representing high level, by high level output to SW0, SW0 is sent on the bus switch of serial flash Flash inside, bus switch is according to the high level signal on SW0, by connect B the 2nd in segment data line be connected on inner total data line, thus CPU can access B, read the BIOS start-up routine start up system in B; When presentation logic address, the value 1 of logical address the 0th bit is exported to SW0, SW0 is sent on the bus switch of serial flash Flash inside, the bit value that bus switch reads on SW0 is reduced into binary logic address 1, by with reduction after logical address match the 2nd of B in segment data line be connected on inner total data line, thus CPU can access B, read the BIOS start-up routine start up system in B.If again resetted, counter comes back to 0, is switched to A by SW0, by that analogy, repeatedly performs.
Table 1
| Level signal (0 is low level, and 1 is high level) | Access region |
| SW0=0 | A |
| SW0=1 | B |
Table 2
| Logical address [0,1 is bit value] | Access region |
| SW0=0 | A |
| SW0=1 | B |
Preferably, serial flash Flash is configured with 2 and switches control pin SW0 and SW1, serial flash Flash can be divided into 2,3 or 4 storage areas.When configuration 2 switching control pin is divided into 4 storage areas A, B, C, D, such as, shown in table 3:
Table 3
| Logical address [0,1 is bit value] | Access region |
| SW1=0，SW1=0 | A |
| SW1=0，SW0=1 | B |
| SW1=1，SW0=0 | C |
| SW1=1，SW0=1 | D |
When resetting for the 1st time, the counter of outside commutation circuit is 0, be decoded as binary switch-over control signal 00, according to order from low to high, the value 0 of the 0th bit of switch-over control signal is exported to SW0, and the value 0 of the 1st bit of switch-over control signal exports to SW1, SW1 and SW2 is sent to the bus switch of serial flash Flash inside, the bit value that bus switch reads on SW0 and SW1 is reduced into binary logic address 00, according to reduction after logical address by connect A the 1st in segment data line be communicated with inner total data line, be switched to storage area A.When resetting for the 2nd time, the count value of outside commutation circuit is 1, be decoded as binary switch-over control signal 01, according to order from low to high, the value 1 of the 0th bit of switch-over control signal is exported to SW0, the value 0 of the 1st bit exports to SW1, SW0 and SW1 is sent in the bus switch of serial flash Flash inside, the bit value that bus switch reads on SW0 and SW1 is reduced into binary logic address 01, according to reduction after bus switch by connect B the 2nd in segment data line be communicated with inner total data line, be switched to storage area B, by that analogy, after receiving the 4th reset signal, then counter is 4, be decoded as binary switch-over control signal 11, the value 1 of the 0th bit is exported to SW0, the value 1 of the 1st bit is exported to SW1, SW0 and SW1 is sent in the bus switch of serial flash Flash inside, bus switch by connect D the 4th in segment data line be communicated with inner total data line, be switched to storage area D.After receiving the 5th reset signal, counter returns to 0, is decoded as binary switch-over control signal 00, is again switched to storage area A.
As shown in table 4, configure 2 switching control pins and serial flash Flash is divided into 3 storage areas A, B and C, switch and control pin SW0 control A and B, SW1 control C.
After receiving first time reset signal, outside commutation circuit counts reset signal rising edge, count value is decoded into binary switch-over control signal 00, according to order from low to high, the value 0 of the 0th bit of switch-over control signal is exported to SW0, the value 1 of the 1st bit exports to SW1, SW1 and SW2 is sent to the bus switch of serial flash Flash inside, the bit value that bus switch reads on SW0 and SW1 is reduced into binary logic address 00, according to the logical address after reduction, by connect A the 1st in segment data line be communicated with inner total data line, be switched to storage area A.Receive the 2nd reset signal, the count value of outside commutation circuit is 1, be decoded as binary switch-over control signal 01, the value 1 of the 0th bit of switch-over control signal is exported to SW0, the value 0 of the 1st bit exports to SW1, SW0 and SW1 is sent in the bus switch of serial flash Flash inside, the bit value that bus switch reads on SW0 and SW1 is reduced into binary logic address 01, according to the logical address after reduction, by connect B the 2nd in segment data line be communicated with inner total data line, be switched to storage area B.Receive the 3rd reset signal, count value is 3, be decoded into binary switch-over control signal 10, the value 0 of the 0th bit is exported to SW0, the value 1 of the 1st bit exports to SW1, SW0 and SW1 is sent in the bus switch of serial flash Flash inside, and the bit value that bus switch reads on SW0 and SW1 is reduced into binary logic address 10, according to reduction after logical address bus switch by connect C the 3rd in segment data line be communicated with inner total data line, be switched to storage area C; Receive the 4th reset signal, count value gets back to 0, exports binary switch-over control signal 00, is switched to storage area A, by that analogy, repeatedly perform.
Table 4
| Logical address [0,1 is bit value] | Access region |
| SW1=0，SW0=0 | A |
| SW1=0，SW0=1 | B |
| SW1=1，SW0=0 | C |
The embodiment of the present invention additionally provides a kind of method dividing storage area, and as shown in Figure 6, the method comprises:
610, be serial storage configuration m switch control pin, described m switching control pin described serial storage is divided into k storage area, wherein, described m be more than or equal to 1 positive integer, described k for being more than or equal to 2, and is less than or equal to 2
mpositive integer;
Wherein, by switching control pin to serial storage configuration, serial storage is divided storage area, if when the switching control number of pins of configuration is m, 2 storage areas at least can be divided into, can be divided into 2 at the most
mindividual storage area, so the storage area of actual division can be k, and 2≤k≤2
m, m gets the positive integer being more than or equal to 1.
620, the switching between a described k storage area is realized by described switching control pin.
Wherein, after serial storage being divided into k storage area, can switch between this k storage area by switching control pin.
In the embodiment of the present invention, by being that serial storage configuration m switches and controls pin, thus divide the storage area of serial storage, and realize the switching between a described k storage area by switching control pin.
The embodiment of the present invention is described in further detail below, a kind of another process flow diagram of method dividing storage area that Fig. 7 provides for the embodiment of the present invention.As shown in Figure 7, described method comprises:
710, be serial flash Flash configure m switch control pin, described m switching control pin described serial storage is divided into k storage area, wherein, described m be more than or equal to 1 positive integer, described k for being more than or equal to 2, and is less than or equal to 2
mpositive integer;
Wherein, when producing serial flash Flash, being configured with outside other pins often needed, returning serial flash Flash configuration m switching and controlling pin, controlling pin by this switching and serial flash Flash can be divided into 2 ~ 2
mindividual storage area, so that when user uses, starts the BIOS start-up routine of CPU as required, completes and successfully start from a slice serial flash Flash in different storage zone backup.
720, control by described switching the switch-over control signal that pin receives the transmission of outside commutation circuit, be communicated with by CPU with the storage area that described switch-over control signal matches.
Wherein, when this serial flash Flash is applied in start up system, serial flash Flash and CPU adopts the interfaces such as IIC, SPI to connect, and serial flash Flash controls pin by the switching of configuration and is connected with outside commutation circuit, is connected with CPU by its interface accessing controller.When system reset, after outside commutation circuit receives the reset signal of watchdog circuit transmission, effective edge of reset signal is counted, and count value is decoded into binary switch-over control signal, according to order from low to high, the value of the jth bit in switch-over control signal is exported to jth to switch and control pin, j be more than or equal to 0 integer.According to switch-over control signal, CPU is communicated with the storage area that switch-over control signal matches, thus CPU accesses this storage area, read BIOS start-up routine from this storage area, realize starting.
Additionally, the switch-over control signal of output can be high/low level, or logical address.
The embodiment of the present invention controls pin by the switching for serial flash Flash additional configuration, serial storage is divided at least 2 storage areas, and switch between at least 2 storage areas of serial flash Flash by the switching control pin of configuration, read the BIOS start-up routine needed.
The invention provides a kind of serial storage and a kind of method and system dividing storage area, switched by configuration and control the storage area that pin divides serial storage, the switching that pin realizes storage area is controlled with by switching, simple to operate, and the storage space utilization factor of serial storage can be improved, reduce costs.
One of ordinary skill in the art will appreciate that all or part of step realized in above-described embodiment method is that the hardware that can carry out instruction relevant by program completes, described program can be stored in a kind of computer-readable recording medium, the above-mentioned storage medium mentioned can be ROM (read-only memory), disk or CD etc.
Above a kind of serial storage provided by the present invention and a kind of method and system dividing storage area are described in detail, for one of ordinary skill in the art, according to the thought of the embodiment of the present invention, all will change in specific embodiments and applications, in sum, this description should not be construed as limitation of the present invention.
Claims (6)
1. divide a system for storage area, it is characterized in that, comprise outside commutation circuit (310) and serial storage (320); Also comprise processor (410) and watchdog circuit (420);
Described serial storage (320) comprises m and switches control pin (110), described m switches control pin (110) and serial storage is divided into k storage area, and realize the switching between a described k storage area by described switching control pin (110), wherein, described m be more than or equal to 1 positive integer, described k for being more than or equal to 2, and is less than or equal to 2
mpositive integer;
Described processor (410) is electrically connected with described serial storage (320), described watchdog circuit (420) is electrically connected with described processor (410), and described watchdog circuit (420) is electrically connected with described outside commutation circuit (310); Described outside commutation circuit (310) controls pin (110) with described serial storage (320) by the switching configured and is electrically connected;
Described watchdog circuit (420) is for sending reset signal to described processor (410) and outside commutation circuit (310);
The described reset signal that described outside commutation circuit (310) sends for receiving described watchdog circuit (420), to the effective edge counting in described reset signal, is decoded into binary switch-over control signal by count value; And send described switch-over control signal to switching control pin (110) of described serial storage (320);
Described serial storage (320) controls pin (110) and receives by switching the described switch-over control signal that outside commutation circuit (310) sends, and is communicated with by described processor (410) with the storage area that described switch-over control signal matches;
The described reset signal that described processor (410) sends for receiving described watchdog circuit (420), accesses the storage area matched with described switch-over control signal in described serial storage (320).
2. system according to claim 1, it is characterized in that, described serial storage (320) inside comprises segment data line (240) in interface accessing controller (210), bus switch (220), inner total data line (230) and k bar;
Described interface accessing controller (210) is connected on described bus switch (220) by described inner total data line (230), described bus switch (220) is connected on the n-th storage area by n-th interior segment data line, and control pin (110) be connected with described switching, wherein, described n for being more than or equal to 1, and is less than or equal to the positive integer of k.
3. system according to claim 1 and 2, is characterized in that, described serial storage is serial flash Flash or EEPROM (Electrically Erasable Programmable Read Only Memo) EEPROM.
4. system according to claim 1 and 2, is characterized in that, the interface of described serial storage comprises IIC interface, Serial Peripheral Interface SPI and System Management Bus SMBus.
5. system according to claim 1, is characterized in that, described switch-over control signal is high level or low level, or logical address.
6. divide a method for storage area, it is characterized in that, comprising:
Control pin for serial storage configuration m switches, described m switches control pin and described serial storage is divided into k storage area;
The switching between a described k storage area is realized by described switching control pin;
Wherein, described m be more than or equal to 1 positive integer, described k for being more than or equal to 2, and is less than or equal to 2
mpositive integer;
Watchdog circuit sends reset signal to processor and outside commutation circuit;
Outside commutation circuit receives the described reset signal that described watchdog circuit sends, and to the effective edge counting in described reset signal, count value is decoded into binary switch-over control signal; And send described switch-over control signal to the switching control tube human hair combing waste of described serial storage;
Described serial storage controls by described switching the described switch-over control signal that pin receives the transmission of outside commutation circuit, is communicated with by processor with the storage area that described switch-over control signal matches;
Processor receives the described reset signal that described watchdog circuit sends, and accesses the storage area matched with described switch-over control signal in described serial storage.
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| CN113127402B (en) * | 2021-04-29 | 2024-05-14 | 广东湾区智能终端工业设计研究院有限公司 | SPI access control method, system, computing device and storage medium |
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| CN101477493A (en) * | 2008-12-17 | 2009-07-08 | 康佳集团股份有限公司 | Method for implementing block memory device |
| CN101958152A (en) * | 2010-10-19 | 2011-01-26 | 华中科技大学 | NAND FLASH controller and application thereof |
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Patent Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN101477493A (en) * | 2008-12-17 | 2009-07-08 | 康佳集团股份有限公司 | Method for implementing block memory device |
| CN101958152A (en) * | 2010-10-19 | 2011-01-26 | 华中科技大学 | NAND FLASH controller and application thereof |
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| CN102789435A (en) | 2012-11-21 |
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