CN111475343B - Computer state outage restoration method and device and terminal equipment - Google Patents

Computer state outage restoration method and device and terminal equipment Download PDF

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Publication number
CN111475343B
CN111475343B CN202010294897.9A CN202010294897A CN111475343B CN 111475343 B CN111475343 B CN 111475343B CN 202010294897 A CN202010294897 A CN 202010294897A CN 111475343 B CN111475343 B CN 111475343B
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state
computer
power
cpld
gpio
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CN111475343A (en
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杨再松
刘全仲
张思栋
曹力
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China Great Wall Technology Group Co ltd
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China Great Wall Technology Group Co ltd
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    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F11/00—Error detection; Error correction; Monitoring
    • G06F11/07—Responding to the occurrence of a fault, e.g. fault tolerance
    • G06F11/14—Error detection or correction of the data by redundancy in operation
    • G06F11/1402—Saving, restoring, recovering or retrying
    • G06F11/1415—Saving, restoring, recovering or retrying at system level
    • G06F11/1441—Resetting or repowering

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  • Theoretical Computer Science (AREA)
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  • General Engineering & Computer Science (AREA)
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Abstract

The application is applicable to the technical field of computers, and provides a computer state outage restoration method, a device and terminal equipment, wherein the computer state outage restoration method comprises the following steps: receiving input setting information of a computer state after power failure recovery; converting the setting information into a state identifier of a general purpose input output port GPIO of a basic input output system BIOS; wherein, the state identifiers of different GPIOs characterize different computer states; storing the state identification of the GPIO into a programmable logic device CPLD of a computer; and after the power-on is detected, reading the state identification of the GPIO from the CPLD, and controlling the state of the computer based on the state identification of the GPIO. For the computer without PCH, the state of the computer can be controlled through the state identification of the GPIO stored in the CPLD after the computer is powered on.

Description

Computer state outage restoration method and device and terminal equipment
Technical Field
The application belongs to the technical field of computers, and particularly relates to a computer state outage restoration method, a device and terminal equipment.
Background
On a general purpose X86 computer, the PCH (Platform Controller Hub, platform control center) embeds a separate small system Management Engine (ME), where Restore on AC Power loss functions are controlled by the ME to achieve the state of the computer when disconnected AC power is restored. Restore on AC Power loss functions are implemented by the cooperation of ME and basic input output system BIOS, and there are three general options: power Off (computer in Off state when current is restored), power On (computer in On state when current is restored), and Last state (Last state, i.e., state when Power is Off).
However, at present, some computers are not provided with PCH, so how to implement Restore on AC Power loss functions on computers not provided with PCH is a problem to be solved.
Disclosure of Invention
In order to overcome the problems in the related art, the embodiment of the application provides a computer state outage restoration method, a device and terminal equipment.
The application is realized by the following technical scheme:
in a first aspect, an embodiment of the present application provides a computer state outage restoration method, including:
receiving input setting information of a computer state after power failure recovery;
converting the setting information into a first state identifier of a general purpose input output port GPIO of a basic input output system BIOS; wherein different ones of the first state identifiers characterize different computer states;
storing the first state identifier into a programmable logic device CPLD of a computer;
and after the power-on of the computer is detected, reading the first state identifier from the CPLD, and controlling the state of the computer based on the first state identifier.
In a possible implementation manner of the first aspect, the converting the setting information into the first state identifier of the general purpose input output port GPIO of the basic input output system BIOS includes:
converting the setting information into a state identifier of two pins GPIO and a state identifier of GPIO; wherein a combination of the state identification of the gpio a and the state identification of the gpio b characterizes the setting information.
In a possible implementation manner of the first aspect, the state identifier of the gpio a and the state identifier of the gpio b each have at least two state identifiers.
In a possible implementation manner of the first aspect, the storing the first state identifier in the programmable logic device CPLD of the computer is specifically:
and storing the first state identifier into a UFM storage space of the CPLD.
In a possible implementation manner of the first aspect, in a case where the setting information characterizes that, after detecting that the computer is powered up, the computer is controlled to be in a state when the computer is powered down,
the method further comprises the steps of:
after the computer power-off is detected, generating computer power-off information that the computer power-off is normal power-off or abnormal power-off at the time;
converting the computer power failure information into a second state identifier of the GPIO, and storing the second state identifier into the CPLD;
the controlling the state of the computer includes:
and reading the second state identifier from the CPLD, and controlling the state of the computer according to the second state identifier.
In a possible implementation manner of the first aspect, the storing the computer power-off identifier in the CPLD includes:
and controlling a power supply module to supply power to the CPLD and stopping supplying power to circuits outside the CPLD.
In a possible implementation manner of the first aspect, a switching unit is provided between the power module and the circuit external to the CPLD, and the power module is controlled by the switching unit to stop supplying power to the circuit external to the CPLD.
In a second aspect, an embodiment of the present application provides a computer state outage restoration device, including:
a setting information receiving unit for receiving input setting information of the computer state after the power failure recovery;
the information conversion unit is used for converting the setting information into a first state identifier of a general purpose input output port GPIO of a basic input output system BIOS; wherein different ones of the first state identifiers characterize different computer states;
the storage unit is used for storing the first state identifier into a programmable logic device CPLD of the computer;
and the state control unit is used for reading the first state identifier from the CPLD after power-on is detected, and controlling the state of the computer based on the first state identifier.
In a third aspect, an embodiment of the present application provides a terminal device, including a memory, a processor, and a computer program stored in the memory and executable on the processor, where the processor implements the computer state outage restoration method according to any one of the first aspects when the computer program is executed by the processor.
In a fourth aspect, embodiments of the present application provide a computer readable storage medium storing a computer program which, when executed by a processor, implements a computer state outage restoration method according to any one of the first aspects.
In a fifth aspect, embodiments of the present application provide a computer program product, which when run on a terminal device, causes the terminal device to perform the computer state outage restoration method according to any one of the first aspects above.
It will be appreciated that the advantages of the second to fifth aspects may be found in the relevant description of the first aspect, and are not described here again.
Compared with the prior art, the embodiment of the application has the beneficial effects that:
in the embodiment of the application, the input setting information of the computer state after the power failure recovery is received, the setting information is converted into the first state identification of the GPIO of the BIOS, the different first state identifications represent different computer states, and the first state identifications are stored in the CPLD of the computer; and after the computer is detected to be powered on, reading a first state identifier from the CPLD, and controlling the state of the computer based on the first state identifier. For example, the setting information is a Power Off, a Power On or a Last state, which indicates that the state of the computer is controlled according to the Power Off, the Power On or the Last state after the computer is powered On, and then the first state identifier of the Power Off, the Power On or the Last state converted into the GPIO may be stored in the CPLD of the computer, and after the Power On of the computer is detected, the first state identifier is read from the CPLD, and the state of the computer is controlled according to the mode of the Power Off, the Power On or the Last state corresponding to the first state identifier.
It is to be understood that both the foregoing general description and the following detailed description are exemplary and explanatory only and are not restrictive of the disclosure.
Drawings
In order to more clearly illustrate the technical solutions of the embodiments of the present application, the drawings that are required for the embodiments or the description of the prior art will be briefly described below, it being obvious that the drawings in the following description are only some embodiments of the present application, and that other drawings may be obtained according to these drawings without inventive effort for a person skilled in the art.
Fig. 1 is an application scenario schematic diagram of a computer state outage restoration method according to an embodiment of the present application;
FIG. 2 is a flowchart of a computer state outage restoration method according to an embodiment of the present disclosure;
FIG. 3 is a schematic diagram illustrating connection between a BIOS and a CPLD according to an embodiment of the present application;
FIG. 4 is a flowchart of a computer state outage restoration method according to an embodiment of the present disclosure;
FIG. 5 is a schematic diagram of a hardware structure according to an embodiment of the present application;
FIG. 6 is a schematic diagram of a computer state outage restoration device according to an embodiment of the present disclosure;
fig. 7 is a schematic structural diagram of a terminal device provided in an embodiment of the present application.
Detailed Description
In the following description, for purposes of explanation and not limitation, specific details are set forth, such as particular system configurations, techniques, etc. in order to provide a thorough understanding of the embodiments of the present application. It will be apparent, however, to one skilled in the art that the present application may be practiced in other embodiments that depart from these specific details. In other instances, detailed descriptions of well-known systems, devices, circuits, and methods are omitted so as not to obscure the description of the present application with unnecessary detail.
It should be understood that the terms "comprises" and/or "comprising," when used in this specification and the appended claims, specify the presence of stated features, integers, steps, operations, elements, and/or components, but do not preclude the presence or addition of one or more other features, integers, steps, operations, elements, components, and/or groups thereof.
It should also be understood that the term "and/or" as used in this specification and the appended claims refers to any and all possible combinations of one or more of the associated listed items, and includes such combinations.
As used in this specification and the appended claims, the term "if" may be interpreted as "when..once" or "in response to a determination" or "in response to detection" depending on the context. Similarly, the phrase "if a determination" or "if a [ described condition or event ] is detected" may be interpreted in the context of meaning "upon determination" or "in response to determination" or "upon detection of a [ described condition or event ]" or "in response to detection of a [ described condition or event ]".
In addition, in the description of the present application and the appended claims, the terms "first," "second," "third," and the like are used merely to distinguish between descriptions and are not to be construed as indicating or implying relative importance.
Reference in the specification to "one embodiment" or "some embodiments" or the like means that a particular feature, structure, or characteristic described in connection with the embodiment is included in one or more embodiments of the application. Thus, appearances of the phrases "in one embodiment," "in some embodiments," "in other embodiments," and the like in the specification are not necessarily all referring to the same embodiment, but mean "one or more but not all embodiments" unless expressly specified otherwise. The terms "comprising," "including," "having," and variations thereof mean "including but not limited to," unless expressly specified otherwise.
On a general purpose X86 computer, the PCH (Platform Controller Hub, platform control center) embeds a separate small system Management Engine (ME), where Restore on AC Power loss functions are controlled by the ME to achieve the state of the computer when disconnected AC power is restored. Restore on AC Power loss functions are implemented by the cooperation of ME and basic input output system BIOS, and there are three general options: power Off (computer in Off state when current is restored), power On (computer in On state when current is restored), and Last state (Last state, i.e., state when Power is Off).
However, at present, some computers are not provided with PCH, so how to implement Restore on AC Power loss functions on computers not provided with PCH is a problem to be solved.
Based on the above-mentioned problems, in the method for recovering the power failure of the computer state in the embodiments of the present application, input setting information of the computer state after the power failure recovery is received, the setting information is converted into a first state identifier of a GPIO of the BIOS, and different first state identifiers represent different computer states, and the first state identifiers are stored in a CPLD of the computer; and after the computer is detected to be powered on, reading a first state identifier from the CPLD, and controlling the state of the computer based on the first state identifier. For example, the setting information is a Power Off, a Power On or a Last state, which indicates that the state of the computer is controlled according to the Power Off, the Power On or the Last state after the computer is powered On, and then the first state identifier of the Power Off, the Power On or the Last state converted into the GPIO may be stored in the CPLD of the computer, and after the Power On of the computer is detected, the first state identifier is read from the CPLD, and the state of the computer is controlled according to the mode of the Power Off, the Power On or the Last state corresponding to the first state identifier.
By way of example, the embodiments of the present application may be applied to an exemplary scenario as shown in fig. 1. In this scenario, the user may input setting information of the computer state after the Power-Off restoration in the BIOS setting interface of the computer 10, for example, the configuration information may be Power Off, power On, or Last state. The computer 10 receives input setting information of the computer state after power failure recovery, converts the setting information into a first state identifier of a GPIO of the BIOS, and the different first state identifiers represent different computer states, and stores the first state identifiers into a CPLD of the computer; and after the computer is detected to be powered on, reading a first state identifier from the CPLD, and controlling the state of the computer based on the first state identifier.
The following describes the computer state power-off recovery method in detail with reference to fig. 1.
FIG. 2 is a schematic flowchart of a computer state outage restoration method according to an embodiment of the present application, and with reference to FIG. 2, the computer state outage restoration method is described in detail below:
in step 110, input power-down restored computer state setting information is received.
The setting information may be Power Off, power On or Last state, which indicates that the state of the computer is controlled according to the mode of Power Off, power On or Last state after the computer is powered On.
Specifically, the Power Off represents that when the computer is powered on, the computer is controlled to be in a shutdown state; when the Power On indicates that the computer is powered On, the computer is controlled to be in a starting state, namely, the computer is controlled to be started; the Last state indicates that when the computer is powered on, the state of the control computer is the state when the power is off, for example, the computer is in the power-on state when the power is off, the control computer is in the power-on state when the power is on, for example, the computer is in the power-off state when the power is off, and the control computer is in the power-off state when the power is on.
In step 120, the setting information is converted into a first state identifier of a general purpose input output port GPIO of a basic input output system BIOS; wherein the different first state identifiers characterize different computer states.
In this step, the setting information is converted into a first state identifier of a General-purpose input/output (GPIO) of a BIOS of the computer, that is, the setting information is represented by the first state identifier of the GPIO, for example, the three setting information Power Off, power On, or Last state are represented.
In some embodiments, the setting information may be converted into the state identifier of the two pins GPIO and the state identifier of the GPIO b, and the combination of the state identifier of the GPIO a and the state identifier of the GPIO b may be capable of characterizing the setting information, as shown in fig. 3.
For example, the state identification of gpio a and the state identification of gpio b may each have at least two state identifications.
In an application scenario, the state identifier of the gpio a may have two state identifiers, for example, 0 or 1; the state identification of GPIOB may have two state identifications, for example 0 or 1. Then, according to the two state identifiers of the gpio a and the two state identifiers of the gpio b, a plurality of combinations may be obtained, for example, four combinations including 00, 01, 10 and 11 may be included, and three combinations 01, 10 and 11 of the four combinations respectively represent the three setting information Power Off, power On and Last state.
Of course, in other application scenarios, the state identifier of the gpio may have more than three state identifiers, and/or the state identifier of the gpio may have more than three state identifiers, and according to the various state identifiers of the gpio and the various state identifiers of the gpio, multiple combination manners may be obtained, and the three combination manners may be selected to respectively represent the three setting information Power Off, power On, and Last state.
In addition, in other application scenarios, the state identifier of the gpio a and/or the state identifier of the gpio b may be identified by other forms besides 0 or 1, which is not limited in the embodiments of the present application.
In step 130, the first status identifier is stored in the programmable logic device CPLD of the computer.
In this step, the first state identifier is stored in the CPLD of the computer, and the first state identifier is not lost after the computer is powered down, so that the first state identifier can be read after the computer is powered up to control the state of the computer.
For example, the first status identification may be stored in the UFM memory space of the CPLD. The UFM is a few bytes of FLASH memory space inside the CPLD complex, and the first state identifier is not lost after the computer is powered down.
In step 140, after detecting that the computer is powered on, the first state identifier is read from the CPLD, and the state of the computer is controlled based on the first state identifier.
Specifically, after the computer is detected to be powered On, a first state identifier stored before can be read from the CPLD, and the state of the computer is controlled according to setting information Power Off, power On or Last state represented by the first state identifier.
For example, if the setting information represented by the first state identifier is Power Off, controlling the computer to be in a shutdown state after the computer is powered on; the setting information represented by the first state identifier is Power On, and the computer is controlled to be in a starting state after the computer is powered On, namely the computer is controlled to be started; the setting information represented by the first state identifier is Last state, and then the state of the control computer is a state when power is off after the computer is powered on, for example, the computer is in a starting state when the power is off, and then the control computer is in a starting state after the computer is powered on, for example, the computer is in a shutdown state when the power is off, and then the control computer is in a shutdown state after the power is on.
FIG. 4 is a schematic flowchart of a computer state outage restoration method according to an embodiment of the present application, and with reference to FIG. 4, the computer state outage restoration method is described in detail below:
in step 210, input power-down restored computer state setting information is received.
In step 220, the setting information is converted into a first state identifier of a general purpose input output port GPIO of a basic input output system BIOS; wherein different ones of the first state identifiers characterize different ones of the computer states.
In step 230, the first status identifier is stored in the programmable logic device CPLD of the computer.
The details of steps 210 to 230 may refer to the relevant details of steps 110 to 130, and will not be repeated here.
In step 240, after detecting the computer power-off, computer power-off information is generated that the computer power-off is normal or abnormal.
The computer may be powered off normally or abnormally, and is usually powered off when normal power off occurs, and is usually powered on when abnormal power off occurs. After the computer power-off is detected, the computer power-off can be determined to be normal power-off or abnormal power-off, so that corresponding computer power-off information is generated.
In step 250, the computer power-off information is converted into a second state identification of the GPIO, and the second state identification is stored in the CPLD.
In this step, the computer power-off information is converted into the second state identifier of the GPIO, that is, the second state identifier of the GPIO indicates the power-off information of the computer, for example, indicates that the two computers are powered off normally and abnormally.
In some embodiments, the computer power-off information may be converted into a state identifier of two pins GPIO and a state identifier of GPIO, where a combination of the state identifier of GPIO and the state identifier of GPIO is capable of characterizing the computer power-off information.
In step 260, after detecting that the computer is powered on, a first state identifier is read from the CPLD, and when the first state identifier represents a Last state, a second state identifier is read from the CPLD, and the state of the computer is controlled according to the second state identifier.
In this step, after the computer is detected to be powered on, the first state identifier is read from the CPLD, and when the first state identifier indicates the Last state, it is described that the state of the computer needs to be controlled to be the state when the power is off when the computer is powered on. At this time, the second state identifier may be read from the CPLD, and the state of the computer may be controlled according to the computer power-off information (normal power-off or abnormal power-off) represented by the second state identifier.
For example, if the computer power-off information represented by the second state identifier is normal power-off, the computer is controlled to be in a power-off state after the computer is powered on; and if the computer power-off information represented by the second state identifier is abnormal power-off, controlling the computer to start after the computer is powered on, so that the computer is in a starting state.
The CPLD still needs to operate for a certain time (for example, more than 5 seconds) after the computer is powered off to write the second state identifier into the CPLD, for example, into the UFM of the CPLD. Because the circuitry outside the CPLD also continues to consume power after the computer is powered down, it may not be possible to support the CPLD for a certain period of time to write the second state identification.
Therefore, the storing the second state identifier in the CPLD may include:
controlling a power supply module to supply power to the CPLD and stopping supplying power to circuits except the CPLD;
the second state identification is stored in the CPLD.
After the computer is powered off, the super capacitor on the circuit board of the computer can continuously supply power to the CPLD for a certain time, so that the CPLD can continuously work to store the state identification data, and the CPLD can maintain the energy Q required during the working period 1 Energy Q equal to the reduction of super capacitance 2 WhereinNeglecting the pressure drop caused by IR may result in: capacitor holding time +.>I.e. the time T the capacitance remains is proportional to the capacity C of itself and inversely proportional to the current I. Wherein V is work For CPLD normal working voltage, V min And the working voltage is cut-off for CPLD, and I is CPLD working current. Because the electric energy provided by the capacitor is limited, other circuits can be separated from the power supply of the CPLD by using the switch unit, and the power supply module PSU only supplies power to the CPLD after the computer is powered off so as to reduce the current I, thereby increasing the time T for maintaining the capacitor as much as possible and advancingAfter the computer is powered off, the CPLD can keep working for as long as possible so as to store the state identification data.
For example, a switching unit may be disposed between the power module and the circuit other than the CPLD, and the power module may be controlled by the switching unit to stop supplying power to the circuit other than the CPLD. For example, the switching unit may be a MOS transistor.
Referring to fig. 5, the power supply module PSU and circuits (such as a network card and a BMC) other than the CPLD are provided with MOS transistors, and the PSU and the CPLD directly supply power, the normal CPLD pulls down the voltage of the G pole of the MOS transistor, the MOS transistors are turned on, and the standby3v3 of the PSU is simultaneously supplied to the CPLD and the circuits other than the CPLD; when the computer is abnormally powered off and shut down, the CPLD pulls up the voltage of the G pole of the MOS tube, and the MOS tube is disconnected, so that the standby3v3 of the PSU stops supplying power to circuits other than the CPLD, and the standby3v3 of the PSU only supplies power to the CPLD.
According to the computer state outage restoration method, the input setting information of the computer state after outage restoration is received, the setting information is converted into the first state identification of the GPIO of the BIOS, different first state identifications represent different computer states, and the first state identifications are stored in the CPLD of the computer; and after the computer is detected to be powered on, reading a first state identifier from the CPLD, and controlling the state of the computer based on the first state identifier. For example, the setting information is a Power Off, a Power On or a Last state, which indicates that the state of the computer is controlled according to the Power Off, the Power On or the Last state after the computer is powered On, and then the first state identifier of the Power Off, the Power On or the Last state converted into the GPIO may be stored in the CPLD of the computer, and after the Power On of the computer is detected, the first state identifier is read from the CPLD, and the state of the computer is controlled according to the mode of the Power Off, the Power On or the Last state corresponding to the first state identifier.
It should be understood that the sequence number of each step in the foregoing embodiment does not mean that the execution sequence of each process should be determined by the function and the internal logic of each process, and should not limit the implementation process of the embodiment of the present application in any way.
Corresponding to the computer state outage restoration method described in the above embodiments, fig. 6 shows a block diagram of the computer state outage restoration device provided in the embodiment of the present application, and for convenience of explanation, only the portions relevant to the embodiments of the present application are shown.
Referring to fig. 6, the computer state power-off restoration device in the embodiment of the present application may include a setting information receiving unit 301, an information converting unit 302, a storage unit 303, and a state control unit 304;
wherein, the setting information receiving unit 301 is configured to receive input setting information of a computer state after power failure recovery;
an information conversion unit 302, configured to convert the setting information into a first state identifier of a general purpose input output port GPIO of a basic input output system BIOS; wherein different ones of the first state identifiers characterize different computer states;
a storage unit 303, configured to store the first state identifier into a programmable logic device CPLD of a computer;
and the state control unit 304 is configured to read the first state identifier from the CPLD after power-up is detected, and control a computer state based on the first state identifier.
Alternatively, the information conversion unit 302 may specifically be configured to:
converting the setting information into a state identifier of two pins GPIO and a state identifier of GPIO; wherein a combination of the state identification of the gpio a and the state identification of the gpio b characterizes the setting information.
Illustratively, the state identification of the gpio a and the state identification of the gpio b each have at least two state identifications.
Optionally, the storage unit 303 may specifically be configured to:
and storing the first state identifier into a UFM storage space of the CPLD.
Optionally, in a case that the setting information characterizes that after the computer is detected to be powered on, the computer is controlled to be in a state when the computer is powered off, the apparatus may further include:
the power-off detection module is used for generating computer power-off information that the computer power-off is normal power-off or abnormal power-off after detecting that the computer is powered off;
the state identifier conversion unit is used for converting the computer power failure information into a second state identifier of the GPIO and storing the second state identifier into the CPLD;
the state control unit 304 may specifically be configured to:
and reading the second state identifier from the CPLD, and controlling the state of the computer according to the second state identifier.
Optionally, the process performed by the state identifier conversion unit to store the second state identifier in the CPLD may specifically be:
controlling a power supply module to supply power to the CPLD and stopping supplying power to circuits outside the CPLD;
and storing the second state identification into the CPLD.
For example, a switching unit may be provided between the power module and the circuit other than the CPLD, and the power module may be controlled by the switching unit to stop supplying power to the circuit other than the CPLD.
It should be noted that, because the content of information interaction and execution process between the above devices/units is based on the same concept as the method embodiment of the present application, specific functions and technical effects thereof may be referred to in the method embodiment section, and will not be described herein again.
It will be apparent to those skilled in the art that, for convenience and brevity of description, only the above-described division of the functional units and modules is illustrated, and in practical application, the above-described functional distribution may be performed by different functional units and modules according to needs, i.e. the internal structure of the apparatus is divided into different functional units or modules to perform all or part of the above-described functions. The functional units and modules in the embodiment may be integrated in one processing unit, or each unit may exist alone physically, or two or more units may be integrated in one unit, where the integrated units may be implemented in a form of hardware or a form of a software functional unit. In addition, specific names of the functional units and modules are only for convenience of distinguishing from each other, and are not used for limiting the protection scope of the present application. The specific working process of the units and modules in the above system may refer to the corresponding process in the foregoing method embodiment, which is not described herein again.
The embodiment of the present application further provides a terminal device, referring to fig. 7, the terminal device 400 may include: at least one processor 410, a memory 420, and a computer program stored in the memory 420 and executable on the at least one processor 410, the processor 410, when executing the computer program, performing steps in any of the various method embodiments described above, such as steps S101 to S104 in the embodiment shown in fig. 2. Alternatively, the processor 410 may implement the functions of the modules/units in the above-described embodiments of the apparatus, such as the functions of the modules 301 to 304 shown in fig. 6, when executing the computer program.
By way of example, a computer program may be partitioned into one or more modules/units that are stored in memory 420 and executed by processor 410 to complete the present application. The one or more modules/units may be a series of computer program segments capable of performing specific functions for describing the execution of the computer program in the terminal device 400.
It will be appreciated by those skilled in the art that fig. 7 is merely an example of a terminal device and is not limiting of the terminal device, and may include more or fewer components than shown, or may combine certain components, or different components, such as input-output devices, network access devices, buses, etc.
The processor 410 may be a central processing unit (Central Processing Unit, CPU), but may also be other general purpose processors, digital signal processors (Digital Signal Processor, DSP), application specific integrated circuits (Application Specific Integrated Circuit, ASIC), off-the-shelf programmable gate arrays (Field-Programmable Gate Array, FPGA) or other programmable logic devices, discrete gate or transistor logic devices, discrete hardware components, or the like. A general purpose processor may be a microprocessor or the processor may be any conventional processor or the like.
The memory 420 may be an internal storage unit of the terminal device, or may be an external storage device of the terminal device, such as a plug-in hard disk, a Smart Media Card (SMC), a Secure Digital (SD) Card, a Flash memory Card (Flash Card), or the like. The memory 420 is used for storing the computer program as well as other programs and data required by the terminal device. The memory 420 may also be used to temporarily store data that has been output or is to be output.
The bus may be an industry standard architecture (Industry Standard Architecture, ISA) bus, an external device interconnect (Peripheral Component, PCI) bus, or an extended industry standard architecture (Extended Industry Standard Architecture, EISA) bus, among others. The buses may be divided into address buses, data buses, control buses, etc. For ease of illustration, the buses in the drawings of the present application are not limited to only one bus or one type of bus.
Embodiments of the present application also provide a computer readable storage medium storing a computer program that, when executed by a processor, implements steps in each embodiment of a computer state outage restoration method described above.
Embodiments of the present application provide a computer program product that, when executed on a mobile terminal, enables the mobile terminal to implement the steps described in the embodiments of the computer state outage restoration method described above.
The integrated units, if implemented in the form of software functional units and sold or used as stand-alone products, may be stored in a computer readable storage medium. Based on such understanding, the present application implements all or part of the flow of the method of the above embodiments, and may be implemented by a computer program to instruct related hardware, where the computer program may be stored in a computer readable storage medium, where the computer program, when executed by a processor, may implement the steps of each of the method embodiments described above. Wherein the computer program comprises computer program code which may be in source code form, object code form, executable file or some intermediate form etc. The computer readable medium may include at least: any entity or device capable of carrying computer program code to a photographing device/terminal apparatus, recording medium, computer Memory, read-Only Memory (ROM), random access Memory (RAM, random Access Memory), electrical carrier signals, telecommunications signals, and software distribution media. Such as a U-disk, removable hard disk, magnetic or optical disk, etc. In some jurisdictions, computer readable media may not be electrical carrier signals and telecommunications signals in accordance with legislation and patent practice.
In the foregoing embodiments, the descriptions of the embodiments are emphasized, and in part, not described or illustrated in any particular embodiment, reference is made to the related descriptions of other embodiments.
Those of ordinary skill in the art will appreciate that the various illustrative elements and algorithm steps described in connection with the embodiments disclosed herein may be implemented as electronic hardware, or combinations of computer software and electronic hardware. Whether such functionality is implemented as hardware or software depends upon the particular application and design constraints imposed on the solution. Skilled artisans may implement the described functionality in varying ways for each particular application, but such implementation decisions should not be interpreted as causing a departure from the scope of the present application.
In the embodiments provided in the present application, it should be understood that the disclosed apparatus/network device and method may be implemented in other manners. For example, the apparatus/network device embodiments described above are merely illustrative, e.g., the division of the modules or units is merely a logical functional division, and there may be additional divisions in actual implementation, e.g., multiple units or components may be combined or integrated into another system, or some features may be omitted, or not performed. Alternatively, the coupling or direct coupling or communication connection shown or discussed may be an indirect coupling or communication connection via interfaces, devices or units, which may be in electrical, mechanical or other forms.
The units described as separate units may or may not be physically separate, and units shown as units may or may not be physical units, may be located in one place, or may be distributed on a plurality of network units. Some or all of the units may be selected according to actual needs to achieve the purpose of the solution of this embodiment.
The above embodiments are only for illustrating the technical solution of the present application, and are not limiting; although the present application has been described in detail with reference to the foregoing embodiments, it should be understood by those of ordinary skill in the art that: the technical scheme described in the foregoing embodiments can be modified or some technical features thereof can be replaced by equivalents; such modifications and substitutions do not depart from the spirit and scope of the technical solutions of the embodiments of the present application, and are intended to be included in the scope of the present application.

Claims (8)

1. A computer state outage restoration method comprising:
receiving setting information of a computer state after Power-Off recovery, which is input by a user at a BIOS setting interface of the computer, wherein the setting information is Power Off, power On or Last state and represents that the state of the computer is controlled in a mode of Power Off, power On or Last state after the computer is powered On;
converting the setting information into a first state identifier of a general purpose input output port GPIO of a basic input output system BIOS; wherein different ones of the first state identifiers characterize different computer states;
storing the first state identifier into a programmable logic device CPLD of a computer;
after detecting that the computer is powered on, reading the first state identifier from the CPLD, and controlling the state of the computer based on the first state identifier;
the converting the setting information into a first state identifier of a general purpose input output port GPIO of a basic input output system BIOS includes:
converting the setting information into a state identifier of two pins GPIO and a state identifier of GPIO; wherein a combination of the state identification of the gpio a and the state identification of the gpio b characterizes the setting information;
the state identifier of the GPIOA and the state identifier of the GPIOB are provided with at least two state identifiers.
2. The method for recovering the power failure of the computer state according to claim 1, wherein the storing the first state identifier in the programmable logic device CPLD of the computer is specifically:
and storing the first state identifier into a UFM storage space of the CPLD.
3. The method for recovering a power-off state of a computer according to any one of claims 1 to 2, wherein when the setting information is Last state, in a case where the setting information characterizes a state in which the control computer state is a state when the computer is powered off after detecting that the computer is powered on,
the method further comprises the steps of:
after the computer power-off is detected, generating computer power-off information that the computer power-off is normal power-off or abnormal power-off at the time;
converting the computer power failure information into a second state identifier of the GPIO, and storing the second state identifier into the CPLD;
the controlling the state of the computer includes:
and reading the second state identifier from the CPLD, and controlling the state of the computer according to the second state identifier.
4. The computer state power down restoration method as recited in claim 3, wherein said storing a second state identification into said CPLD comprises:
controlling a power supply module to supply power to the CPLD and stopping supplying power to circuits outside the CPLD;
and storing the second state identification into the CPLD.
5. The computer state power-off restoration method according to claim 4, wherein a switching unit is provided between the power module and a circuit other than the CPLD, and the power module is controlled by the switching unit to stop supplying power to the circuit other than the CPLD.
6. A computer state outage restoration device comprising:
the setting information receiving unit is used for receiving setting information of the computer state after the Power-Off recovery, which is input by a user at a BIOS setting interface of the computer, wherein the setting information is Power Off, power On or Last state and represents that the state of the computer is controlled in a mode of Power Off, power On or Last state after the computer is powered On;
the information conversion unit is used for converting the setting information into a first state identifier of a general purpose input output port GPIO of a basic input output system BIOS; wherein different ones of the first state identifiers characterize different computer states;
the storage unit is used for storing the first state identifier into a programmable logic device CPLD of the computer;
the state control unit is used for reading the first state identifier from the CPLD after power-on is detected, and controlling the state of the computer based on the first state identifier;
the converting the setting information into a first state identifier of a general purpose input output port GPIO of a basic input output system BIOS includes:
converting the setting information into a state identifier of two pins GPIO and a state identifier of GPIO; wherein a combination of the state identification of the gpio a and the state identification of the gpio b characterizes the setting information;
the state identifier of the GPIOA and the state identifier of the GPIOB are provided with at least two state identifiers.
7. A terminal device comprising a memory, a processor and a computer program stored in the memory and executable on the processor, characterized in that the processor implements the method according to any of claims 1 to 5 when executing the computer program.
8. A computer readable storage medium storing a computer program, characterized in that the computer program when executed by a processor implements the method according to any one of claims 1 to 5.
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