CN103809987A - Method for replacing FPGA IP program in SOC chip - Google Patents
Method for replacing FPGA IP program in SOC chip Download PDFInfo
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- CN103809987A CN103809987A CN201210441579.6A CN201210441579A CN103809987A CN 103809987 A CN103809987 A CN 103809987A CN 201210441579 A CN201210441579 A CN 201210441579A CN 103809987 A CN103809987 A CN 103809987A
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Abstract
The invention discloses a method for replacing an FPGA IP program in an SOC chip, which comprises the following steps: the MCU IP configures a configuration interface of the FPGA IP through a general IO interface of the MCU IP, so that the FPGA IP in a normal working state enters a program downloading mode; the MCU IP inputs a specific command byte of read data to the serial FLASH memory through a general IO interface of the MCU IP, and then inputs an initial address where a program code needing to be configured is positioned, so that the serial FLASH memory starts to output data from the initial address to the FPGAIP; the FPGAIP which enters the program downloading mode starts to receive the data output by the serial FLASH memory for program downloading; and when the FPGA IP receives the data output by all the FLASH memories, the program downloading work is completed, the program downloading mode is skipped out, and the configuration completion mode is entered to realize the replacement of the FPGAIP program in the FPGA IP.
Description
Technical field
The present invention relates to embedded system field, relate in particular to the method for the inner FPGAIP program of a kind of SOC chip replacing self.
Background technology
In current embedded system, due to the demand of function and performance is constantly increased, the design complexities of embedded system is also increased, so almost can both see the figure of SOC chip in all embedded systems.
By the needed multiple IP kernels of integrated system, as the IP kernel of processing digital signal and the IP kernels of Analog signals such as MCU IP, DSP IP, FPGAIP, realize integrated very many independent chip functions in very little chip volume, greatly promote the integrated level of one single chip, thereby simplified the design complexities of whole embedded system.
The SOC chip the present invention relates to is the SOC chip of a integrated FPGA IP and MCU IP, wherein FPGA IP is that the capacity of a Domestic Scientific Research institutes's independent research is the FPGAIP of 2000 logical blocks, and MCU IP is the general MCU IP of a 8 of being designed by offshore company.
Above-mentioned SOC has now been widely used in, in SAR radar encryption system, completing the function of data encryption.In view of the parallel data processing power of FPGA is stronger, and MCU has innate advantage on aspect Application of Interface and control, so FPGAIP is mainly responsible for the realization of cryptographic algorithm, MCU IP is mainly responsible for the work such as key management and interface communication.
Due to the specific demand of system to encryption method, must often change different cryptographic algorithm according to different occasions, namely need to change at any time online FPGA IP program, thereby realize the object of changing cryptographic algorithm, but because the bootstrap loading program of the FPGA IP of present stage can only load the program in the fixed address region of FLASH storer, so need to increase extra Digital Logic and go to control the loading procedure of FPGAIP program.
Due to the restriction of system cost and complexity, do not allow to increase again extra controller or processor completes above-mentioned functions, therefore in the urgent need to developing a kind of method that can complete by the digital control part of SOC chip self replacing FPGA IP program, so both simplify system complexity, effectively reduced again cost.
Summary of the invention
(1) technical matters that will solve
In view of this, fundamental purpose of the present invention is to provide the method for the inner FPGA IP program of a kind of SOC chip replacing self, under the prerequisite that does not increase additional hardware cost, complete by SOC chip internal resource the function of changing FPGA IP program, and then simplify system complexity, reduce costs.
(2) technical scheme
For achieving the above object, the invention provides the method for the inner FPGA IP program of a kind of SOC chip replacing self, this SOC chip comprises FPGA IP and MCU IP, the multiple programs that use in FPGA IP are kept in a serial FLASH memory, the configuration interface of FPGA IP and the general Purpose IO Interface of MCUIP are all connected in the serial line interface of serial FLASH memory, and the general Purpose IO Interface of MCU IP is connected with the configuration interface of FPGA IP, and the method comprises:
Being configured of step 1:MCU IP configuration interface to FPGA IP by its general Purpose IO Interface, makes FPGA IP in normal operation enter into program downloading mode;
Step 2:MCU IP is the particular command byte to serial FLASH memory input read data by its general Purpose IO Interface, input subsequently needs the start address at the program code place of configuration, makes serial FLASH memory start to export data from this start address to FPGA IP;
Step 3: the FPGA IP that has entered into program downloading mode starts to receive the data of serial FLASH memory output, carries out program download;
Step 4: when FPGA IP has received after the data of all FLASH storeies output, completed program download work, jumped out program downloading mode, entered into configure and become the mode, realized the replacing of self inner FPGAIP program.
In such scheme, being configured of the IP of MCU described in step 1 configuration interface to FPGA IP by its general Purpose IO Interface, be by the fixing pin in the configuration interface of FPGA IP is configured to particular level, make FPGA IP in normal operation enter into program downloading mode.
In such scheme, FPGAIP described in step 1 enters into after program downloading mode, also comprises: FPGA IP informs MCU IP by configuration pin, and it successfully enters downloading mode.
In such scheme, the IP of FPGA described in step 4 enters into and configures while becoming the mode, also comprises: FPGAIP informs MCU IP by its configuration interface, and it has entered into configure and has become the mode.
In such scheme, described MCU IP is used for the program of the FPGA IP that changes the SOC chip that coexists.
In such scheme, described FPGA IP and MCU IP communicate by SFR (SpecialFunction Register) bus of MCU IP, make MCU IP FPGA IP can be used as to a peripheral hardware and conduct interviews.
(3) beneficial effect
Can find out from technique scheme, the present invention has following beneficial effect:
1) the present invention carries out program change by the MCU IP of SOC inside to the FPGA IP that coexists inner, not extra increase hardware cost, and also it is simpler that system is realized, and so both simplified system complexity, effectively reduces again cost.
2) in FLASH storer, can deposit the program of multiple FPGAIP, replacing program in real time makes the mode of operation of FPGA IP very versatile and flexible, adapts to multiple application scenario.
Accompanying drawing explanation
Fig. 1 is the method flow diagram of the inner FPGA IP program of SOC chip replacing provided by the invention self;
Fig. 2 be realize method shown in Fig. 1 based on chief component and the annexation schematic diagram of hardware;
Fig. 3 is the method flow diagram according to the inner FPGA IP program of SOC chip replacing self of one embodiment of the invention.
Embodiment
For making the object, technical solutions and advantages of the present invention clearer, below in conjunction with specific embodiment, and with reference to accompanying drawing, the present invention is described in more detail.
As shown in Figure 1, Fig. 1 is the method flow diagram of the inner FPGA IP program of SOC chip replacing provided by the invention self, and the method comprises the following steps:
Being configured of step 1:MCU IP configuration interface to FPGA IP by its general Purpose IO Interface, makes FPGA IP in normal operation enter into program downloading mode;
Step 2:MCU IP is the particular command byte to serial FLASH memory input read data by its general Purpose IO Interface, input subsequently needs the start address at the program code place of configuration, makes serial FLASH memory start to export data from this start address to FPGA IP;
Step 3: the FPGA IP that has entered into program downloading mode starts to receive the data of serial FLASH memory output, carries out program download;
Step 4: when FPGA IP has received after the data of all FLASH storeies output, completed program download work, jumped out program downloading mode, entered into configure and become the mode, realized the replacing of self inner FPGA IP program.
Wherein, being configured of the IP of MCU described in step 1 configuration interface to FPGA IP by its general Purpose IO Interface, be by the fixing pin in the configuration interface of FPGA IP is configured to particular level, make FPGA IP in normal operation enter into program downloading mode.
The IP of FPGA described in step 1 enters into after program downloading mode, also comprises: FPGA IP informs MCU IP by configuration pin, and it successfully enters downloading mode.
The IP of FPGA described in step 4 enters into and configures while becoming the mode, also comprises: FPGA IP informs MCU IP by its configuration interface, and it has entered into configure and has become the mode.
SOC chip based on shown in Fig. 1 is changed the method for self inner FPGA IP program, Fig. 2 be realize method shown in Fig. 1 based on chief component and the annexation schematic diagram of hardware.SOC chip involved in the present invention is the SOC chip of a integrated FPGA IP and MCU IP, wherein FPGA IP is that the capacity of a Domestic Scientific Research institutes's independent research is the FPGA IP of 2000 logical blocks, and MCU IP is the general MCU IP of a 8 of being designed by offshore company.This SOC chip comprises FPGAIP and MCU IP, the multiple programs that use in FPGA IP are kept in a serial FLASH memory, the general Purpose IO Interface of the configuration interface of FPGA IP and MCU IP is all connected in the serial line interface of serial FLASH memory, and the general Purpose IO Interface of MCU IP and the configuration interface of FPGAIP are connected.
Wherein, described MCU IP is used for the program of the FPGA IP that changes the SOC chip that coexists.Described FPGA IP and MCU IP communicate by SFR (the Special Function Register) bus of MCU IP, make MCU IP FPGA IP can be used as to a peripheral hardware and conduct interviews.The binary code of preserving respectively FPGA IP and MCU IP program imports to respectively in FPGA IP and MCU IP in the time that system powers on.
Below in conjunction with Fig. 3, embodiments of the invention are described further, but this embodiment should not be construed limitation of the present invention.
Step 1: first, the special fever writes of several FPGA IP program code FLASH that needs are used is written to the different addresses section of FLASH storer.
Step 2: MCU IP is connected with main control system.
Step 3: send instruction by main control system to MCU IP, inform that the program in its FPGA IP needs to change, inform the start address of its new program in FLASH storer simultaneously.
FPGA IP is configured to downloading mode by step 4:MCU IP, then, by the order of read data and start address input FLASH storer, can from main control system, see that MCUIP beams back the successful information of download after having downloaded.
Above-described specific embodiment; object of the present invention, technical scheme and beneficial effect are further described; institute is understood that; the foregoing is only specific embodiments of the invention; be not limited to the present invention; within the spirit and principles in the present invention all, any modification of making, be equal to replacement, improvement etc., within all should being included in protection scope of the present invention.
Claims (6)
1. the method for the inner FPGA IP program of SOC chip replacing self, this SOC chip comprises FPGA IP and MCU IP, the multiple programs that use in FPGA IP are kept in a serial FLASH memory, the general Purpose IO Interface of the configuration interface of FPGA IP and MCU IP is all connected in the serial line interface of serial FLASH memory, and the general Purpose IO Interface of MCU IP is connected with the configuration interface of FPGA IP, and the method comprises:
Being configured of step 1:MCU IP configuration interface to FPGA IP by its general Purpose IO Interface, makes FPGA IP in normal operation enter into program downloading mode;
Step 2:MCU IP is the particular command byte to serial FLASH memory input read data by its general Purpose IO Interface, input subsequently needs the start address at the program code place of configuration, makes serial FLASH memory start to export data from this start address to FPGA IP;
Step 3: the FPGA IP that has entered into program downloading mode starts to receive the data of serial FLASH memory output, carries out program download;
Step 4: when FPGA IP has received after the data of all FLASH storeies output, completed program download work, jumped out program downloading mode, entered into configure and become the mode, realized the replacing of self inner FPGA IP program.
2. the method for the inner FPGA IP program of SOC chip replacing according to claim 1 self, it is characterized in that, being configured of the IP of MCU described in step 1 configuration interface to FPGA IP by its general Purpose IO Interface, be by the fixing pin in the configuration interface of FPGA IP is configured to particular level, make FPGA IP in normal operation enter into program downloading mode.
3. the method for the inner FPGA IP program of SOC chip replacing according to claim 2 self, is characterized in that, FPGAIP described in step 1 enters into after program downloading mode, also comprises:
FPGA IP informs MCU IP by configuration pin, and it successfully enters downloading mode.
4. the method for the inner FPGA IP program of SOC chip replacing according to claim 1 self, is characterized in that, the IP of FPGA described in step 4 enters into and configures while becoming the mode, also comprises:
FPGA IP informs MCU IP by its configuration interface, and it has entered into configure and has become the mode.
5. the method for the inner FPGA IP program of SOC chip replacing according to claim 1 self, is characterized in that, described MCU IP is used for the program of the FPGA IP that changes the SOC chip that coexists.
6. the method for the inner FPGA IP program of SOC chip replacing according to claim 1 self, it is characterized in that, described FPGA IP and MCU IP communicate by SFR (SpecialFunction Register) bus of MCU IP, make MCU IP FPGA IP can be used as to a peripheral hardware and conduct interviews.
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| CN201210441579.6A CN103809987A (en) | 2012-11-07 | 2012-11-07 | Method for replacing FPGA IP program in SOC chip |
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Cited By (4)
| Publication number | Priority date | Publication date | Assignee | Title |
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| CN104049995A (en) * | 2014-05-23 | 2014-09-17 | 北京兆易创新科技股份有限公司 | Method and device for configuring FPGA (field programmable gate array) in MCU (microprogrammed control unit) chip |
| CN110297660A (en) * | 2019-06-25 | 2019-10-01 | 江苏沁恒股份有限公司 | SOC kernel is accelerated to read the method and system of instruction |
| CN110442352A (en) * | 2019-07-23 | 2019-11-12 | 武汉光迅科技股份有限公司 | A kind of the code method for down loading and device of DSP |
| CN111124433A (en) * | 2018-10-31 | 2020-05-08 | 华北电力大学扬中智能电气研究中心 | Program programming device, system and method |
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Cited By (7)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN104049995A (en) * | 2014-05-23 | 2014-09-17 | 北京兆易创新科技股份有限公司 | Method and device for configuring FPGA (field programmable gate array) in MCU (microprogrammed control unit) chip |
| CN104049995B (en) * | 2014-05-23 | 2017-06-16 | 北京兆易创新科技股份有限公司 | The method and apparatus that FPGA is configured in MCU chip |
| CN111124433A (en) * | 2018-10-31 | 2020-05-08 | 华北电力大学扬中智能电气研究中心 | Program programming device, system and method |
| CN111124433B (en) * | 2018-10-31 | 2024-04-02 | 华北电力大学扬中智能电气研究中心 | Program programming equipment, system and method |
| CN110297660A (en) * | 2019-06-25 | 2019-10-01 | 江苏沁恒股份有限公司 | SOC kernel is accelerated to read the method and system of instruction |
| CN110442352A (en) * | 2019-07-23 | 2019-11-12 | 武汉光迅科技股份有限公司 | A kind of the code method for down loading and device of DSP |
| CN110442352B (en) * | 2019-07-23 | 2023-11-07 | 武汉光迅科技股份有限公司 | Code downloading method and device for DSP |
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