CN113553081A

CN113553081A - FPGA loading method based on ZYNQ chip

Info

Publication number: CN113553081A
Application number: CN202110844994.5A
Authority: CN
Inventors: 张清洪; 张建刚; 肖均; 王智宏; 罗孝杰; 高珊
Original assignee: Chengdu Yilingte Technology Co ltd
Current assignee: Chengdu Yilingte Technology Co ltd
Priority date: 2021-07-26
Filing date: 2021-07-26
Publication date: 2021-10-26

Abstract

The invention discloses a ZYNQ chip-based FPGA loading method, which comprises the following steps: the method comprises the steps of power-on automatic loading during power-on starting and upper computer controlled loading after a ZYNQ system is started; the process of the power-on automatic loading comprises the following steps: when the equipment is powered on and started, the loading mode of the FPGA is defaulted to active loading, and at the moment, the FPGA actively reads files from Flash2 and loads the files quickly; the process of controlling loading by the upper computer comprises the following steps: after the ZYNQ system runs, automatically running a control daemon, monitoring a network port and responding to an upper computer command; the upper computer establishes communication with a ZYNQ system by using modes of an internet port, a serial port and the like, and issues an FPGA code to be updated; the ZYNQ system receives data, stores the data in a DDR3 internal memory, verifies the data and feeds back a verification result to the upper computer; and the ZYNQ system determines an equipment updating mode according to the instruction of the upper computer. The ZYNQ chip-based FPGA loading method provided by the invention has the characteristics of quick and convenient FPGA updating and short equipment interrupt working time.

Description

FPGA loading method based on ZYNQ chip

Technical Field

The invention relates to the technical field of FPGA program updating, in particular to an FPGA loading method based on a ZYNQ chip.

Background

At present, most FPGA chips are based on the structure of an SRAM, data in an SRAM unit is lost after power failure, so that after a system is powered on, correct configuration data must be loaded into the SRAM by a configuration circuit, after configuration is completed, the FPGA enters a working state, after power failure, the FPGA is restored to a white chip, internal logic relations disappear, and therefore the FPGA needs to be reconfigured once when being powered on every time.

The FPGA device has three types of configuration downloading modes: an active configuration mode, a passive configuration mode and a JTAG mode; active configuration mode: the FPGA is used as a controller when being electrified every time, the FPGA device guides a configuration operation process, controls an external memory and an initialization process, and actively sends a data reading signal to the configuration device, so that data of Flash is read into the FPGA, and the FPGA is programmed; passive configuration mode: an external computer or a controller controls the configuration process, the FPGA is used as a memory, data are written into the FPGA to realize the programming of the FPGA, and the FPGA can be programmed on line by the mode; JTAG mode: JTAG is directly burned into FPGA, and is suitable for use in debugging and testing. The passive configuration mode configures the FPGA through an external CPU, the FPGA configured by the CPU can be loaded only after the CPU is operated, and the FPGA cannot be loaded once the CPU is powered on, so that the loading time is long during the power-on process. Flash is loaded at a high speed, but the content of Flash data is relatively troublesome to update, the Flash data is generally programmed through JTAG before leaving a factory, and the Flash content is very troublesome to update after leaving the factory. Based on the above problems, it is necessary to provide a new FPGA loading method based on a ZYNQ chip.

Disclosure of Invention

The invention aims to provide an FPGA loading method based on a ZYNQ chip, which can adopt two loading modes of active loading and passive loading, can select whether to update Flash or not, and has the characteristics of quick and convenient FPGA updating and short equipment interruption working time.

In order to achieve the purpose, the invention provides the following scheme:

a ZYNQ chip-based FPGA loading method is applied to equipment consisting of a ZYNQ system, a Flash memory and an FPGA, wherein the ZYNQ system is divided into a PL end and a PS end, the Flash memory comprises a Flash1 and a Flash2, the Flash1 is used for storing ZYNQ loading data, and the Flash2 is used for storing FPGA configuration data, and is characterized by comprising the following steps: the method comprises the steps of power-on automatic loading during power-on starting and upper computer controlled loading after a ZYNQ system is started;

the process of the power-on automatic loading comprises the following steps: when the equipment is powered on and started, the ZYNQ system is started, the data of the Flash1 is read, the PS end and the PL end of the ZYNQ system are loaded, the loading mode of the FPGA is defaulted to be active loading, and at the moment, the FPGA actively reads files from the Flash2 and loads the files quickly;

the specific steps of the upper computer for controlling loading comprise:

s1, broadcasting a searching device command by upper computer software;

s2, the control daemon of ZYNQ receives the search broadcast and responds to the basic information of the equipment;

s3, the upper computer displays the basic information of the searched equipment;

s4, selecting equipment from the upper computer software by a user, selecting a file to be loaded, and issuing a loading command;

s5, the upper computer software starts the file downloading service according to the predefined port;

s6, the upper computer software sends a loading command to inform the device of the service IP address, the network port, the file name and the MAC address information of the controlled device;

s7, the control daemon of the equipment receives the loading command, and analyzes the loading command to obtain the IP address, the network port, the file name and the MAC address of the controlled equipment of the upper computer;

s8, checking whether the MAC address of the controlled equipment is consistent with the MAC address of the equipment, if so, starting a downloading task by the equipment control daemon process, and downloading a file from an upper computer server;

and S9, the device control daemon verifies the downloaded file, verifies the file type, determines the device updating mode according to the instruction requirement of the user if the file type is correct, and replies an error response if the file type is not correct.

Optionally, in the step S9 in the specific step of controlling and loading by the upper computer, the device control daemon verifies the downloaded file, verifies the file type, and determines a device update mode according to the instruction requirement of the user if the file type is correct, otherwise, replies an error response, where the device update mode includes: updating only the FPGA, updating only the Flash2, updating only the FPGA and updating only the Flash 2.

Optionally, the specific step of updating the FPGA includes:

b1, configuring the application program to generate a program signal and starting programming;

b2, the FPGA receives the program signal, the internal circuit initializes and pulls down the init signal, and after the initialization is completed, the FPGA pulls up the init signal;

b3, after the program control command is sent by the configuration application program, then initializing the DMA controller; opening a file, reading 8192 bytes of data each time, calling a DMA interface to write the data into FIFO in a configuration logic, and continuing until the file is sent;

b4, receiving FIFO data by a logic configuration program in the ZYNQ system, monitoring the init signal level, and waiting for the init signal of the FPGA to be pulled high;

b5, the configuration logic receives the init of the high level, and generates a time sequence which meets the configuration requirement of the FPGA to complete data loading;

b6, after the normal loading of the FPGA is finished, releasing the DONE signal, wherein the DONE signal which is not normally loaded is always low;

b7, the configuration application program starts to monitor the DONE signal output by the FPGA after the file is sent, waits for a period of time, if the DONE signal with high level is received, the FPGA is loaded completely, otherwise the loading fails;

and B8, configuring the application program to report the operation result.

Optionally, the specific step of updating Flash2 includes:

c1, the configuration application program starts the Flash2 updating flow according to the instruction issued by the client;

c2, configuring an application program to calculate an erasing area of the Flash2, and converting block addresses of the Flash2 to be erased according to the erasing area;

c3, the configuration application program issues the operation address and the operation data of Flash2 to the configuration logic through the AXI bus;

c4, converting the configuration logic into a read-write time sequence of Flash2 according to the contents of the register, sequentially erasing the block addresses of the Flash2, and circularly erasing the area to be written all the time;

c5, configuring an application program to start reading files, reading the files by taking the page size of Flash2 as a unit each time, and calculating the written Flash2 page address;

c6, writing in a page of data, issuing a Flash2 programming command, waiting for the page programming state to be completed, and circulating until the whole file is finished;

and C7, reading the Flash2 status register to judge whether the written file is correct or not, and reporting the operation result.

Optionally, the FPGA and the Flash2 are both updated, specifically: flash2 is updated after the FPGA is updated.

According to the specific embodiment provided by the invention, the invention discloses the following technical effects: according to the FPGA loading method based on the ZYNQ chip, provided by the invention, the FPGA is directly and quickly loaded through Flash when the system is powered on, the system can conveniently communicate with an upper computer after the ZYNQ system runs, FPGA codes can be quickly updated through the FPGA high-speed configuration channels of PS and PL, the FPGA updating time is shortened to the maximum extent, and the interruption time of equipment is reduced; when the device works normally, the plug-in Flash is updated, and the work of the FPGA cannot be influenced by updating the Flash. According to the FPGA loading method based on the ZYNQ chip, the FPGA can quickly load files at any time through a scheme of combining active loading and passive loading of the FPGA, the FPGA and the Flash are respectively updated by using the controller, and the advantages of being least in FPGA updating time, shortest in equipment interruption working time and convenient in Flash data updating are achieved.

Drawings

In order to more clearly illustrate the embodiments of the present invention or the technical solutions in the prior art, the drawings needed in the embodiments will be briefly described below, and it is obvious that the drawings in the following description are only some embodiments of the present invention, and it is obvious for those skilled in the art to obtain other drawings without creative efforts.

FIG. 1 is a schematic block diagram of a circuit system of an apparatus for an FPGA loading method based on a ZYNQ chip according to the present invention;

FIG. 2 is a flow chart of the FPGA loading method based on the ZYNQ chip of the invention;

FIG. 3 is a flow chart of upper computer controlled loading of the ZYNQ chip-based FPGA loading method of the present invention;

FIG. 4 is a flow chart of FPGA update of the FPGA loading method based on the ZYNQ chip of the invention;

FIG. 5 is a flow chart of Flash updating of the ZYNQ chip-based FPGA loading method of the present invention.

Detailed Description

The technical solutions in the embodiments of the present invention will be clearly and completely described below with reference to the drawings in the embodiments of the present invention, and it is obvious that the described embodiments are only a part of the embodiments of the present invention, and not all of the embodiments. All other embodiments, which can be derived by a person skilled in the art from the embodiments given herein without making any creative effort, shall fall within the protection scope of the present invention.

In order to make the aforementioned objects, features and advantages of the present invention comprehensible, embodiments accompanied with figures are described in further detail below.

The FPGA loading method based on the ZYNQ chip is applied to equipment consisting of a ZYNQ system, a Flash memory and at least one FPGA, the equipment is connected with an upper computer, as shown in figure 1, the inside of the equipment comprises the ZYNQ system and a Field Programmable Gate Array (FPGA) to be loaded, a ZYNQ series combines a dual-core ARM Cortex-A9 processor and the FPGA, and is a brand-new heterogeneous platform, the ZYNQ is divided into a PL (programmable logic) end and a PS (processor system) end, the PS end is always started when the ZYNQ is started, then the PL end is configured, the processing system can run some complex software applications by the OS, and the PL end can customize needed operation or peripheral equipment; the upper computer is a computer capable of directly sending an operation command, is mainly used for controlling the loading of equipment, files needing to be loaded are firstly placed in the upper computer, the upper computer can send configuration files to the equipment, send configuration commands and the like, and can also monitor the state of the equipment, and the upper computer is communicated with the equipment through Ethernet; the DDR3 is an internal memory, and is used for storing operation data of the processor and data exchanged to the outside when the PS runs, for example, data received by the PS end is stored in the DDR3 first, and the data stored in the DDR3 disappears when power is lost; the Flash1 is used for storing the loaded data of the ZYNQ, the loaded data does not disappear after power failure, the data of the Flash1 can be read when the ZYNQ system is started, and the PS end and the PL end of the ZYNQ system are loaded; the FPGA loading channel is a high-speed data transmission channel, the bottom layer uses a DMA channel, and loading data stored by the DDR3 at the PS end can quickly enter configuration logic through the FPGA loading channel; the Flash loading channel is a slow channel, and the PS terminal transmits data through read-write configuration logic; the configuration logic is a section of code written by a PL terminal and is mainly used for generating an FPGA programming time sequence and a Flash2 reading and writing time sequence; the loading mode control refers to controlling a mode selection pin through a GPIO (general purpose input/output) of ZYNQ, and the FPGA acquires the level of the loading mode pin during loading initialization so as to determine the loading mode of the time, wherein the loading mode comprises two modes of directly configuring the FPGA by ZYNQ and configuring the FPGA by Flash 2; the Flash2 is used for storing configuration data of the FPGA, and both the ZYNQ system and the FPGA can read data of the Flash 2; the FPGA to be configured is mainly used for taking charge of logic operation and signal processing functions and is a main chip of a user;

the FPGA loading method based on the ZYNQ chip is shown in FIG. 2 and comprises the steps of power-on automatic loading during power-on starting and upper computer control loading after the start of a ZYNQ system is finished;

the process of the power-on automatic loading comprises the following steps: when the equipment is powered on and started, the ZYNQ system is started, the data of the Flash1 is read, the PS end and the PL end of the ZYNQ system are loaded, the loading mode of the FPGA is defaulted to be active loading, and at the moment, the FPGA actively reads files from the Flash2 and loads the files quickly; in this way, the FPGA loading is not influenced by the starting time of the ZYNQ system, the FPGA loading speed is high, and the equipment can work normally and quickly;

the process of controlling loading by the upper computer comprises the following steps: after the ZYNQ system runs, automatically running a control daemon, monitoring a network port and responding to an upper computer command; the upper computer establishes communication with a ZYNQ system by using modes of an internet port, a serial port and the like, and issues an FPGA code to be updated; the ZYNQ system receives data, stores the data in a DDR3 internal memory, verifies the data and feeds back a verification result to the upper computer; the ZYNQ system determines an equipment updating mode according to an instruction of an upper computer; the specific steps are shown in fig. 3, and include:

s1, broadcasting a searching device command by upper computer software;

s9, the device control daemon verifies the downloaded file, verifies the file type, if correct, determines the device updating mode according to the instruction requirement of the user, otherwise, replies an error response;

the device updating method in step S9 includes: updating only FPGA, updating only Flash2, FPGA and Flash 2;

the process of updating the FPGA comprises the following steps: data interaction is carried out on data and control of PS and PL through a high-speed FPGA updating channel; an application configuration program of the ZYNQ system initiates an FPGA updating operation according to a command of the upper computer; the PS firstly sends a control command loaded by the FPGA to the configuration logic and switches the loading mode of the FPGA into passive loading; after the switching is completed, the PS initiates an FPGA loading signal and waits for receiving an FPGA completion initialization signal; after receiving the initialization completion signal, the PS starts a DMA channel and transmits data to the configuration logic at a high speed; the configuration logic generates an FPGA loading time sequence according to the command of the PS, and rapidly completes FPGA loading; the specific steps are shown in fig. 4, and include:

b8, configuring an application program to report the operation result;

the process of updating Flash2 is as follows: the configuration application program of the ZYNQ system initiates Flash2 updating operation according to the command of the upper computer; the read-write operation speed of Flash2 is relatively slow, so PS and PL only need to configure channels through low-speed Flash 2; PS sends control and data to configuration logic, and the configuration logic writes Flash2 according to requirements; the specific steps are shown in fig. 5, and include:

c7, reading the Flash2 status register to judge whether the written file is correct or not, and reporting the operation result;

the FPGA and the Flash2 are updated, and specifically, the method comprises the following steps: according to the specific steps of updating the FPGA and the specific steps of updating the Flash2, the FPGA is updated first, and then the Flash2 is updated.

According to the FPGA loading method based on the ZYNQ chip, provided by the invention, the FPGA is directly and quickly loaded through Flash when the system is powered on, the system can conveniently communicate with an upper computer after the ZYNQ system runs, FPGA codes can be quickly updated through the FPGA high-speed configuration channels of PS and PL, the FPGA updating time is shortened to the maximum extent, and the interruption time of equipment is reduced; when the device works normally, the plug-in Flash is updated, and the work of the FPGA cannot be influenced by updating the Flash. According to the FPGA loading method based on the ZYNQ chip, the FPGA can quickly load files at any time through a scheme of combining active loading and passive loading of the FPGA, the FPGA and the Flash are respectively updated by using the controller, and the advantages of being least in FPGA updating time, shortest in equipment interruption working time and convenient in Flash data updating are achieved.

The principles and embodiments of the present invention have been described herein using specific examples, which are provided only to help understand the method and the core concept of the present invention; meanwhile, for a person skilled in the art, according to the idea of the present invention, the specific embodiments and the application range may be changed. In view of the above, the present disclosure should not be construed as limiting the invention.

Claims

1. A ZYNQ chip-based FPGA loading method is applied to equipment consisting of a ZYNQ system, a Flash memory and an FPGA, wherein the ZYNQ system is divided into a PL end and a PS end, the Flash memory comprises a Flash1 and a Flash2, the Flash1 is used for storing configuration data of the ZYNQ system, and the Flash2 is used for storing configuration data of the FPGA, and is characterized by comprising the following steps: the method comprises the steps of power-on automatic loading during power-on starting and upper computer controlled loading after a ZYNQ system is started;

the process of the power-on automatic loading comprises the following steps: when the equipment is powered on and started, the loading mode of the FPGA is defaulted to active loading, and at the moment, the FPGA actively reads files from Flash2 and loads the files quickly; the ZYNQ system reads the data of the Flash1 and loads a ZYNQ minimum system;

the specific steps of the upper computer for controlling loading comprise:

s1, broadcasting a searching device command by upper computer software;

2. The FPGA loading method based on ZYNQ chip as claimed in claim 1, wherein in the step S9 in the specific steps of upper computer control loading, the device control daemon verifies the downloaded file, verifies the file type, determines the device updating mode according to the instruction requirement of the user if the file type is correct, and otherwise replies an error response, wherein the device updating mode comprises: updating only the FPGA, updating only the Flash2, updating only the FPGA and updating only the Flash 2.

3. The ZYNQ chip-based FPGA loading method according to claim 2, wherein the specific step of updating the FPGA comprises:

b5, the configuration logic receives the init of the high level, and generates a time sequence which meets the FPGA configuration requirement to complete data loading;

and B8, configuring the application program to report the operation result.

4. The FPGA loading method based on ZYNQ chip as claimed in claim 2, wherein the specific step of updating Flash2 comprises:

5. The FPGA loading method based on the ZYNQ chip as claimed in claim 2, wherein the FPGA and the Flash2 are both updated, specifically: flash2 is updated after the FPGA is updated.