CN111274183A - Multi-path high-speed protocol interface dynamic reconfigurable system and implementation method - Google Patents
Multi-path high-speed protocol interface dynamic reconfigurable system and implementation method Download PDFInfo
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- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
- G06F13/38—Information transfer, e.g. on bus
- G06F13/40—Bus structure
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- G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
- G06F13/38—Information transfer, e.g. on bus
- G06F13/42—Bus transfer protocol, e.g. handshake; Synchronisation
Abstract
The invention provides a dynamic reconfigurable system of a multi-path high-speed protocol interface and an implementation method thereof, aiming at the situation that the common high-speed protocol interfaces in the fields of the current communication system, the radar system, the general computer system, the storage system and the like are not uniform enough, and mainly solving the problem that the same interface can be configured into a plurality of high-speed protocol interfaces. The system comprises a reconfiguration control module, a high-speed protocol interface dynamic reconfigurable module, a nonvolatile memory and a system host, wherein: the reconfiguration control module receives a remote or local reconfiguration command, reads a configuration file corresponding to the reconfiguration command and transmits the configuration file to the high-speed protocol interface dynamic reconfiguration module; the high-speed protocol interface dynamic reconfigurable module receives the configuration file sent by the reconfiguration control module, completes the reconfiguration work of the high-speed protocol interface dynamic reconfigurable module and reconfigures the protocol type of the high-speed protocol interface; a nonvolatile memory for caching important data of the intermediate state before reconstruction; and the system host is connected with the high-speed protocol interface dynamic reconfigurable module through a high-speed interface.
Description
Technical Field
The invention relates to a multi-path high-speed protocol interface dynamic reconfigurable system and an implementation method, belonging to the technical field of FPGA dynamic reconfigurable.
Background
With the development of scientific technology, the amount of data generated is increasing exponentially, and the use of high-speed interfaces is becoming more and more common. However, there are many standard high-speed interfaces on the market, and the main high-speed protocol interfaces adopted in various fields are not uniform enough, for example, the high-speed interface of the communication system commonly uses a network protocol, the high-speed interface of the radar system commonly uses an SRIO protocol, the high-speed interface of the general computer system commonly uses a PCIe protocol, and the high-speed interface of the mass storage device commonly uses a PCIe protocol and an NVMe protocol.
Disclosure of Invention
The invention provides a dynamic reconfigurable system of a multi-path high-speed protocol interface and an implementation method thereof, aiming at the situation that the common high-speed protocol interfaces in the fields of the current communication system, the radar system, the general computer system, the storage system and the like are not uniform enough.
In order to achieve the purpose, the invention is realized by the following technical scheme:
a multi-path high-speed protocol interface dynamic reconfigurable system comprises a reconfiguration control module, a high-speed protocol interface dynamic reconfigurable module, a nonvolatile memory and a system host, wherein:
the reconfiguration control module receives an external reconfiguration command, reads a configuration file corresponding to the reconfiguration command, and transmits the configuration file to the high-speed protocol interface dynamic reconfiguration module;
the high-speed protocol interface dynamic reconfigurable module receives the configuration file sent by the reconfiguration control module and completes the reconfiguration work of the high-speed protocol interface dynamic reconfigurable module;
a nonvolatile memory for caching important data of the intermediate state before reconstruction;
the system host is connected with the high-speed protocol interface dynamic reconfigurable module through a high-speed interface and is connected with the configuration file storage through a network so as to upgrade the local configuration file on line.
On the basis of the multi-path high-speed protocol interface dynamic reconfigurable system, the high-speed protocol interface dynamic reconfigurable module is an FPGA chip and comprises a high-speed protocol interface analysis module, a data processing module and a SelectMAP interface, the SelectMAP interface is connected with the reconfiguration control module, the data processing module realizes the data transmission and processing functions of the high-speed protocol interface dynamic reconfigurable module, and the high-speed protocol interface analysis module comprises an SRIO analysis module, a PCIe analysis module and an NVMe analysis module.
On the basis of the multi-path high-speed protocol interface dynamic reconfigurable system, the reconfiguration control module is an FPGA chip and comprises a configuration FSM module, a network analysis module, a reconfiguration instruction control module and a local serial port command analysis module, a system host inputs a reconfiguration instruction into the reconfiguration instruction control module, the reconfiguration instruction data is analyzed and output by the network analysis module, the reconfiguration instruction module performs instruction identification, corresponding reconfiguration work is completed according to a corresponding instruction, and the configuration FSM module writes a corresponding configuration file in a configuration file memory into the high-speed protocol interface dynamic reconfigurable module; the serial port command is output through the local serial port command analysis module to reconstruct a command, the command is specified to read a corresponding configuration file in the configuration file storage, and the command is transmitted to the high-speed protocol interface dynamic reconfigurable module through the SelectMAP interface.
A dynamic reconfigurable realization method for a multi-path high-speed protocol interface comprises the following steps:
s1, the board card is in a normal working state;
s2, waiting for receiving a local serial port control reconstruction instruction or a network signal reconstruction instruction of a system host;
s3, receiving a reconstruction command, and analyzing the reconstruction command by a reconstruction control module;
s4, sending a stop instruction to the high-speed protocol dynamic reconfigurable module, stopping the high-speed protocol dynamic reconfigurable module and packaging the current important data;
s5, caching the packed important data into a nonvolatile memory;
s6, confirming whether the data caching is finished, if so, executing the step S7, and if not, executing the step S5;
s7, the reconfiguration control module reads the configuration file and transmits the configuration file to the high-speed protocol dynamic reconfigurable module;
s8, confirming whether the reconstruction is finished or not, if so, executing the step S9, and if not, continuing to execute the step S7;
s9, reestablishing connection of the high-speed interface link;
s10, confirming whether the high-speed interface establishes connection or not;
s11. re-perform steps S1 through S10 if a connection is established, and perform step S9 if a connection is not established.
The invention has the advantages that: the invention can realize the dynamic reconfiguration of a plurality of high-speed protocol interfaces under different application scenes, effectively solves the problems of time-sharing multiplexing of the plurality of high-speed protocol interfaces, online upgrading of the versions of configuration files, real-time fault maintenance and the like, achieves the effect of one machine with multiple purposes, increases the flexibility of storage equipment, greatly reduces the resource expenditure of FPGA, and reduces the material cost of the equipment.
Drawings
The accompanying drawings, which are included to provide a further understanding of the invention and are incorporated in and constitute a part of this specification, illustrate embodiments of the invention and together with the description serve to explain the principles of the invention and not to limit the invention.
Fig. 1 is a schematic diagram of a multi-path high-speed protocol interface dynamic reconfigurable system of the invention.
Fig. 2 is a classification diagram of the FPGA reconfigurable technology.
FIG. 3 is a block diagram of an implementation of a slave select map configuration block.
FIG. 4 is a diagram of a configuration module implementation.
Fig. 5 is a block diagram of a remote control reconfiguration mode implementation.
FIG. 6 is a block diagram of a local control reconfiguration mode implementation.
Fig. 7 is a block diagram of an implementation method for dynamically reconfiguring multiple high-speed protocol interfaces.
Detailed Description
The technical solutions in the embodiments of the present invention will be clearly and completely described below with reference to the drawings in the embodiments of the present invention, and it is obvious that the described embodiments are only a part of the embodiments of the present invention, and not all of the embodiments. All other embodiments, which can be derived by a person skilled in the art from the embodiments given herein without making any creative effort, shall fall within the protection scope of the present invention.
Referring to fig. 1, a multi-path high-speed protocol interface dynamic reconfigurable system includes a reconfiguration control module, a high-speed protocol interface dynamic reconfigurable module, a nonvolatile memory and a system host, wherein:
the reconfiguration control module receives an external reconfiguration command, reads a configuration file corresponding to the reconfiguration command, transmits the configuration file to the high-speed protocol interface dynamic reconfigurable module to assist in completing reconfiguration work, and can upgrade the version of the configuration file on line;
the high-speed protocol interface dynamic reconfigurable module receives the configuration file sent by the reconfiguration control module and completes the reconfiguration work of the high-speed protocol interface dynamic reconfigurable module;
a nonvolatile memory for caching important data of the intermediate state before reconstruction;
the system host is connected with the high-speed protocol interface dynamic reconfigurable module through a high-speed interface and is connected with the configuration file storage through a network so as to upgrade the local configuration file on line.
In this embodiment, the reconfiguration control module and the high-speed protocol interface dynamic reconfiguration module are both implemented by an FPGA chip, and currently, an FPGA mainly has three programming processes: SRAM-based structures, Flash-based structures, and antifuse-based structures. The FPGA based on the SRAM structure writes configuration data into an on-chip Random Access Memory (RAM) when the FPGA is initialized and electrified, the FPGA can start to work normally after the initialization configuration of the FPGA is completed, but the configuration data stored in the on-chip RAM can be lost immediately after the FPGA is powered off. The FPGA based on the SRAM structure supports repeated programming, which is the basis for realizing a reconfigurable technology. The FPGA based on the SRAM structure supports repeated programming and has high erasing speed. Therefore, the FPGA reconfigurable technology provided by the invention is carried out on the FPGA based on the SRAM structure.
As shown in fig. 2, the reconfigurable technology of the FPGA is divided into static reconfiguration and dynamic reconfiguration, and the dynamic reconfiguration can be divided into dynamic global reconfiguration and dynamic local reconfiguration according to the difference of the reconfiguration areas. The main object required to be reconfigurable in the invention is a high-speed interface analysis module, the high-speed interface analysis module mainly comprises a physical layer, a link layer, a protocol layer and the like, and the physical layer uses a hardware structure high-speed serial controller (Transceiver) of an FPGA (field programmable gate array), and can only be dynamically configured and cannot be defined by software and cannot be dynamically reconfigured. The link layer and the protocol layer are defined by software, and dynamic reconfiguration can be realized. When the internal unit of the FPGA is arranged, the physical layer, the link layer and the protocol layer are closely adjacent, and the high-speed transmission of the high-speed protocol can be realized only through the shortest path, so that the local reconfigurable area is difficult to divide. The invention provides a software-defined global dynamic reconfigurable mode, namely configuration files respectively supporting various high-speed protocols are stored in a peripheral configuration file memory before reconfiguration, and after a reconfiguration command is received, a reconfiguration control module unloads the corresponding configuration files into a high-speed protocol dynamic reconfigurable module to complete the reconfiguration work of a high-speed storage interface.
TABLE 1 configuration Bandwidth of FPGA configuration modes
Table 1 shows configuration bandwidths of the FPGA configuration mode, and the same configuration file uses different configuration modes, so that configuration times are greatly different. The Slave SelectMAP configuration interface provides 8-bit, 16-bit and 32-bit bidirectional data bus interfaces, and can be used for configuring and reading back the FPGA. The configuration clock of the selectMAP is 100MHz at the fastest speed, if the data width selects 32 bits, the maximum bandwidth is 3.2Gb/s, the data compression function is supported, and the dynamic reconfiguration function of parallel configuration is supported, so the configuration mode of the Slave selectMAP is selected as the configuration mode of the reconfiguration FPGA.
The high-speed protocol interface dynamic reconfigurable module is an FPGA chip and comprises a high-speed protocol interface analysis module, a data processing module and a SelectMAP interface, the SelectMAP interface is connected with a reconfiguration control module, the data processing module realizes the data transmission and processing functions of the high-speed protocol interface dynamic reconfigurable module, the high-speed protocol interface analysis module comprises a SRIO analysis module, a PCIe analysis module, a NVMe analysis module and other high-speed protocol analysis modules, the problems of high-speed protocol time-sharing multiplexing such as SRIO, PCIe and NVMe, version online upgrading of configuration files, real-time fault maintenance and the like are effectively solved, the effect of one machine with multiple purposes is achieved, the flexibility of storage equipment is improved, the resource expenditure of the FPGA is greatly reduced, and the material cost of the storage equipment is reduced.
The reconfiguration control module comprises a configuration FSM module, a network analysis module, a reconfiguration instruction control module and a local serial port command analysis module, the system host inputs a reconfiguration instruction into the reconfiguration instruction control module, the reconfiguration instruction data is analyzed and output by the network analysis module, the reconfiguration instruction module performs instruction identification and completes corresponding reconfiguration work according to a corresponding instruction, and the configuration FSM module writes a corresponding configuration file in the configuration file memory into the high-speed protocol interface dynamic reconfiguration module; the serial port command outputs the reconstruction instruction number through the local serial port command analysis module, the corresponding configuration file in the configuration file reading memory is appointed to be read, and the reconstruction instruction number is transmitted to the high-speed protocol interface dynamic reconstruction module through the SelectMAP interface. Fig. 3 is a connection diagram of the reconfiguration control module performing power-on configuration and version update operations on the high-speed protocol dynamic reconfigurable module through a slave select map interface, where the high-speed protocol dynamic reconfigurable module is a slave device side and the configuration logic is completed by the reconfiguration control module. The specific implementation process is as follows: and the reconfiguration control module receives a local or remote reconfiguration instruction, reads the configuration file from the corresponding position of the configuration file memory, and configures the dynamic reconfigurable module through the slave electrospark MAP interface. The specific operation steps are shown in fig. 4.
The invention provides 2 reconstruction control modes which are divided into a local control mode and a remote control mode, wherein the remote reconstruction mode can also realize the online upgrade function of the version of the configuration file.
Fig. 5 is a block diagram illustrating an implementation of the remote control reconfiguration mode. The system host can realize remote reconstruction control of the reconstruction control module and online upgrade of the configuration file through a gigabit Ethernet interface. The system host sends a reconstruction command or a configuration file with an updated version to the reconstruction control module through the gigabit Ethernet, the reconstruction command data is output through the analysis of a network analysis command, namely an SGMII IP core, the reconstruction command data is identified through the reconstruction command control module, and the corresponding reconstruction work is completed according to the corresponding command. And when the command is a reconfiguration command, starting a configuration FSM module, writing a corresponding configuration file in the configuration file memory into the dynamic reconfigurable hardware acceleration controller, and reconfiguring the high-speed interface protocol. When the configuration file is of a new version, the configuration file is written into a corresponding address in a configuration file memory to replace the previous old version file. The method of remote control reconstruction mode can reconstruct high-speed interface protocol in real time, and can upgrade the version of configuration file on line, so that it is an effective method for implementing safety fault maintenance.
Fig. 6 is a block diagram illustrating an implementation of the local control reconfiguration mode. Under the condition that the system host does not have custom software and can remotely control the reconfiguration command, the reconfiguration of the high-speed interface can be realized by adopting a local control mode. The local operation can be completed through a serial port, the corresponding configuration file in the configuration file reading memory is appointed to be read through a serial port command, and the configuration file is transmitted to the reconfigurable high-speed protocol controller through the SelectMAP interface.
When global dynamic reconfiguration is carried out, a global bit stream configuration file of a specific high-speed interface is loaded into a dynamic reconfigurable hardware acceleration controller, all logics of FPGA logic resources before reconfiguration are erased, and therefore important data such as state indication and intermediate results of calculation need to be stored in a certain storage area before reconfiguration.
In summary, the reconfiguration control module of the present invention can receive a local serial port control reconfiguration instruction or a network signal reconfiguration instruction of the system host, and write the corresponding configuration file in the configuration file memory into the high-speed interface dynamic reconfigurable module, so as to implement the reconfigurable function of the high-speed interface. The system host can upgrade the local configuration file on line through the network port to realize the software version upgrading and fault maintenance functions. The state and the intermediate result before the reconfiguration are cached in the nonvolatile memory, so that the system can conveniently perform data backup of a plurality of reconfiguration tasks, and the system can conveniently perform redundancy upgrade.
Referring to fig. 7, a method for implementing dynamic reconfiguration of a multi-path high-speed protocol interface includes the following steps:
s1, the board card is in a normal working state;
s2, waiting for receiving a local serial port control reconstruction instruction or a network signal reconstruction instruction of a system host;
s3, receiving a reconstruction command, and analyzing the reconstruction command by a reconstruction control module;
s4, sending a stop instruction to the high-speed protocol dynamic reconfigurable module, stopping the high-speed protocol dynamic reconfigurable module and packaging the current important data;
s5, caching the packed important data into a nonvolatile memory;
s6, confirming whether the data caching is finished, if so, executing the step S7, and if not, executing the step S5;
s7, the reconfiguration control module reads the configuration file and transmits the configuration file to the high-speed protocol dynamic reconfigurable module;
s8, confirming whether the reconstruction is finished or not, if so, executing the step S9, and if not, continuing to execute the step S7;
s9, reestablishing connection of the high-speed interface link;
s10, confirming whether the high-speed interface establishes connection or not;
s11. re-perform steps S1 through S10 if a connection is established, and perform step S9 if a connection is not established.
Finally, it should be noted that: although the present invention has been described in detail with reference to the foregoing embodiments, it will be apparent to those skilled in the art that changes may be made in the embodiments and/or equivalents thereof without departing from the spirit and scope of the invention. Any modification, equivalent replacement, or improvement made within the spirit and principle of the present invention should be included in the protection scope of the present invention.
Claims (4)
1. A dynamic reconfigurable system of multi-path high-speed protocol interfaces is characterized in that: the system comprises a reconfiguration control module, a high-speed protocol interface dynamic reconfigurable module, a nonvolatile memory and a system host, wherein:
the reconfiguration control module receives an external reconfiguration command, reads a configuration file corresponding to the reconfiguration command, and transmits the configuration file to the high-speed protocol interface dynamic reconfiguration module;
the high-speed protocol interface dynamic reconfigurable module receives the configuration file sent by the reconfiguration control module, completes the reconfiguration work of the high-speed protocol interface dynamic reconfigurable module and reconfigures the protocol type of the high-speed protocol interface;
a nonvolatile memory for caching important data of the intermediate state before reconstruction;
the system host is connected with the high-speed protocol interface dynamic reconfigurable module through a high-speed interface and is connected with the configuration file storage through a network so as to upgrade the local configuration file on line.
2. The multi-path high-speed protocol interface dynamic reconfigurable system according to claim 1, characterized in that: the high-speed protocol interface dynamic reconfigurable module is an FPGA chip and comprises a high-speed protocol interface analysis module, a data processing module and a SelectMAP interface, the SelectMAP interface is connected with the reconfiguration control module, the data processing module realizes the data transmission and processing functions of the high-speed protocol interface dynamic reconfigurable module, and the high-speed protocol interface analysis module comprises an SRIO analysis module, a PCIe analysis module and an NVMe analysis module.
3. The multi-path high-speed protocol interface dynamic reconfigurable system according to claim 1, characterized in that: the reconfiguration control module is an FPGA chip and comprises a configuration FSM module, a network analysis module, a reconfiguration instruction control module and a local serial port command analysis module, the system host inputs a reconfiguration instruction into the reconfiguration instruction control module, the reconfiguration instruction data is analyzed by the network analysis module, the reconfiguration instruction module identifies the reconfiguration instruction and completes corresponding reconfiguration work according to a corresponding instruction, and the configuration FSM module writes a corresponding configuration file in the configuration file memory into the high-speed protocol interface dynamic reconfigurable module; the serial port command is output through the local serial port command analysis module to reconstruct a command, the command is specified to read a corresponding configuration file in the configuration file storage, and the command is transmitted to the high-speed protocol interface dynamic reconfigurable module through the SelectMAP interface.
4. A dynamic reconfigurable realization method of a multi-path high-speed protocol interface is characterized by comprising the following steps:
s1, the board card is in a normal working state;
s2, waiting for receiving a local serial port control reconstruction instruction or a network signal reconstruction instruction of a system host;
s3, receiving a reconstruction command, and analyzing the reconstruction command by a reconstruction control module;
s4, sending a stop instruction to the high-speed protocol dynamic reconfigurable module, stopping the high-speed protocol dynamic reconfigurable module and packaging the current important data;
s5, caching the packed important data into a nonvolatile memory;
s6, confirming whether the data caching is finished, if so, executing the step S7, and if not, executing the step S5;
s7, the reconfiguration control module reads the configuration file and transmits the configuration file to the high-speed protocol dynamic reconfigurable module;
s8, confirming whether the reconstruction is finished or not, if so, executing the step S9, and if not, continuing to execute the step S7;
s9, reestablishing connection of the high-speed interface link;
s10, confirming whether the high-speed interface establishes connection or not;
s11. re-perform steps S1 through S10 if a connection is established, and perform step S9 if a connection is not established.
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