CN112181891A

CN112181891A - NVMe (network video recorder) -based storage board card and data processing method

Info

Publication number: CN112181891A
Application number: CN202011144639.9A
Authority: CN
Inventors: 高维臣
Original assignee: Beijing Dadi Xinhe Information Technology Co ltd
Current assignee: Beijing Dadi Xinhe Information Technology Co ltd
Priority date: 2020-10-23
Filing date: 2020-10-23
Publication date: 2021-01-05
Anticipated expiration: 2040-10-23
Also published as: CN112181891B

Abstract

The invention provides a storage board card based on NVMe and a data processing method, and relates to the technical field of embedded systems, wherein the storage board card is provided with a processor module, an NVMe storage module and an FPGA module on a PCB circuit board; the FPGA module is connected with the processor module through a first PCIE signal line, and the processor module is connected with the NVMe storage module through a second PCIE signal line; the FPGA module is used for processing the received first data, and the NVMe storage module is used for storing and processing the received second or third data. According to the NVMe-based storage board card and the NVMe-based storage method, the processor module controls data storage, the FPGA module and the NVMe storage module respectively perform data processing or data storage, the parallel processing capacity of the FPGA module can be exerted, and the FPGA has a good performance power consumption ratio; the efficiency of data access can be improved, product quality and reliability have been improved.

Description

NVMe (network video recorder) -based storage board card and data processing method

Technical Field

The disclosure relates to the technical field of embedded systems, in particular to a storage board card based on NVMe and a data processing method.

Background

With the rapid development of integrated circuits, computer processing technologies and software technologies, the processing platform system architecture also develops and evolves rapidly. VPX is a new generation of high-speed serial bus standard developed by vta (VME International Trade Association ) organization on the basis of its VME bus in 2007. At present, the performance of the existing 6U VPX storage board card is low, the general read-write bandwidth is 2-3 GB/s, the requirements of high read-write speed and large storage capacity cannot be met, and various tasks such as radar signal analysis, data encryption and decryption and the like cannot be completed. Therefore, a storage board card is needed, which can meet the requirement of processing various tasks.

Disclosure of Invention

The present disclosure is proposed to solve the above technical problems. The embodiment of the disclosure provides a storage board card based on NVMe and a data processing method.

According to a first aspect of the embodiments of the present disclosure, there is provided an NVMe-based storage board card, including: a PCB circuit board; the PCB is provided with a processor module, a plurality of NVMe storage modules based on the NVMe standard and an FPGA module; the FPGA module is connected with the processor module through a first PCIE signal line, and the processor module is connected with the NVMe storage module through a second PCIE signal line; the FPGA module is used for processing the received first data to obtain second data and sending the second data to the processor module; the processor module is used for sending the second data and the storage instruction to the NVMe storage module, or generating third data according to the second data and sending the third data and the storage instruction to the NVMe storage module; sending a reading instruction to the NVMe storage module, and receiving fourth data returned by the NVMe storage module; the NVMe storage module is configured to perform storage processing on the received second data or the third data, or send the stored fourth data to the processor module.

Optionally, the processor module comprises a CPU chip unit; the CPU chip unit is connected with the first DDR memory unit; the PCB circuit board is provided with an XMC interface, a USB interface, an Ethernet interface, a VGA interface, an audio interface, a serial interface, a PCIE interface and an optical fiber interface; the CPU chip unit is connected with at least one interface of the XMC interface, the USB interface, the Ethernet interface, the VGA interface, the audio interface, the serial interface, the PCIE interface and the optical fiber interface.

Optionally, the FPGA module includes: the FPGA chip is connected with the second DDR memory module; a plurality of LVDS interfaces and a plurality of GTH interfaces are arranged on the PCB; the FPGA chip is respectively connected with the LVDS interface and the GTH interface.

Optionally, the FPGA chip is provided with a plurality of high-speed expansion card interfaces and a debug JTAG interface, wherein the FPGA chip receives a debug instruction and configuration information through the debug JTAG interface.

Optionally, the NVMe storage module comprises: the system comprises a PCIE interface, a controller unit, a distribution unit and a storage unit; the controller unit is connected with the second PCIE signal line through the PCIE interface; the distribution unit is respectively connected with the controller unit and the storage unit; wherein the number of the storage units is multiple.

Optionally, the method further comprises: a power supply unit; the power supply unit is arranged on the PCB; the processor module, the NVME storage module and the FPGA module are respectively connected with the power supply unit.

Optionally, the method further comprises: a plurality of status indicator lights; the multiple status indicator lamps are arranged on the PCB; the processor module, the NVME storage module and the FPGA module are respectively connected with corresponding status indicator lamps.

According to a second aspect of the embodiments of the present disclosure, there is provided a data processing method based on the NVMe-based storage board card, including: the method comprises the steps that a processor module receives a storage request and data to be stored sent by external equipment, generates first data based on the data to be stored, and sends the first data to an FPGA module through a first PCIE signal line; the FPGA module processes the first data to obtain second data and sends the second data to the processor module through the first PCIE signal line; the processor module generates third data based on the data to be stored and the second data, and sends the third data and a storage instruction to the NVMe storage module through a second PCIE signal line, or the processor module sends the second data and the storage instruction to the NVME storage module through a second PCIE signal line; the NVMe storage module performs storage processing on the received second data or the third data based on the received storage instruction.

Optionally, the processor module receives a read request sent by an external device, generates a read instruction based on the read request, and sends the read instruction to the NVMe storage module through a second PCIE signal line; the NVMe storage module sends stored fourth data to the processor module through a second PCIE signal line according to the reading instruction; the processor module generates the first data based on the fourth data and sends the first data to the FPGA module through a first PCIE signal line; the processor module receives the second data returned by the FPGA module through the first PCIE signal line, integrates the second data and the fourth data, and transmits the integrated data to external equipment.

Optionally, a virtual interface module, a virtual task distribution module and a virtual data processing module are arranged in the FPGA chip; the virtual interface module receives the first data and sends the first data to the virtual task distribution module; the virtual task distribution module sends the first data to a corresponding virtual data processing module; and the virtual data processing module processes the first data to obtain the second data and sends the second data to the processor module.

Optionally, a controller unit, a distribution unit and a storage unit are arranged in the NVMe storage mold; the controller unit receives the storage instruction and the second data or the third data sent by a second PCIE signal line; wherein, the storage instruction carries address information of a storage unit; the controller unit converts the storage instruction and the second data or the third data into a preset format and then sends the preset format to the distribution unit; and the distribution unit sends the storage instruction with a preset format and the second data or the third data to a corresponding storage unit according to the address information of the storage unit, so that the storage unit stores the second data or the third data.

Optionally, the controller unit receives the read instruction sent through a second PCIE signal line; the reading instruction carries address information of a storage unit; the controller unit sends the reading instruction to the distribution unit; the distribution unit sends the reading instruction to a corresponding storage unit according to the address information of the storage unit, so that the storage unit reads the fourth data and sends the fourth data to the distribution unit; wherein the fourth data has a preset format; the distribution unit transmits the fourth data to the controller unit.

Optionally, the processing of the first data by the FPGA module includes: compression or decompression processing, signal analysis processing, encoding or decoding processing.

Based on the storage board card based on the NVMe and the data processing method provided by the embodiment of the disclosure, the PCB is provided with a processor module, an NVMe storage module and an FPGA module, the FPGA module is connected with the processor module through a first PCIE signal line, and the processor module is connected with the NVMe storage module through a second PCIE signal line; the processor module controls data storage, the FPGA module and the NVMe storage module respectively perform data processing or storage, the parallel processing capability of the FPGA module can be exerted, and the FPGA has good performance power consumption ratio; the efficiency of data access can be improved, product quality and reliability have been improved.

The technical solution of the present disclosure is further described in detail by the accompanying drawings and examples.

Drawings

The above and other objects, features and advantages of the present disclosure will become more apparent by describing in more detail embodiments of the present disclosure with reference to the attached drawings. The accompanying drawings are included to provide a further understanding of the embodiments of the disclosure, and are incorporated in and constitute a part of this specification, illustrate embodiments of the disclosure and together with the description serve to explain the principles of the disclosure and not to limit the disclosure. In the drawings, like reference numbers generally represent like parts or steps.

Fig. 1 is a schematic block diagram of an embodiment of an NVMe-based storage board of the present disclosure;

fig. 2 is a schematic block diagram of another embodiment of an NVMe-based storage board of the present disclosure;

fig. 3A is a schematic diagram of a module layout of the NVMe-based storage board card of the present disclosure; fig. 3B is a schematic diagram of a storage board card based on NVMe of the present disclosure;

fig. 4 is a schematic diagram of a module arranged in an FPGA chip in an embodiment of the NVMe-based storage board of the present disclosure;

fig. 5 is a schematic diagram of modules arranged in an NVMe storage module in an embodiment of an NVMe-based storage board of the present disclosure;

FIG. 6 is a schematic diagram of the architecture of the upper computer software;

FIG. 7 is a schematic diagram of a PCIe driven architecture;

FIG. 8 is a flow chart diagram of one embodiment of a data processing method of the present disclosure;

fig. 9 is a flowchart of another embodiment of a data processing method of the present disclosure.

Detailed Description

Example embodiments according to the present disclosure will be described in detail below with reference to the accompanying drawings. It is to be understood that the described embodiments are merely a subset of the embodiments of the present disclosure and not all embodiments of the present disclosure, with the understanding that the present disclosure is not limited to the example embodiments described herein.

It should be noted that: the relative arrangement of the components and steps, the numerical expressions, and numerical values set forth in these embodiments do not limit the scope of the present disclosure unless specifically stated otherwise.

It will be understood by those of skill in the art that the terms "first," "second," and the like in the embodiments of the present disclosure are used merely to distinguish one element from another, and are not intended to imply any particular technical meaning, nor is the necessary logical order between them.

It is also understood that in embodiments of the present disclosure, "a plurality" may refer to two or more than two and "at least one" may refer to one, two or more than two.

It is also to be understood that any reference to any component, data, or structure in the embodiments of the disclosure, may be generally understood as one or more, unless explicitly defined otherwise or stated otherwise.

In addition, the term "and/or" in the present disclosure is only one kind of association relationship describing the associated object, and means that there may be three kinds of relationships, such as a and/or B, and may mean: a exists alone, A and B exist simultaneously, and B exists alone. In addition, the character "/" in the present disclosure generally indicates that the former and latter associated objects are in an "or" relationship.

It should also be understood that the description of the various embodiments of the present disclosure emphasizes the differences between the various embodiments, and the same or similar parts may be referred to each other, so that the descriptions thereof are omitted for brevity.

Meanwhile, it should be understood that the sizes of the respective portions shown in the drawings are not drawn in an actual proportional relationship for the convenience of description.

The following description of at least one exemplary embodiment is merely illustrative in nature and is in no way intended to limit the disclosure, its application, or uses.

Techniques, methods, and apparatus known to those of ordinary skill in the relevant art may not be discussed in detail but are intended to be part of the specification where appropriate.

It should be noted that: like reference numbers and letters refer to like items in the following figures, and thus, once an item is defined in one figure, further discussion thereof is not required in subsequent figures.

Embodiments of the present disclosure may be implemented in electronic devices such as terminal devices, computer systems, servers, etc., which are operational with numerous other general purpose or special purpose computing system environments or configurations. Examples of well known terminal devices, computing systems, environments, and/or configurations that may be suitable for use with an electronic device, such as a terminal device, computer system, or server, include, but are not limited to: personal computer systems, server computer systems, thin clients, thick clients, hand-held or laptop devices, microprocessor-based systems, set-top boxes, programmable consumer electronics, network pcs, minicomputer systems, mainframe computer systems, distributed cloud computing environments that include any of the above, and the like.

As shown in fig. 1, the present disclosure provides an NVMe-based storage board card, including a PCB circuit board 11; a processor module 12, a plurality of NVMe memory modules 14 based on NVMe standards, and an FPGA (Field Programmable Gate Array) module 13 are disposed on the PCB circuit board 11. The NVMe (non-volatile cache memory express) standard is a storage controller interface standard developed for enterprises and common client systems using PCIe solid-state storage devices. PCIe modules based on the NVMe standard can be called NVMe storage modules, and the NVMe storage modules have the characteristics of low energy consumption and high performance.

The FPGA module 13 is connected to the processor module 12 through a first PCIE (Peripheral Component Interconnect Express) signal line, and the processor module 12 is connected to the NVMe storage module 14 through a second PCIE signal line. The FPGA module 13 processes the received first data to obtain second data and sends the second data to the processor module 13. The first data and the second data may be image data, radar signal data, data that needs to be encrypted and decrypted, and the like. The external device can be various terminals, boards and the like positioned outside the storage board card. The first data may be sent to the FPGA module 13 by the processor module 12 or an external device.

The processor module 12 sends the second data and the storage instruction to the NVMe storage module 14, or generates third data according to the second data and sends the third data and the storage instruction to the NVMe storage module 14. The processor module 12 sends a read instruction to the NVMe storage module 14 and receives fourth data returned by the NVMe storage module 14. The NVMe storage module 14 performs storage processing on the received second data or third data, or transmits the stored fourth data to the processor module 12. The third data and the fourth data may include image data, radar signal data, data that needs to be encrypted and decrypted, and the like.

In one embodiment, the processor module 12 includes a CPU (Central Processing Unit) chip Unit, and the CPU chip Unit is connected to the first DDR memory Unit. The PCB 11 is provided with a plurality of interfaces such as an XMC interface, a USB interface, an Ethernet interface, a VGA interface, an audio interface, a serial interface, a PCIE interface and an optical fiber interface, and the CPU chip unit is connected with at least one interface of the XMC interface, the USB interface, the Ethernet interface, the VGA interface, the audio interface, the serial interface, the PCIE interface and the optical fiber interface.

The FPGA module 13 includes an FPGA chip conforming to the UltraScale architecture and a second DDR memory module, and the FPGA chip is connected to the second DDR memory module. The PCB 11 is provided with a plurality of LVDS interfaces and a plurality of GTH interfaces, and the FPGA chip is respectively connected with the LVDS interfaces and the GTH interfaces. The FPGA chip is provided with a plurality of high-speed expansion card interfaces and a debugging JTAG interface, and receives debugging instructions and configuration information through the debugging JTAG interface.

In one embodiment, the storage board card based on the NVMe is provided with a plurality of status indicator lamps and a power supply unit, the plurality of status indicator lamps and the power supply unit 16 are arranged on the PCB circuit board 11, the processor module 12, the NVMe storage module 14 and the FPGA module 13 are respectively connected with the corresponding status indicator lamps, and the NVMe storage module 14 and the FPGA module 13 are respectively connected with the power supply unit 16.

In one embodiment, as shown in fig. 2, the NVMe-based storage board of the present disclosure may be a 6U VPX integrated GPU board, the board complying with the VITA65 specification. The NVMe-based storage board card integrates an FPGA chip conforming to a Xilinx UltraScale architecture, integrates an Intel Xeon D-1500 series server-level CPU and an onboard NVME storage module, has the capacity of 1T-10TB and the like, and continuously records the speed of more than 4.5GB/s (the capacity of more than 4 TB).

As shown in fig. 3A and 3B, the NVMe-based storage board is a 6U OpenVPX-compliant board, the processor module 12 includes Intel Xeon D-1500 series CPU chips, and the first DDR memory unit includes a 32GB DDR4 memory. The memory card adopts NVME (M.2) memory modules with 5 blocks of X4 PCIE interfaces, the memory capacity of each NVME memory module is 2TB, and the maximum memory capacity of 10TB can be realized.

The main technical parameters of the NVME M.2 storage module are as follows: an X4 PCIE 3.0 interface; supports NVME 1.1 specification; maximum storage capacity 2 TB; maximum write rate 1500 MB/s; maximum read rate 2500 MB/s; through the application of the NVME interface specification, the storage performance is greatly improved.

The NVMe-based storage board card comprises a plurality of front panel interfaces, including 1 RJ45 gigabit network port, 2 USB2.0/3.0 interfaces, 1 display interface, 1x SFP + tera network optical port, reset keys and the like. The NVMe-based storage board card comprises a VPX interface: 1x 8PCIe Gen3@ P2, 1 way gigabit Ethernet (1000Base-T) @ P4, 2x RS422@ P4, 8x GTX/GTH @ P5, 16x LVDS @ P4. Other parameters of the NVMe-based storage board card include: main power supply: + 12V; typical power consumption: < 100W; can be provided at normal temperature (0-55 ℃); a wide temperature (-40-70 ℃) version; relative humidity 0-95%; the heat dissipation mode is as follows: air cooling and cold guiding.

The NVMe-based storage board card can provide 1 group of X8 PCIe interfaces externally, a user can conveniently build a high-performance embedded computing system (HPEC), and the NVMe-based storage board card is suitable for carrying out various processing such as signal processing, video compression/decompression, image enhancement, encoding, decoding and cryptanalysis when data are stored and read.

The CPU chip of the processor module 12 employs an Intel Xeon D-1539 processor, and the parameters of the Intel Xeon D-1539 processor include: 8 cores, 1.6GHz main frequency and 2.1GHz Rui frequency; 12MB Cache; the maximum power consumption is 35W; 32GB DDR4 ECC memory; an integrated chipset; 1 path of SFP + ten-gigabit network port; 24XPCIe 3.0, 8X PCIe 2.0 interface; 2-way USB 2.0; 2-path SATA 3.0; and the operating systems such as Windows7/8, Linux and the like are supported. The Intel Xeon D-1500 processor provides 24 sets of PCIE 3.0 interfaces and 8 sets of PCIE 2.0 interfaces for the outside, and respectively expands the Xilinx FPGA, the NVME storage module or the GPU module.

In one embodiment, the FPGA chip is a Xilinx FPGA chip. The Xilinx UltraScale + FPGA series comprises

UltraScale + FPGA and

UltraScale + FPGA and 3D IC series. The main innovations of the UltraScale architecture include: the new generation of 90% utilization oriented routing methods, enhanced high speed memory cascades like ASIC clocks and logic infrastructure help to eliminate bottlenecks in DSP and packet processing; the enhanced DSP Slice integrates a 27x 18 bit multiplier and two adders, so that the performance and efficiency of fixed-point and IEEE Std 754 floating-point operation can be remarkably improved; the new generation of security application is realized by advanced methods such as AES bit stream decryption and authentication, key fuzzy processing, security equipment programming and the like; DDR4 supports a mass storage interface bandwidth of up to 2,666 Mb/s; the UltraRAM provides a large-capacity on-chip memory and supports SRAM device integration; the performance power consumption ratio advantage can be further improved by 20% to 30% by the innovative IP interconnection optimization technology; the MPSoC technology combines a software engine and a hardware engine, and supports real-time control, graphic and video processing, waveform and data packet processing, multi-level security, safety, reliability and the like.

In the FPGA chip of the UltraScale series, a GC (Global clock) pin replaces SRCC and MRCC. The clock regions of the FPGA chips of the UltraScale series are 6x6, namely 36, and if the FPGA chips of the UltraScale series are 7 series, the clock regions of the FPGA chips of the UltraScale series are 2x6, namely 12. The FPGA chip of the UltraScale series does not contain a clock buffer, and the function of the FPGA chip is replaced by the newly added BUFGCE _ DIV.

The FPGA chip of the FPGA module 13 adopts an FPGA chip based on Xilinx UltraScale Kintex series, the model is XCKU060-FFVA1156-2-I, PCIE Gen 3X 8 is supported, two groups of 64-bitDDR4 are provided, the capacity of each group is 4Gbyte, the FPGA chip can stably operate at 2400MT/s, an 8X GTH high-speed interface is provided for the outside, and 16 pairs of LVDS interfaces are provided. The board card has the characteristics of automatically controlling the power-on sequence, quickly loading programs in a BPI mode, supporting two system clock access modes of an on-board system and an off-board system and the like.

The main technical parameters of the FPGA chip XCKU060 are as follows: two clusters of DDR4 are externally hung, the data bit width is 64-bit, each group has the capacity of 4GByte, and the stable operation can be carried out at 2400 MT/s; a BPI x16 Nor Flash with the capacity of 1Gb is externally hung and used for storing a system configuration program; a QSPI x4 Nor Flash is externally hung, the capacity is 512Mb, and the QSPI x4 Nor Flash can be used for storing parameters; the loading mode is a BPI mode; two external QSFP + circuits support 40Gbps transmission rate; the PCIE network interface supports a PCIE Gen3 x8 mode, and the transmission rate can reach 5000 Mbyte/s; providing 16 pairs of LVDS interfaces externally; an 8X GTH interface is provided externally, and the transmission rate can reach 13.6Gbps and the like.

In one embodiment, the internal logic of the FPGA chip is divided into a fixed area and a reconfigurable area, the reconfigurable area can realize the reconfiguration of various algorithms, and different algorithm programs can be downloaded to the reconfigurable area through the fixed area to realize different algorithms. As shown in fig. 4, the FPGA chip is provided with a virtual interface module 131, a virtual task distribution module 132, and a virtual data processing module 133. The virtual interface module 131 receives the first data or the data sent by the external device, and sends the first data or the data sent by the external device to the virtual task distributing module 132. The virtual task distributing module 132 transmits the first data or the external device to the corresponding virtual data processing module 133. The virtual data processing module 133 processes the first data or the data sent by the external device, obtains the second data, and sends the second data to the processor module 12.

In one embodiment, NVMe is a high performance, scalable host controller interface for PCIe-based solid state drives. A notable feature of NVMe is the provision of multiple queues to process I/O commands. A single NVMe device supports up to 64K I/O queues, each of which can manage up to 64K commands. When the host issues an I/O command, the host system places the command on the commit queue (SQ) and then notifies the NVMe device using the doorbell register (DB). After the NVMe device has finished processing the I/O command, the device writes the processing result to a Completion Queue (CQ) and causes an interrupt to notify the host system. NVMe uses MSI/MSI-X and interrupt aggregation to improve the performance of interrupt handling.

The NVMe driver is a C-function library that can be linked directly to the application to provide direct, zero-copy data transfer between the application and the NVMe solid state drive. The set of library functions directly controls the NVMe device by mapping PCI BAR registers directly into local processes and then performing memory map based I/o (mmio). NVM Express (NVMe) is a register level interface that allows in-band host software to communicate with the NVM subsystem. An NVMe management interface (NVMe-MI) allows the management controller to communicate out-of-band with the NVMe NVM subsystem through one or more external interfaces.

NVMe is a protocol for communication between Host and SSD. NVMe-MI utilizes Management Component Transport Protocol (MCTP) as a command transport and utilizes the existing MCTP SMBus/I2C and PCIe bonded physical layer. NVMe has three key queues: submission Queue (SQ), Completion Queue (CQ) and Doorbell Register (DB). SQ and CQ are located in the memory of Host, and DB is located inside the controller of SSD. SQ and CQ are in Host's memory and DB is on the SSD side, NVMe Subsystem is typically SSD. The SQ is located in a Host memory, when the Host needs to send a command, the prepared command is firstly placed in the SQ, and then the SSD is informed to fetch the command; CQ is also located in Host memory, SSD will write command completion status to CQ.

In one embodiment, the NVMe storage module may be implemented in a variety of ways. For example, as shown in fig. 5, the NVMe storage module includes: PCIE interface, controller unit 141, distribution unit 142, and storage unit 143. The controller unit 141 is connected to the second PCIE signal line and the processor module 12 through the PCIE interface; the distribution unit 142 is connected to the controller unit 141 and the storage unit 143, respectively; the controller unit 141, the distribution unit 142 and the storage unit 143 may have various implementations. The number of the storage units 143 is plural, and may be implemented as a Solid State Disk (SSD) or the like.

In one embodiment, the storage performance test can be performed on the NVMe-based storage board card by using IOmeter test software, and the test result is recorded. According to the test results, the maximum reading speed of the memory card on the 6U backboard can reach 3846.01MBPS, and the maximum writing speed can reach 2238.12 MBPS. By using NVME and VROC technologies, the performance of data recording of the NVMe-based storage board card can be 6000MB/s (RAID0, the storage capacity is more than 4 TB).

In one embodiment, a performance test of a gigabit network interface is performed, a gigabit network optical fiber direct connection test environment of two NVMe-based storage board cards is established, and a professional local area network speed measurement tool software charIOT is adopted to perform the performance test of the gigabit network interface. charIOT adopts an End to End method to test the performance of network equipment or a network system in a real environment by generating simulated real traffic. Installing and running an Endpoint program of charIOT on two machines needing to be tested, and installing a console program of charIOT on the other machine, wherein the test result is as follows: an unoptimized interface is used for testing a TCP (transmission control protocol), and the throughput performance is 3964 Mbps; the optimized interface is used for testing the TCP protocol, and the throughput performance is 5923 Mbps.

In one embodiment, for the upper computer software of the NVMe-based storage board card disclosed by the present disclosure, Linux-based development is mainly implemented to implement device self-check, network communication, record playback management, file management, WEB interface, and the like. The NVMe-based storage board card provides highly available storage services to users using a network interface. A user can use a browser to configure various services of the NVMe-based storage board card through a WEB page, and the state of the NVMe-based storage board card can be inquired in real time.

As shown in fig. 6, the software architecture of the upper computer software mainly includes a Web front-end and a Web back-end, a service component, and an equipment layer. The Web front-end and back-end services comprise the display of front-end pages, the interaction with users and the management of back-end Web data. The associated business functions may be implemented via the middleware interface upon receipt of an operation associated with the recorder. Meanwhile, complex page management functions are realized through MySQL. The service layer mainly realizes specific service functions of file management, equipment management, unloading control, excitation and the like.

The device layer processes transmission of data and instructions between the upper computer and the lower computer (NVMe-based storage board card), and mainly calls related functions to interact with hardware and interface devices such as a memory, an optical fiber card, a gigabit network and a hard disk, and the main functions comprise hard disk reading and writing, PCIe driving, memory space management and network data receiving and transmitting. The function request of the user is packaged into an instruction through the network and sent to the PCIe recording card for managing and controlling the recording card. Meanwhile, for a large amount of file data, the data is transmitted to the PCIe unloading card through PCIe, and the unloading card transmits the data to the recording card through the optical port, so that the performance maximization is achieved. The system function aspect calls the system Shell to realize the system related functions, which comprises the following steps: restart/shut down.

In one embodiment, the architecture of the PCIe driver is as shown in FIG. 7. The upper computer is mainly provided with two channels for communicating with the FPGA. The data access mainly transmits a large amount of data through DMA (direct memory access) to realize high-performance data transmission; the command channel is used for transmitting data such as single control commands or configuration parameters. Through the two data channels, the upper computer and the lower computer can avoid packaging and analyzing protocol frames through protocols, and performance optimization can be maximized.

Fig. 8 is a flowchart of an embodiment of a data processing method according to the present disclosure, where the data processing method is applied to the NVMe-based storage board in the above embodiment, as shown in fig. 8:

s801, the processor module receives a storage request and data to be stored sent by external equipment, generates first data based on the data to be stored, and sends the first data to the FPGA module through a first PCIE signal line. For example, the data to be stored is 3D point cloud signals and peripheral image data.

S802, the FPGA module processes the first data to obtain second data and sends the second data to the processor module through the first PCIE signal line. The processing of the first data by the FPGA module comprises compression or decompression processing, signal analysis processing, encoding or decoding processing and the like. For example, the first data is a 3D point cloud signal, and the second data is an analysis result of the FPGA module on the 3D point cloud signal.

And S803, the processor module generates third data based on the data to be stored and the second data, and sends the third data and the storage instruction to the NVME storage module through the second PCIE signal line, or the processor module sends the second data and the storage instruction to the NVME storage module through the second PCIE signal line. For example, the third data is 3D scene image data generated by the processor module based on the peripheral image data and the analysis result of the 3D point cloud signal.

S804, the NVMe storage module performs storage processing on the received second data or third data based on the received storage instruction. For example, the NVMe storage module may store the analysis result of the 3D point cloud signal, or 3D scene image data, or the like.

Fig. 9 is a flowchart of another embodiment of the data processing method of the present disclosure, where the data processing method is applied to the NVMe-based storage board in the above embodiment, as shown in fig. 9:

s901, the processor module receives a reading request sent by an external device, generates a reading instruction based on the reading request, and sends the reading instruction to the NVMe storage module through a second PCIE signal line. For example, the external device sends a read request to obtain the stored user information data.

And S902, the NVMe storage module sends the stored fourth data to the processor module through the second PCIE signal line according to the reading instruction.

And S903, the processor module generates first data based on the fourth data, and sends the first data to the FPGA module through the first PCIE signal line. For example, the fourth data is user information data, the user information data includes information such as name, telephone, identification card, and the like, and if the identification card information needs to hide several digits therein, the identification card data (first data) is generated based on the user information data.

And S904, the processor module receives second data returned by the FPGA module through the first PCIE signal line, integrates the second data and the fourth data, and transmits the integrated data to external equipment.

For example, the FPGA module processes the identification card data (first data) to generate identification card desensitization information (second data) with several digits hidden therein; the processor module integrates the identification card desensitization information (second data) and the user information data and transmits the integrated data to the external equipment.

In one embodiment, a virtual interface module, a virtual task distribution module and a virtual data processing module are arranged in the FPGA chip. The virtual interface module receives the first data and sends the first data to the virtual task distribution module. The virtual task distribution module sends the first data to the corresponding virtual data processing module, and the virtual data processing module processes the first data to obtain second data and sends the second data to the processor module.

In one embodiment, a controller unit, a dispensing unit, and a storage unit are disposed within the NVMe storage die. The controller unit receives a storage instruction and second data or third data sent by the second PCIE signal line, where the storage instruction carries address information of the storage unit.

The controller unit extracts address information of the storage unit carried in the storage instruction, converts the storage instruction and the second data or the third data into a preset format and then sends the preset format and the preset format to the distribution unit; the preset format is a plurality of formats preset by the system and used for converting the second data or the third data into a uniform format. The distribution unit sends a storage instruction with a preset format and the second data or the third data to the corresponding storage unit according to the address information of the storage unit, and the storage unit stores the second data or the third data.

And the controller unit receives a reading instruction sent by the second PCIE signal line, wherein the reading instruction carries address information of the storage unit and data information required to be acquired. The controller unit sends the reading instruction to the distribution unit, the distribution unit extracts address information of the storage unit carried in the instruction, and the reading instruction is sent to the corresponding storage unit according to the address information of the storage unit. The storage unit reads fourth data and sends the fourth data to the distribution unit, and the fourth data have a preset format. The distribution unit sends the fourth data to the controller unit, and the controller unit may convert the fourth data into a format specified by the external device and send the converted fourth data to the external device.

The foregoing describes the general principles of the present disclosure in conjunction with specific embodiments, however, it is noted that the advantages, effects, etc. mentioned in the present disclosure are merely examples and are not limiting, and they should not be considered essential to the various embodiments of the present disclosure. Furthermore, the foregoing disclosure of specific details is for the purpose of illustration and description and is not intended to be limiting, since the disclosure is not intended to be limited to the specific details so described.

In the storage board card based on NVMe and the data processing method in the above embodiments, the PCB is provided with the processor module, the NVMe storage module, and the FPGA module, the FPGA module is connected to the processor module through the first PCIE signal line, and the processor module is connected to the NVMe storage module through the second PCIE signal line; the processor module controls data storage, the FPGA module and the NVMe storage module respectively perform data processing or storage, the parallel processing capability of the FPGA module can be exerted, and the FPGA has good performance power consumption ratio; the efficiency of data access can be improved, product quality and reliability have been improved.

The methods and apparatus of the present disclosure may be implemented in a number of ways. For example, the methods and apparatus of the present disclosure may be implemented by software, hardware, firmware, or any combination of software, hardware, and firmware. The above-described order for the steps of the method is for illustration only, and the steps of the method of the present disclosure are not limited to the order specifically described above unless specifically stated otherwise. Further, in some embodiments, the present disclosure may also be embodied as programs recorded in a recording medium, the programs including machine-readable instructions for implementing the methods according to the present disclosure. Thus, the present disclosure also covers a recording medium storing a program for executing the method according to the present disclosure.

It is also noted that in the devices, apparatuses, and methods of the present disclosure, each component or step can be decomposed and/or recombined. These decompositions and/or recombinations are to be considered equivalents of the present disclosure.

The previous description of the disclosed aspects is provided to enable any person skilled in the art to make or use the present disclosure. Various modifications to these aspects, and the like, will be readily apparent to those skilled in the art, and the generic principles defined herein may be applied to other aspects without departing from the scope of the disclosure. Thus, the present disclosure is not intended to be limited to the aspects shown herein but is to be accorded the widest scope consistent with the principles and novel features disclosed herein.

The foregoing description has been presented for purposes of illustration and description. Furthermore, the description is not intended to limit embodiments of the disclosure to the form disclosed herein. While a number of example aspects and embodiments have been discussed above, those of skill in the art will recognize certain variations, modifications, alterations, additions and sub-combinations thereof.

Claims

1. An NVMe-based storage board card, comprising:

a PCB circuit board; the PCB is provided with a processor module, a plurality of NVMe storage modules based on the NVMe standard and an FPGA module; the FPGA module is connected with the processor module through a first PCIE signal line, and the processor module is connected with the NVMe storage module through a second PCIE signal line;

the FPGA module is used for processing the received first data to obtain second data and sending the second data to the processor module;

the processor module is used for sending the second data and the storage instruction to the NVMe storage module, or generating third data according to the second data and sending the third data and the storage instruction to the NVMe storage module; sending a reading instruction to the NVMe storage module, and receiving fourth data returned by the NVMe storage module;

the NVMe storage module is configured to perform storage processing on the received second data or the third data, or send the stored fourth data to the processor module.

2. The memory card of claim 1,

the processor module comprises a CPU chip unit; the CPU chip unit is connected with the first DDR memory unit; the PCB circuit board is provided with an XMC interface, a USB interface, an Ethernet interface, a VGA interface, an audio interface, a serial interface, a PCIE interface and an optical fiber interface; the CPU chip unit is connected with at least one interface of the XMC interface, the USB interface, the Ethernet interface, the VGA interface, the audio interface, the serial interface, the PCIE interface and the optical fiber interface.

3. The memory card of claim 2,

the FPGA module comprises: the FPGA chip is connected with the second DDR memory module; a plurality of LVDS interfaces and a plurality of GTH interfaces are arranged on the PCB; the FPGA chip is respectively connected with the LVDS interface and the GTH interface.

4. The memory card of claim 3,

the FPGA chip is provided with a plurality of high-speed expansion card interfaces and a debugging JTAG interface, wherein the FPGA chip receives debugging instructions and configuration information through the debugging JTAG interface.

5. A storage board card as claimed in claim 3, wherein the NVMe storage module comprises: the system comprises a PCIE interface, a controller unit, a distribution unit and a storage unit; the controller unit is connected with the second PCIE signal line through the PCIE interface; the distribution unit is respectively connected with the controller unit and the storage unit; wherein the number of the storage units is multiple.

6. The storage card of claim 1, further comprising:

a power supply unit; the power supply unit is arranged on the PCB; the processor module, the NVME storage module and the FPGA module are respectively connected with the power supply unit.

7. The storage card of claim 1, further comprising:

a plurality of status indicator lights; the multiple status indicator lamps are arranged on the PCB; the processor module, the NVME storage module and the FPGA module are respectively connected with corresponding status indicator lamps.

8. A data processing method based on the NVMe-based storage board card of any one of claims 1-7, comprising:

the method comprises the steps that a processor module receives a storage request and data to be stored sent by external equipment, generates first data based on the data to be stored, and sends the first data to an FPGA module through a first PCIE signal line;

the FPGA module processes the first data to obtain second data and sends the second data to the processor module through the first PCIE signal line;

the processor module generates third data based on the data to be stored and the second data, and sends the third data and a storage instruction to the NVMe storage module through a second PCIE signal line, or the processor module sends the second data and the storage instruction to the NVME storage module through a second PCIE signal line;

the NVMe storage module performs storage processing on the received second data or the third data based on the received storage instruction.

9. The method of claim 8, further comprising:

the processor module receives a reading request sent by external equipment, generates a reading instruction based on the reading request, and sends the reading instruction to the NVMe storage module through a second PCIE signal line;

the NVMe storage module sends stored fourth data to the processor module through a second PCIE signal line according to the reading instruction;

the processor module generates the first data based on the fourth data and sends the first data to the FPGA module through a first PCIE signal line;

the processor module receives the second data returned by the FPGA module through the first PCIE signal line, integrates the second data and the fourth data, and transmits the integrated data to external equipment.

10. The method of claim 9, further comprising:

a virtual interface module, a virtual task distribution module and a virtual data processing module are arranged in the FPGA chip;

the virtual interface module receives the first data and sends the first data to the virtual task distribution module;

the virtual task distribution module sends the first data to a corresponding virtual data processing module;

and the virtual data processing module processes the first data to obtain the second data and sends the second data to the processor module.