CN112291237A - Reconfigurable symmetric encryption method for realizing software definition based on domestic FPGA - Google Patents
Reconfigurable symmetric encryption method for realizing software definition based on domestic FPGA Download PDFInfo
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- CN112291237A CN112291237A CN202011173773.1A CN202011173773A CN112291237A CN 112291237 A CN112291237 A CN 112291237A CN 202011173773 A CN202011173773 A CN 202011173773A CN 112291237 A CN112291237 A CN 112291237A
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- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
- H04L63/00—Network architectures or network communication protocols for network security
- H04L63/04—Network architectures or network communication protocols for network security for providing a confidential data exchange among entities communicating through data packet networks
- H04L63/0428—Network architectures or network communication protocols for network security for providing a confidential data exchange among entities communicating through data packet networks wherein the data content is protected, e.g. by encrypting or encapsulating the payload
- H04L63/0435—Network architectures or network communication protocols for network security for providing a confidential data exchange among entities communicating through data packet networks wherein the data content is protected, e.g. by encrypting or encapsulating the payload wherein the sending and receiving network entities apply symmetric encryption, i.e. same key used for encryption and decryption
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F15/00—Digital computers in general; Data processing equipment in general
- G06F15/76—Architectures of general purpose stored program computers
- G06F15/78—Architectures of general purpose stored program computers comprising a single central processing unit
- G06F15/7867—Architectures of general purpose stored program computers comprising a single central processing unit with reconfigurable architecture
- G06F15/7871—Reconfiguration support, e.g. configuration loading, configuration switching, or hardware OS
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F15/00—Digital computers in general; Data processing equipment in general
- G06F15/76—Architectures of general purpose stored program computers
- G06F15/78—Architectures of general purpose stored program computers comprising a single central processing unit
- G06F15/7867—Architectures of general purpose stored program computers comprising a single central processing unit with reconfigurable architecture
- G06F15/7885—Runtime interface, e.g. data exchange, runtime control
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- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
- H04L67/00—Network arrangements or protocols for supporting network services or applications
- H04L67/01—Protocols
- H04L67/06—Protocols specially adapted for file transfer, e.g. file transfer protocol [FTP]
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- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
- H04L67/00—Network arrangements or protocols for supporting network services or applications
- H04L67/2866—Architectures; Arrangements
- H04L67/30—Profiles
Abstract
The invention designs a reconfigurable symmetrical encryption method for realizing software definition based on a domestic FPGA. The software-defined reconfigurable data symmetric encryption structure drives and controls hardware resources through self-defined software in a system host, different cryptographic algorithms can be selected to complete dynamic reconfiguration to encrypt and decrypt data in real-time operation according to a control command sent by the system host, and the system host is connected with a reconfiguration controller and can complete updating of the cryptographic algorithm configuration file through transmitting the cryptographic algorithm configuration file through Ethernet. The technology completely meets the requirements of definable requirement, reconfigurable hardware, reconfigurable software and reconfigurable function in software definition.
Description
Technical Field
The invention relates to the field of encryption, in particular to a reconfigurable symmetric encryption method for realizing software definition based on a domestic FPGA (field programmable gate array).
Background
The research of the FPGA reconfigurable technology starts late, but some remarkable achievements are achieved in recent years after more and more colleges and scientific research institutions are added into the research queue of the FPGA reconfigurable technology. Wu Wenbo, the university of electronic technology in 2016, proposes a design scheme of a radar timer system based on an FPGA local dynamic reconfigurable technology, and the design scheme fully applies the design idea of a local reconfigurable method on the existing logic level of the radar timer and uses the local dynamic reconfigurable technology to realize reconstruction of the radar timer. The signal generated by the radar timer becomes a programmable signal by using the FPGA reconfigurable technology, and the flexibility is great. The Baoshuang of the university of Beijing industry in 2017 applies the FPGA reconfigurable technology to the field of industrial controllers. The industrial controller communicates with various control devices by using a field bus, however, with the development of the industrial field bus, the types of communication protocols are continuously increased, and the realization of an industrial controller with complete functions and strong universality faces huge challenges. The FPGA reconfigurable industrial controller with the Baoshuang design can realize the seamless switching between different communication protocols without power failure, and greatly improves the real-time property, the universality, the flexibility and the expandability of the industrial controller. In addition, the FPGA reconfigurable technology has wide application in other fields. Such as: adaptive hardware systems, wireless video encoders, adaptive Viterbi decoders, encryption applications, network remote reconstruction, and the like.
Disclosure of Invention
The invention aims to provide a reconfigurable symmetric encryption method for realizing software definition based on a domestic FPGA, and the method improves the real-time property, the universality, the flexibility and the expandability.
In order to achieve the purpose, the invention is realized by the following technical scheme:
a reconfigurable symmetric encryption method for realizing software definition based on a domestic FPGA comprises the following steps:
1) the user-defined software is responsible for sending a reconstruction control instruction, receiving a returned reconstruction state and transmitting a password algorithm configuration file;
2) the configuration file memory is used for storing logic configuration files of various encryption and decryption algorithms and is configured into an on-chip reconfigurable configuration partition through the reconfiguration controller during reconfiguration;
3) the reconfigurable area is composed of an encryption and decryption module and a reconfigurable high-speed protocol controller, the encryption and decryption module is composed of a cryptographic algorithm dynamic reconfigurable module for realizing encryption and decryption tasks and the like and a static non-reconfigurable module for data management and the like, and the encryption and decryption module is used for designing corresponding hardware logic to complete functions of managing a system clock, controlling data communication, working states and the like by using a reconfigurable area carrier;
4) the encryption and decryption module controls dynamic writing of configuration files, dynamic scheduling of configuration tasks and transmission of internal data by using the reconfiguration controller.
Preferably, the data path has two data paths, one is a data path in an unencrypted normal working state, and the other is an encryption/decryption data path after the user-defined software sends out an encryption instruction to complete dynamic reconstruction of a cryptographic algorithm.
Preferably, the control program of the dynamic reconfigurable hardware acceleration controller comprises the following steps:
1) starting a storage function, and waiting for the system host to self-define software to send an instruction;
2) judging whether a reconstruction instruction is received or not, if not, continuing to wait, if so, continuing to analyze the reconstruction instruction and generate a control signal, once sending a storage stop working instruction to the data management module, sending a configuration information transmission instruction to the configuration file storage, and sending a reconstruction starting instruction to the cryptographic algorithm reconstruction module;
3) judging whether the reconstruction is finished or not, if not, continuing to wait, and if so, sending a starting data encryption and decryption instruction to the data management module;
4) and judging whether the encryption and decryption are started successfully or not, if not, continuing to wait, and if so, sequentially sending a storage starting working instruction to the data management module and returning a completion state to the system host self-defined software.
The invention has the advantages that: the method can realize that corresponding logic is configured in a specified logic resource area according to different requirements of custom software during real-time operation, and the logic unit and the interconnection unit are correspondingly modified, thereby realizing the functions of encryption and decryption or direct storage of different cryptographic algorithms of data.
Drawings
The accompanying drawings, which are included to provide a further understanding of the invention and are incorporated in and constitute a part of this specification, illustrate embodiments of the invention and together with the description serve to explain the principles of the invention and not to limit the invention.
Fig. 1 is a reconfigurable data symmetric encryption overall structure of the invention.
FIG. 2 is a flowchart of the dynamic reconfiguration control system program of the present invention.
Detailed Description
The technical solutions in the embodiments of the present invention will be clearly and completely described below with reference to the drawings in the embodiments of the present invention, and it is obvious that the described embodiments are only a part of the embodiments of the present invention, and not all of the embodiments. All other embodiments, which can be derived by a person skilled in the art from the embodiments given herein without making any creative effort, shall fall within the protection scope of the present invention.
The structure of the invention is mainly completed by the cooperation of four parts of custom software, a configuration file memory, a reconfiguration controller and a reconfigurable area in a system host. The custom software is mainly responsible for sending a reconstruction control instruction, receiving a returned reconstruction state and transmitting a password algorithm configuration file. The configuration file memory is used for storing logic configuration files of various encryption and decryption algorithms, and the logic configuration files are configured into the on-chip reconfigurable configuration partition through the reconfiguration controller during reconfiguration. The reconfigurable area is the key for stable operation of the dynamic reconfigurable process and consists of an encryption and decryption module and a reconfigurable high-speed protocol controller. The encryption and decryption module consists of a dynamic reconfigurable module for realizing cryptographic algorithms such as encryption and decryption tasks and a static non-reconfigurable module for data management and the like. The encryption and decryption module is used for reconstructing a regional carrier, designing corresponding hardware logic to complete functions of managing a system clock, controlling data communication, working state and the like, and controlling functions of dynamic writing of configuration files, dynamic scheduling of configuration tasks, transmission of internal data and the like by using a reconstruction controller. The method can realize that corresponding logic is configured in a specified logic resource area according to different requirements of custom software during real-time operation, and the logic unit and the interconnection unit are correspondingly modified, thereby realizing the functions of encryption and decryption or direct storage of different cryptographic algorithms of data. The overall structure of the reconfigurable data symmetric encryption structure is shown in fig. 1.
The whole structure has two data paths, one is a data path in a non-encrypted normal working state, and the other is an encryption and decryption data path after the user-defined software sends out an encryption instruction to complete dynamic reconstruction of a cryptographic algorithm. Before the whole framework is operated, the configuration file of the cryptographic algorithm is required to be interconnected with the reconstruction controller through custom software, and the configuration file of the cryptographic algorithm is written into a configuration file storage.
After the software-defined reconfigurable data symmetric encryption overall architecture design is completed, the design of a control program in a dynamic reconfigurable hardware acceleration controller needs to be performed to meet the software-defined dynamic reconfigurable functional requirements, and the flow of the dynamic reconfigurable control program is shown in fig. 2.
Claims (3)
1. A reconfigurable symmetric encryption method for realizing software definition based on a domestic FPGA is characterized by comprising the following steps:
1) the user-defined software is responsible for sending a reconstruction control instruction, receiving a returned reconstruction state and transmitting a password algorithm configuration file;
2) the configuration file memory is used for storing logic configuration files of various encryption and decryption algorithms and is configured into an on-chip reconfigurable configuration partition through the reconfiguration controller during reconfiguration;
3) the reconfigurable area is composed of an encryption and decryption module and a reconfigurable high-speed protocol controller, the encryption and decryption module is composed of a cryptographic algorithm dynamic reconfigurable module for realizing encryption and decryption tasks and the like and a static non-reconfigurable module for data management and the like, and the encryption and decryption module is used for designing corresponding hardware logic to complete functions of managing a system clock, controlling data communication, working states and the like by using a reconfigurable area carrier;
4) the encryption and decryption module controls dynamic writing of configuration files, dynamic scheduling of configuration tasks and transmission of internal data by using the reconfiguration controller.
2. The reconfigurable symmetrical encryption method for realizing software definition based on the domestic FPGA according to claim 1, wherein the data path comprises two data paths, one is a data path in a non-encrypted normal working state, and the other is an encryption/decryption data path after the custom software sends an encryption instruction to complete dynamic reconfiguration of a cryptographic algorithm.
3. The method for realizing software-defined reconfigurable symmetric encryption based on the domestic FPGA according to claim 1, wherein the control program of the dynamic reconfigurable hardware acceleration controller comprises the following steps:
1) starting a storage function, and waiting for the system host to self-define software to send an instruction;
2) judging whether a reconstruction instruction is received or not, if not, continuing to wait, if so, continuing to analyze the reconstruction instruction and generate a control signal, once sending a storage stop working instruction to the data management module, sending a configuration information transmission instruction to the configuration file storage, and sending a reconstruction starting instruction to the cryptographic algorithm reconstruction module;
3) judging whether the reconstruction is finished or not, if not, continuing to wait, and if so, sending a starting data encryption and decryption instruction to the data management module;
4) and judging whether the encryption and decryption are started successfully or not, if not, continuing to wait, and if so, sequentially sending a storage starting working instruction to the data management module and returning a completion state to the system host self-defined software.
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Cited By (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN113836080A (en) * | 2021-09-23 | 2021-12-24 | 合肥芯荣微电子有限公司 | Computer system with software reconfigurable processor circuit and method thereof |
| CN114047948A (en) * | 2021-11-08 | 2022-02-15 | 可信计算科技(无锡)有限公司 | Reconfigurable trusted cryptographic module simulator, implementation method and simulation reconstruction method |
| CN114124389A (en) * | 2021-11-09 | 2022-03-01 | 国网山东省电力公司电力科学研究院 | Reconfigurable computing-based national cryptographic algorithm FPGA deployment method and system |
| CN116541898A (en) * | 2023-07-07 | 2023-08-04 | 山东多次方半导体有限公司 | FPGA-based reconfigurable password card design method for realizing multiple algorithms |
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| Publication number | Priority date | Publication date | Assignee | Title |
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