CN114398304A - Method for solving SRIO interface blocking - Google Patents
Method for solving SRIO interface blocking Download PDFInfo
- Publication number
- CN114398304A CN114398304A CN202210025365.4A CN202210025365A CN114398304A CN 114398304 A CN114398304 A CN 114398304A CN 202210025365 A CN202210025365 A CN 202210025365A CN 114398304 A CN114398304 A CN 114398304A
- Authority
- CN
- China
- Prior art keywords
- fpga
- srio interface
- cpu
- solving
- srio
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 238000000034 method Methods 0.000 title claims abstract description 26
- 230000000903 blocking effect Effects 0.000 title claims abstract description 18
- 238000004891 communication Methods 0.000 abstract description 6
- 238000013461 design Methods 0.000 abstract description 4
- 238000010586 diagram Methods 0.000 description 2
- 238000012360 testing method Methods 0.000 description 2
- 238000012795 verification Methods 0.000 description 2
- 230000004075 alteration Effects 0.000 description 1
- 230000009286 beneficial effect Effects 0.000 description 1
- 230000007547 defect Effects 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
- 238000012545 processing Methods 0.000 description 1
- 238000006467 substitution reaction Methods 0.000 description 1
Images
Classifications
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
- G06F13/38—Information transfer, e.g. on bus
- G06F13/42—Bus transfer protocol, e.g. handshake; Synchronisation
- G06F13/4282—Bus transfer protocol, e.g. handshake; Synchronisation on a serial bus, e.g. I2C bus, SPI bus
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F1/00—Details not covered by groups G06F3/00 - G06F13/00 and G06F21/00
- G06F1/24—Resetting means
Landscapes
- Engineering & Computer Science (AREA)
- Theoretical Computer Science (AREA)
- Physics & Mathematics (AREA)
- General Engineering & Computer Science (AREA)
- General Physics & Mathematics (AREA)
- Information Transfer Systems (AREA)
Abstract
The invention relates to the technical field of high-speed interface communication, and discloses a method for solving SRIO interface blocking, which comprises the following steps: the first step is as follows: the CPU polls the state of an SRIO interface between the CPU and the FPGA through a local BUS (BUS); the second step is that: after receiving a reset signal sent by the CPU, the FPGA resets the internal logic; the third step: after receiving the reconfiguration command, the FPGA sends an IPROG command through the ICAP to reconfigure, captures an externally input asynchronous reset signal, and reconfigures the FPGA started in an active mode, thereby solving the problem that normal communication cannot be realized due to SRIO interface blockage between the FPGA and a PowerPC CPU; in the hardware design of the Master configuration mode, the FPGA is reconfigured under the condition that the equipment is not powered off, and the problem of SRIO interface blockage between the CPU and the FPGA is solved.
Description
Technical Field
The invention relates to the technical field of high-speed interface communication, in particular to a method for solving SRIO interface blocking.
Background
In the hardware architecture design of heterogeneous computing, a CPU + FPGA is a common hardware architecture mode, and in a scenario where the CPU + FPGA needs to exchange data at a high speed, SRIO is a common communication interface. Due to the difference of the power-on time and the reset processing of the CPU and the FPGA, the SRIO interface can be accidentally blocked and cannot be recovered in the using process, and further communication cannot be achieved. For an FPGA which is configured by adopting a Slave-Serial and Slave-SelectMAP mode in hardware design, the problem can be solved by reconfiguration; however, for the FPGAs started in the Master-Serial, Master-SelectMAP, Master-SPI, and Master-BPI modes, since the FPGAs is configured and started only once when the hardware board is powered on, the FPGAs can be reconfigured only by power-off restart. In some application scenarios, the device is not allowed to be powered off, which needs to solve the problem of reconfiguring internal logic data once by the FPGA without power failure. The method solves the problem of dynamically configuring the FPGA in a Master configuration mode without power failure by using the internal primitive ICAP of the FPGA.
Disclosure of Invention
Technical problem to be solved
Aiming at the defects of the prior art, the invention provides a method for solving SRIO interface blocking.
(II) technical scheme
In order to achieve the purpose, the invention provides the following technical scheme: a method for solving SRIO interface blocking comprises the following steps:
the first step is as follows: the CPU polls the state of an SRIO interface between the CPU and the FPGA through a local BUS (BUS);
the second step is that: after receiving a reset signal sent by the CPU, the FPGA resets the internal logic;
the third step: after receiving the reconfiguration command, the FPGA sends an IPROG command through the ICAP to reconfigure.
Preferably, in the first step, once the SRIO interface is found to be blocked, a soft reset signal is first sent to the FPGA, and the SRIO interface is reset.
Preferably, in the first step, once the SRIO interface is found to be blocked, a soft reset signal is first sent to the FPGA, and the SRIO interface is reset.
Preferably, the address stored in the FLASH by the logic to be reconfigured is filled in the Warm boot start address of the configuration data sent by the IRPOG in the third step.
Preferably, when the FPGA is configured in a Master mode, data is read from the 0 address of the FLASH by default after the FPGA is powered on and started. So the configuration bit file we write at FLASH address 0 should contain the ICAP2 primitive.
(III) advantageous effects
Compared with the prior art, the invention provides a method for solving SRIO interface blocking, which has the following beneficial effects:
1. according to the method for solving the SRIO interface blocking problem, in the hardware design of a Master configuration mode, the FPGA is reconfigured under the condition that equipment is not powered off, and the problem of SRIO interface blocking between a CPU and the FPGA is solved.
2. According to the method for solving the SRIO interface blocking problem, when the SRIO interface blocking problem is solved, only the BOOT _ ADDR in the icap2_ top module is changed into 0x0000_0000, and after the CPU monitors that the SRIO interface at the opposite end is blocked, the CPU informs the FPGA to generate a reset signal to the icap2_ top module, so that the reconfiguration of the FPGA can be completed without power failure, and the problem of the interface blocking is solved.
3. According to the method for solving the SRIO interface blockage, an externally input asynchronous reset signal is captured, the FPGA started in an active mode is reconfigured, and the problem that normal communication cannot be achieved due to the SRIO interface blockage between the FPGA and a PowerPC CPU is solved.
Drawings
FIG. 1 is a block diagram of the present invention;
FIG. 2 is a diagram illustrating a CAP data frame format according to the present invention.
Detailed Description
The technical solutions in the embodiments of the present invention will be clearly and completely described below with reference to the drawings in the embodiments of the present invention, and it is obvious that the described embodiments are only a part of the embodiments of the present invention, and not all of the embodiments. All other embodiments, which can be derived by a person skilled in the art from the embodiments given herein without making any creative effort, shall fall within the protection scope of the present invention.
Referring to fig. 1-2, a method for solving SRIO interface blocking includes the following steps:
the first step is as follows: the CPU polls the state of an SRIO interface between the CPU and the FPGA through a local BUS (BUS);
the second step is that: after receiving a reset signal sent by the CPU, the FPGA resets the internal logic;
the third step: after receiving the reconfiguration command, the FPGA sends an IPROG command through the ICAP to reconfigure.
In the first step, once the situation that the SRIO interface is blocked is found, a soft reset signal is firstly sent to the FPGA, and meanwhile, the SRIO interface is reset.
In the first step, once the situation that the SRIO interface is blocked is found, a soft reset signal is firstly sent to the FPGA, and meanwhile, the SRIO interface is reset.
And in the third step, the address stored in the FLASH of the logic to be reconfigured is filled in by the Warm boot start address of the configuration data sent by the IRPOG.
And when the FPGA is configured in a Master mode, reading data from the 0 address of the FLASH by default after the FPGA is powered on and started. So the configuration bit file we write at FLASH address 0 should contain the ICAP2 primitive.
When the method is used, the first project is established and named led1, and the finally generated bit file is led _ icap _ top.
1. After the FPGA is powered on, the internal lighting logic is first executed (flashing once for 1 second). After waiting for about 10 seconds, releasing the reset signal of the icap2_ top module;
2. and after 5 seconds of reset release is received by the icap2_ top module, writing a new load address into the ICAPE2 core according to fixed time sequence.
3. ICAPE2, upon receiving the instruction, reads the led2_ top. bit file from FLASH at address 0x0040_0000 and loads.
The second project is named led2, the finally generated bit file is led2_ top. bit, the implementation function is lighting logic, and the flash is performed once every 200 milliseconds.
And (3) generating an icap _ test.mcs file by using a vido 2018.2 tool and led1.bit and led2.bit, and finally programming the icap _ test.mcs file into Flash. Note that the Start address of led2_ top. bit is to be kept consistent with that in ICAP.
The implementation flow shows a verification method of the reconfiguration function of ICAP2, and the verification is completed on a xilinx xc7k325tfbg900 chip, so that the determination method is feasible.
Although embodiments of the present invention have been shown and described, it will be appreciated by those skilled in the art that changes, modifications, substitutions and alterations can be made in these embodiments without departing from the principles and spirit of the invention, the scope of which is defined in the appended claims and their equivalents.
Claims (5)
1. A method for solving SRIO interface blocking is characterized in that: the method comprises the following steps:
the first step is as follows: the CPU polls the state of an SRIO interface between the CPU and the FPGA through a local BUS (BUS);
the second step is that: after receiving a reset signal sent by the CPU, the FPGA resets the internal logic;
the third step: after receiving the reconfiguration command, the FPGA sends an IPROG command through the ICAP to reconfigure.
2. The method according to claim 1, wherein the method for solving SRIO interface blocking comprises: in the first step, once the situation that the SRIO interface is blocked is found, a soft reset signal is firstly sent to the FPGA, and meanwhile, the SRIO interface is reset.
3. The method according to claim 1, wherein the method for solving SRIO interface blocking comprises: and if the problem of interface blockage cannot be solved in the first step, writing a reconfiguration instruction into the FPGA.
4. The method according to claim 1, wherein the method for solving SRIO interface blocking comprises: and in the third step, the address stored in the FLASH of the logic to be reconfigured is filled in by the Warm boot start address of the configuration data sent by the IRPOG.
5. The method according to claim 1, wherein the method for solving SRIO interface blocking comprises: and when the FPGA is configured in a Master mode, reading data from the 0 address of the FLASH by default after the FPGA is powered on and started. So the configuration bit file we write at FLASH address 0 should contain the ICAP2 primitive.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202210025365.4A CN114398304A (en) | 2022-03-01 | 2022-03-01 | Method for solving SRIO interface blocking |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202210025365.4A CN114398304A (en) | 2022-03-01 | 2022-03-01 | Method for solving SRIO interface blocking |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| CN114398304A true CN114398304A (en) | 2022-04-26 |
Family
ID=81230116
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN202210025365.4A Pending CN114398304A (en) | 2022-03-01 | 2022-03-01 | Method for solving SRIO interface blocking |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN114398304A (en) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN114443170A (en) * | 2022-01-29 | 2022-05-06 | 中国航空无线电电子研究所 | FPGA dynamic parallel loading and unloading system |
Citations (7)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN101727423A (en) * | 2008-10-17 | 2010-06-09 | 东北大学 | System capable of preempting multiple hardware tasks on reconfigurable FPGA and implementing method thereof |
| CN105095139A (en) * | 2014-05-08 | 2015-11-25 | 中兴通讯股份有限公司 | Inter-integrated circuit system and data operation and transmission method thereof |
| CN209088985U (en) * | 2018-12-29 | 2019-07-09 | 成都蓉威电子技术有限公司 | A kind of designing system of RapidIO Reconfigurable Datapath |
| CN111190853A (en) * | 2019-12-26 | 2020-05-22 | 南京理工大学 | High-speed communication system between pieces based on EMIF and SRIO interface |
| CN111274183A (en) * | 2020-02-21 | 2020-06-12 | 山东超越数控电子股份有限公司 | Multi-path high-speed protocol interface dynamic reconfigurable system and implementation method |
| CN112540770A (en) * | 2019-09-23 | 2021-03-23 | 中国科学院沈阳自动化研究所 | PowerPC and FPGA-based heterogeneous platform and acceleration method thereof |
| CN113010264A (en) * | 2021-04-16 | 2021-06-22 | 西北工业大学 | Software radar online reconfigurable platform based on FPGA + DSP and implementation method |
-
2022
- 2022-03-01 CN CN202210025365.4A patent/CN114398304A/en active Pending
Patent Citations (7)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN101727423A (en) * | 2008-10-17 | 2010-06-09 | 东北大学 | System capable of preempting multiple hardware tasks on reconfigurable FPGA and implementing method thereof |
| CN105095139A (en) * | 2014-05-08 | 2015-11-25 | 中兴通讯股份有限公司 | Inter-integrated circuit system and data operation and transmission method thereof |
| CN209088985U (en) * | 2018-12-29 | 2019-07-09 | 成都蓉威电子技术有限公司 | A kind of designing system of RapidIO Reconfigurable Datapath |
| CN112540770A (en) * | 2019-09-23 | 2021-03-23 | 中国科学院沈阳自动化研究所 | PowerPC and FPGA-based heterogeneous platform and acceleration method thereof |
| CN111190853A (en) * | 2019-12-26 | 2020-05-22 | 南京理工大学 | High-speed communication system between pieces based on EMIF and SRIO interface |
| CN111274183A (en) * | 2020-02-21 | 2020-06-12 | 山东超越数控电子股份有限公司 | Multi-path high-speed protocol interface dynamic reconfigurable system and implementation method |
| CN113010264A (en) * | 2021-04-16 | 2021-06-22 | 西北工业大学 | Software radar online reconfigurable platform based on FPGA + DSP and implementation method |
Non-Patent Citations (2)
| Title |
|---|
| 刘建军;郭秋丽;邸海涛;孟海宁;: "一种主从式动态重配置系统的软件架构技术", 航空计算技术, no. 05, 25 September 2018 (2018-09-25), pages 149 - 152 * |
| 李平;吴晓;山寿;: "基于SPI FLASH的FPGA多重配置", 现代电子技术, no. 22, 15 November 2013 (2013-11-15), pages 135 - 138 * |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN114443170A (en) * | 2022-01-29 | 2022-05-06 | 中国航空无线电电子研究所 | FPGA dynamic parallel loading and unloading system |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| WO2021164170A1 (en) | Multi-path high-speed protocol interface dynamic reconfiguration system and implementation method therefor | |
| CN107977217B (en) | Method for online loading XILINX-FPGA multi-version updating program | |
| US7856546B2 (en) | Configurable processor module accelerator using a programmable logic device | |
| CN101853172B (en) | Device and method for dynamically upgrading complex programmable logic device (CPLD) | |
| CN105808290B (en) | Remote dynamic updating system and method for multi-FPGA complete machine system | |
| WO2018064885A1 (en) | Apparatus and method for configuring or updating programmable logic device | |
| US10929150B2 (en) | Optical line terminal and method for upgrading primary device and secondary device of optical line terminal | |
| CN103618618A (en) | Line card fault recovery method and related device based on distributed PCIE system | |
| CN114398304A (en) | Method for solving SRIO interface blocking | |
| CN102053849B (en) | Distributed system, main system and slave systems thereof and a code loading method | |
| CN105302621A (en) | Method for remotely achieving initial value restoration of server BIOS Setup | |
| JP2016045954A (en) | System and method for initializing rf module through nonvolatile control | |
| CN113127302A (en) | Method and device for monitoring GPIO (general purpose input/output) of board card | |
| CN112988271A (en) | System and method for dynamically configuring FPGA (field programmable Gate array) in passive SelectMAP (selectable MAP) mode | |
| CN115167935A (en) | Software dynamic function reconstruction information processing method based on domestic DSP | |
| CN101359298A (en) | Method for removing internal memory with BIOS and computer system thereof | |
| CN112347035B (en) | Remote FPGA equipment-oriented dynamic part reconfigurable configuration device and method | |
| CN213634473U (en) | Device and system for realizing remote deployment and debugging of FPGA (field programmable Gate array) based on SIP (Session initiation protocol) | |
| CN104461659A (en) | High-reliability computer starting method | |
| CN113626363A (en) | Multi-bus architecture device facing micro-nano satellite-borne computer and control method thereof | |
| CN111459875A (en) | MCU processor and packaging method thereof | |
| CN116432574B (en) | Method and device for automatically reading back FLASH data by FPGA configuration controller | |
| CN109144583A (en) | Mainboard information acquisition method, device, system and equipment based on Domestic Platform | |
| US20220113883A1 (en) | Field-programmable gate array (fpga) for implementing data transfer between different configuration and application processes | |
| CN114741347B (en) | PCIe card control method and device and PCIe card |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| PB01 | Publication | ||
| PB01 | Publication | ||
| SE01 | Entry into force of request for substantive examination | ||
| SE01 | Entry into force of request for substantive examination |