CN113010264A - Software radar online reconfigurable platform based on FPGA + DSP and implementation method - Google Patents
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Abstract
The invention discloses a software radar online reconfigurable platform based on FPGA + DSP and an implementation method thereof.A signal processing hardware platform is powered on to run, and a bootstrap program loads a main control core program; the upper computer builds and configures a radar system and sends configuration information to the master control core; the main control core distributes an algorithm component program to the algorithm core according to the configuration information; the DSP communication core receives the data, sends the data to the algorithm core for processing according to the thread priority order, and returns the processed data to the communication core; the upper computer reconstructs the radar system, transmits an online reconstruction instruction, transmits the reconstructed configuration information to the main control core, and covers the original configuration information; the main control core receives the reconstruction instruction and re-analyzes the configuration information; and according to the new configuration information, reconstructing the configuration and the priority of the algorithm core to finish reconstruction. The invention can dynamically reconstruct the radar system in real time according to different task requirements, reduces the coupling between software and hardware of the radar system and shortens the radar research and development period.
Description
Technical Field
The invention belongs to the technical field of radars, and particularly relates to a software radar online reconfigurable platform and an implementation method.
Background
Road traffic radar has long been used in assisted driving systems, and in emerging autonomous driving, radar has played an important role. At present, the radar and the video are combined and applied in the field of automatic driving, and great strength is contributed to the development of intelligent traffic. Compared with the traditional equipment, the radar equipment has more advantages, such as convenient installation and maintenance of a barrier gate radar and high precision, and more accurate vehicle detection can provide great convenience for vehicle owners no matter in parking spaces or driving. Most importantly, the radar has the characteristics of all-weather real-time performance, high resolution and multiple targets, strong anti-interference performance, capability of measuring speed and distance, no influence of severe weather and the like, is a sharp device for realizing intelligent traffic, the software-based radar online reconstruction technology is oriented to actual requirements, and an intelligent traffic system is in close fit, so that the realization of intellectualization, comprehensiveness, accuracy and real-time of the traffic system has more feasibility.
In the aspect of military requirements, the radar has various types, and radars with different purposes and different functions have different requirements on signal parameters (carrier frequency, pulse width and the like). At present, the designed and developed radar cannot meet the requirement of intelligently tracking and detecting targets with different attributes under different environments. From the perspective of actual combat, in order to capture the air control right and win the electromagnetic warfare in the early stage of the warfare in the modern warfare, radars have become the first major tactical target of missiles and air forces in various countries. Due to the reason, the concept of the Software-based Radar is developed, the Software-based Radar (Software Defined Radar) is a general hardware platform for detecting and tracking a standard interface, which is formed by a broadband smart antenna and a radio frequency front end, and a general high-speed DSP/CPU system, and the specific functions are completed by Software. The design of the radars of different systems is realized by software by building a universal hardware platform, so that the research and development time is shortened, and the research and development cost and the development risk are reduced. The survival ability of the radar is a key index which has to be considered in the development of the modern radar, and the software-based radar online reconfigurable technology provides a new idea for the research of the existing radar. Through the standardized design of the core algorithm component, the functions of the radar system can be built and defined by the component, the radar system has the advantages of service component modularization, dynamic loading application and the like, the radar signal system can be easily changed by downloading a new program and releasing new parameters through the software-based radar online reconfigurable technology, and the task requirement can be quickly responded. On the other hand, the high-performance digital device is used, and the software radar online reconstruction technology is more quickly and conveniently realized by adopting the system structure of the embedded system.
Disclosure of Invention
In order to overcome the defects of the prior art, the invention provides a software radar online reconfigurable platform based on FPGA + DSP and an implementation method thereof, wherein firstly, a signal processing hardware platform is electrified and operated, and a bootstrap program is loaded with a main control kernel program; the upper computer builds and configures a radar system and sends configuration information to the master control core; the main control core distributes an algorithm component program to the algorithm core according to the configuration information; the DSP communication core receives the data, sends the data to the algorithm core for processing according to the thread priority order, and returns the processed data to the communication core; the upper computer reconstructs the radar system, transmits an online reconstruction instruction, transmits the reconstructed configuration information to the main control core, and covers the original configuration information; the main control core receives the reconstruction instruction and re-analyzes the configuration information; and according to the new configuration information, reconstructing the configuration and the priority of the algorithm core to finish reconstruction. The invention can dynamically reconstruct the radar system in real time according to different task requirements, reduces the coupling between software and hardware of the radar system and shortens the radar research and development period.
The technical scheme adopted by the invention for solving the technical problems is as follows:
a software radar online reconfigurable platform based on FPGA + DSP is of a four-layer structure and comprises a human-computer interaction module, a reconfigurable core layer, an operating system layer and a hardware layer which are sequentially arranged from top to bottom;
the human-computer interaction module comprises a control interface and a display interface; the control interface is responsible for scheme planning, system modeling, parameter configuration and instruction issuing; the display interface is responsible for storing and displaying the processing result of the radar signal;
the reconstruction core layer comprises a component library, component management and reconstruction management; the component library comprises a complete radar algorithm component library, or self-defined component research and development are carried out on the basis of a component standardized model according to radar function requirements;
the operating system layer is based on an SYS/BIOS real-time operating system and is responsible for dynamically managing tasks, threads, interrupts and management configuration of hardware resources in the DSP;
the hardware layer is a software radar hardware processing platform, comprises an AD, an FPGA, a DSP and front-end equipment and is responsible for executing calculation, storage and communication tasks.
Preferably, the radar algorithm component library comprises PC, MTI, MTD, CFAR algorithm components.
Preferably, the component library describes parameters of the components by using an XML electronic form.
A software radar online reconfigurable implementation method based on FPGA + DSP includes the following steps:
step 1: establishing a software radar component standardized model;
step 2: designing a software radar system scheme, and building a hardware processing platform according to the software radar system scheme;
and step 3: configuring a software radar system scheme and parameters, and allocating tasks of each core of a hardware processing platform DSP;
and 4, step 4: a hardware processing platform is powered on to run, and a bootstrap program loads a DSP main control core program;
and 5: the upper computer builds and configures a software radar system and sends configuration information to the DSP main control core;
step 6: the DSP main control core distributes algorithm components to the DSP algorithm cores according to the configuration information, and sets the priority of task threads of each algorithm core of the DSP;
and 7: collecting radar signal data through hardware processing platform front-end equipment;
and 8: the FPGA receives radar signal data, sends an interrupt notification to the DSP, and the data communication thread starts to run;
and step 9: after receiving the radar signal data, the DSP communication core sends the radar signal data to the DSP algorithm core with the highest priority according to the priority order of the threads,
step 10: the DSP algorithm checks the received radar signal data for processing, returns the processed data to the DSP communication core after the processing is finished, and sends the processed data to the DSP algorithm core with the next priority after the DSP communication core receives the processed data returned by the DSP algorithm core, and so on;
step 11: the DSP communication core respectively stores and uploads the processing results of all the DSP algorithm cores;
step 12: the upper computer reconstructs the software radar system, sends an online reconstruction instruction, sends reconstructed configuration information to the DSP main control core, and covers the original configuration information;
step 13: the DSP main control core receives the reconstruction instruction and re-analyzes the configuration information; loading, unloading or upgrading the algorithm core according to the new configuration information, and reallocating the task and task priority of the DSP algorithm core;
step 14: the reconstructed DSP algorithm core operates a new processing program again; and completing the reconstruction.
The invention has the following beneficial effects:
1. the method can carry out real-time dynamic reconstruction according to the radar battlefield requirements, ensures the basic operation capacity of the system and improves the stability;
2. the invention performs software and hardware decoupling on the radar system based on the algorithm component technology, thereby greatly improving the expandability and reducing the upgrading and maintenance cost.
Drawings
FIG. 1 is a structural diagram of a software-based radar online reconfigurable platform based on FPGA + DSP.
FIG. 2 is a flow chart of a signal processing simulation system according to an embodiment of the present invention.
Fig. 3 is a schematic diagram of a radar system according to an embodiment of the present invention.
Fig. 4 is a block diagram of the overall software design of the system according to the embodiment of the present invention.
Fig. 5 is a multi-core workflow diagram of a pulse doppler radar simulation processing system according to an embodiment of the present invention.
Fig. 6 is a multi-core workflow diagram of the reconstructed pulse doppler radar simulation processing system according to the embodiment of the present invention.
Detailed Description
The invention is further illustrated with reference to the following figures and examples.
As shown in fig. 1, a software-based radar online reconfigurable platform based on FPGA + DSP is a four-layer structure, which is a human-computer interaction module, a reconfigurable core layer, an operating system layer and a hardware layer sequentially from top to bottom;
the human-computer interaction module comprises a control interface and a display interface; the control interface is responsible for scheme planning, system modeling, parameter configuration and instruction issuing; the display interface is responsible for storing and displaying the processing result of the radar signal;
the reconstruction core layer comprises a component library, component management and reconstruction management; the component library comprises a complete radar algorithm component library which comprises algorithm components such as a PC, an MTI, an MTD and a CFAR, or self-defined component research and development are carried out on the basis of a component standardized model according to radar function requirements; the component library adopts an XML electronic form to describe the parameters of the components;
the operating system layer is based on an SYS/BIOS real-time operating system and is responsible for dynamically managing tasks, threads, interrupts and management configuration of hardware resources in the DSP;
the hardware layer is a software radar hardware processing platform, comprises an AD, an FPGA, a DSP and front-end equipment and is responsible for executing calculation, storage and communication tasks.
A software radar online reconfigurable implementation method based on FPGA + DSP includes the following steps:
step 1: establishing a software radar component standardized model;
step 2: designing a software radar system scheme, and building a hardware processing platform according to the software radar system scheme;
and step 3: configuring a software radar system scheme and parameters, and allocating tasks of each core of a hardware processing platform DSP;
and 4, step 4: a hardware processing platform is powered on to run, and a bootstrap program loads a DSP main control core program;
and 5: the upper computer builds and configures a software radar system and sends configuration information to the DSP main control core;
step 6: the DSP main control core distributes algorithm components to the DSP algorithm cores according to the configuration information, and sets the priority of task threads of each algorithm core of the DSP;
and 7: collecting radar signal data through hardware processing platform front-end equipment;
and 8: the FPGA receives radar signal data, sends an interrupt notification to the DSP, and the data communication thread starts to run;
and step 9: after receiving the radar signal data, the DSP communication core sends the radar signal data to the DSP algorithm core with the highest priority according to the priority order of the threads,
step 10: the DSP algorithm checks the received radar signal data for processing, returns the processed data to the DSP communication core after the processing is finished, and sends the processed data to the DSP algorithm core with the next priority after the DSP communication core receives the processed data returned by the DSP algorithm core, and so on;
step 11: the DSP communication core respectively stores and uploads the processing results of all the DSP algorithm cores;
step 12: the upper computer reconstructs the software radar system, sends an online reconstruction instruction, sends reconstructed configuration information to the DSP main control core, and covers the original configuration information;
step 13: the DSP main control core receives the reconstruction instruction and re-analyzes the configuration information; loading, unloading or upgrading the algorithm core according to the new configuration information, and reallocating the task and task priority of the DSP algorithm core;
step 14: the reconstructed DSP algorithm core operates a new processing program again; and completing the reconstruction.
The specific embodiment is as follows:
in order to verify the software radar online reconfigurable technical scheme, visual modeling software is used for building a pulse Doppler radar signal processing simulation system, and the simulation system consists of typical processing modules of the radar signal processing system and comprises basic algorithm components such as pulse compression, moving target detection and constant false alarm detection. The signal processing simulation system flow is shown in figure 2. In fig. 2, the input data is a radar echo simulation signal, which mainly includes target echo, environmental clutter, system noise, and various interferences.
According to the data flow of the simulation system, an algorithm component is called on a graphical development interface of the radar system and connected with the input-output relationship of the component interface, so that a radar system scheme is formed as shown in fig. 3. A pulse Doppler radar signal system is built in the page, and a parameter configuration interface can be popped up by double clicking the component in the system. The radar system can be reconstructed by modifying the parameters of the components, the system sends a reconstruction instruction to the hardware processing platform after reconstruction, and the hardware processing platform can reconstruct the components running on the specified core through the reconstruction flow after receiving the reconstruction instruction. And generating a new XML description file by the modified parameters, and updating the original parameters in the component.
After the radar system is formed, a generation button is clicked, a task configuration parameter file of the component can be generated, the configuration file is issued to a main control core 0 of the hardware platform to perform task analysis, and the mapping relation of the algorithm component corresponding to the multiple cores is matched. The algorithm components are made into executable mirror image files and loaded into FLASH of the DSP, and then the algorithm components can be loaded onto cores to run respectively.
The multi-core reconstruction function division and the multi-core DSP have the advantages that multiple cores can be processed in parallel, and software developers can reasonably distribute application programs to have higher processing efficiency. The most critical in the design of multi-core software is that a plurality of tasks are definitely divided into different cores, and the functions of the multi-core are divided as follows based on a master-slave model:
1) and the core 0 is used as a main control core, interacts with an external upper computer and manages and dispatches other cores according to the instruction of the upper computer. Meanwhile, the core 0 carries a network communication task thread and can acquire an algorithm mirror image which needs to be loaded by the system from an external server.
2) The core 1 serves as a communication core and is responsible for receiving data acquired by the FPGA through the SRIO, analyzing the data format, and then distributing the data to different algorithm cores for processing according to task planning of the main control core. And the data processing result is sent to the display control terminal through the Ethernet interface for result analysis.
3) The other cores are slave cores and are used as algorithm cores, and are responsible for operating a specific algorithm to process data and sending the received data to the communication core after processing. The algorithm core is managed and scheduled by the main control core, and the algorithm components running on the algorithm core can be upgraded on line.
Because the loading of the multi-core application program and the starting of other cores are completed by the core 0 when the DSP is powered on and started by default, the core 0 is adopted as a main control core to take charge of the initialization management of the whole system. After the DSP is powered on, the core 0 is started first to complete initialization of system hardware, then the mirror image starting core 1 of the core 1 is loaded, other cores are in a dormant state, and the core 0 determines the starting sequence of the other data processing cores according to the command of the upper computer. The overall software design block diagram of the system is shown in fig. 4.
After the core 1 is started as a communication core, firstly, SRIO hardware is initialized, then, a hardware interrupt thread is operated to monitor an SRIO doorbell packet event, and then, an inter-core communication thread is established for carrying out data interaction with 6 algorithm cores. And then, when receiving the interrupt of the doorbell packet, indicating that external data comes, the main thread analyzes and classifies the data and distributes different data to corresponding algorithm cores for processing. And other slave cores establish inter-core communication threads after being started, monitor data of the communication cores and process the data through a specific algorithm after the data arrive.
And after the core 0 is started, an external interrupt thread is established for monitoring a control command of the upper computer. And an Ethernet communication thread is established, a network communication task is triggered after an online reconfiguration command is received, a connection request is initiated to a remote server, a required software mirror image is read from a core server, and then software on a corresponding core is replaced.
Due to the limitation of equipment, the invention adopts an upper computer to generate echo simulation data, and the echo simulation data is sent to the FPGA through an Ethernet interface to simulate the acquisition of echo signals. The FPGA sends the acquired echo data to the DSP for processing through the SRIO interface, and the upper computer sends a reconstruction instruction and other notification signals to the DSP through external hardware interruption. After the DSP receives the external hardware interrupt, the control command is analyzed by matching the ID of the interrupt source. And after the DSP finishes processing the received radar signals, packaging the processing results and sending the processing results back to the upper computer through the Ethernet interface, and calling MATLAB by the upper computer to display the processing results.
Under the scheduling of the main control core 0, the algorithm core 2 runs a Pulse Compression (PC) algorithm component program; the algorithm core 3 runs a Moving Target Detection (MTD) algorithm component program (realized by adopting FFT); the algorithm core 4 runs a constant false alarm detection program (realized by adopting unit average constant false alarm detection, 3 protection units and 8 reference units on each side), and the cores 5-7 are reserved for standby. The multi-core work flow of the pulse Doppler radar simulation processing system is shown in figure 5.
1) The main control core 0 sequentially starts the operation of the cores 1-4 under the control of a software framework of the main control core, and the cores 5-7 are still in a dormant state;
2) after the communication core 1 operates, waiting for the FPGA to transmit analog echo data through the SRIO; after receiving the radar signal data, analyzing the radar signal data, removing format information, and sending a data address to an algorithm core 2-4;
3) the 3 algorithm cores receive data addresses through inter-core communication respectively, pulse compression, moving target detection and averaging unit constant false alarm processing are sequentially carried out on the data, and after the processing of each algorithm core is finished, a result address is returned to the communication core;
4) after each algorithm core finishes processing, the communication core 1 sends the processing result to an upper computer for storage through the Ethernet result so as to carry out analysis and comparison.
On the basis of the realization of the pulse Doppler radar, a reconstruction scheme is designed for carrying out reconstruction technical verification. On the basis of the original system, the core 5 loads a moving target display algorithm component to join the system to reconstruct a new signal processing system. The reconstruction scheme is characterized in that a moving target display algorithm component is added when an original system runs, after the pulse compression algorithm component finishes the processing of original data, the data are sent to the moving target display algorithm component for processing, and moving target display and constant false alarm detection processing are sequentially carried out on the result of the moving target display algorithm processing. The moving target display module is added to filter out the net target clutter, and the multi-kernel mapping of the reconstruction scheme is shown in fig. 6.
And respectively loading the systems before and after reconstruction into a hardware platform, and carrying out example verification according to the steps of the reconstruction method, wherein the accuracy of reconstruction is verified according to experimental results.
Claims (4)
1. A software radar online reconfigurable platform based on FPGA + DSP is characterized in that the online reconfigurable platform is of a four-layer structure and sequentially comprises a human-computer interaction module, a reconfigurable core layer, an operating system layer and a hardware layer from top to bottom;
the human-computer interaction module comprises a control interface and a display interface; the control interface is responsible for scheme planning, system modeling, parameter configuration and instruction issuing; the display interface is responsible for storing and displaying the processing result of the radar signal;
the reconstruction core layer comprises a component library, component management and reconstruction management; the component library comprises a complete radar algorithm component library, or self-defined component research and development are carried out on the basis of a component standardized model according to radar function requirements;
the operating system layer is based on an SYS/BIOS real-time operating system and is responsible for dynamically managing tasks, threads, interrupts and management configuration of hardware resources in the DSP;
the hardware layer is a software radar hardware processing platform, comprises an AD, an FPGA, a DSP and front-end equipment and is responsible for executing calculation, storage and communication tasks.
2. The FPGA + DSP-based software-based radar online reconfigurable platform according to claim 1, wherein the radar algorithm component library comprises PC, MTI, MTD and CFAR algorithm components.
3. The FPGA + DSP-based software-based radar online reconfigurable platform is characterized in that the component library adopts an XML electronic form to describe parameters of the components.
4. A software radar online reconfigurable implementation method based on FPGA + DSP is characterized by comprising the following steps:
step 1: establishing a software radar component standardized model;
step 2: designing a software radar system scheme, and building a hardware processing platform according to the software radar system scheme;
and step 3: configuring a software radar system scheme and parameters, and allocating tasks of each core of a hardware processing platform DSP;
and 4, step 4: a hardware processing platform is powered on to run, and a bootstrap program loads a DSP main control core program;
and 5: the upper computer builds and configures a software radar system and sends configuration information to the DSP main control core;
step 6: the DSP main control core distributes algorithm components to the DSP algorithm cores according to the configuration information, and sets the priority of task threads of each algorithm core of the DSP;
and 7: collecting radar signal data through hardware processing platform front-end equipment;
and 8: the FPGA receives radar signal data, sends an interrupt notification to the DSP, and the data communication thread starts to run;
and step 9: after receiving the radar signal data, the DSP communication core sends the radar signal data to the DSP algorithm core with the highest priority according to the priority order of the threads,
step 10: the DSP algorithm checks the received radar signal data for processing, returns the processed data to the DSP communication core after the processing is finished, and sends the processed data to the DSP algorithm core with the next priority after the DSP communication core receives the processed data returned by the DSP algorithm core, and so on;
step 11: the DSP communication core respectively stores and uploads the processing results of all the DSP algorithm cores;
step 12: the upper computer reconstructs the software radar system, sends an online reconstruction instruction, sends reconstructed configuration information to the DSP main control core, and covers the original configuration information;
step 13: the DSP main control core receives the reconstruction instruction and re-analyzes the configuration information; loading, unloading or upgrading the algorithm core according to the new configuration information, and reallocating the task and task priority of the DSP algorithm core;
step 14: the reconstructed DSP algorithm core operates a new processing program again; and completing the reconstruction.
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| CN113468101A (en) * | 2021-07-07 | 2021-10-01 | 中国船舶重工集团公司第七二四研究所 | Domestic CPU-based radar signal processing function reconstruction method |
| CN113419991B (en) * | 2021-07-07 | 2023-09-26 | 中国船舶集团有限公司第七二四研究所 | Dynamic configuration method for radar anti-interference measures based on CPU and FPGA |
| CN113468101B (en) * | 2021-07-07 | 2024-02-27 | 中国船舶集团有限公司第七二四研究所 | Radar signal processing function reconstruction method based on domestic CPU |
| CN114398304A (en) * | 2022-03-01 | 2022-04-26 | 山西银河电子设备厂 | Method for solving SRIO interface blocking |
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