CN113626363A - Multi-bus architecture device facing micro-nano satellite-borne computer and control method thereof - Google Patents
Multi-bus architecture device facing micro-nano satellite-borne computer and control method thereof Download PDFInfo
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Abstract
The invention provides a multi-bus architecture device facing a micro-nano satellite-borne computer and a control method thereof: the multi-bus architecture device comprises a processing unit, an antifuse FPGA and a monitoring unit; the device has three working states: a normal operating state, a fault operating state and a full-speed operating state; the invention realizes the fusion and sharing of multi-bus data of the system, optimizes resource allocation by matching high and low speed buses, reduces system power consumption, improves system resource utilization rate and system reliability, creates bridging links inside a host and a backup machine and between the host and a backup machine, and realizes the information interaction and fault-tolerant function of the system by using the cross backup of the buses; the problem that various bus data of the existing satellite-borne computer cannot be effectively interacted is solved, the bridge link can be directly used for information interaction between the host computer and the standby computer, and the integration level of the system is improved.
Description
Technical Field
The invention belongs to on-satellite data transmission and processing, and particularly relates to a multi-bus architecture device for a micro-nano on-board computer and a control method thereof.
Background
In recent years, as the space exploration is continuously promoted, the research and development of the space technology are continuously advanced, and the space task is gradually diversified and complicated, under the background, the functions of the satellite system are continuously improved, so that the data interaction and the information network between the processors on the satellite and between the onboard computer and the load become more complicated, and higher system performance is required to complete the determined task. In the face of the situations of large data volume and complex environment, the problems of rapidity and reliability of on-satellite data transmission and processing need to be solved, which puts higher requirements on an on-satellite bus responsible for on-satellite data transmission. The core of the micro/nano satellite is an on-board computer which is a master node of a data bus network, the on-board computer connects various devices and subsystems on the satellite together by using a data bus to perform data transmission and management, provides services such as data support, information management and the like for all loads of the micro/nano satellite, and is the core of on-board data processing.
With the development of the micro-nano satellite technology, the number of tasks carried by the micro-nano satellite is more and more, and data required to be processed is more and more huge, so that higher requirements are provided for the bus performance of the satellite-borne computer, and the development of the satellite-borne computer system is gradually limited in the aspects of reliability and performance by the bus architecture of the traditional satellite-borne computer.
Disclosure of Invention
Aiming at solving the problems, the invention provides a multi-bus architecture device facing a micro-nano spaceborne computer and a control method thereof, which realize the fusion and sharing of multi-bus data of a system, optimize resource allocation by matching use of high and low speed buses, reduce the power consumption of the system and improve the utilization rate of system resources and the reliability of the system.
The invention is realized by the following method:
a multi-bus architecture device for a micro-nano satellite-borne computer comprises:
the multi-bus architecture device comprises a processing unit, an antifuse FPGA and a monitoring unit;
the processing unit comprises an ARM processor, a DSP processor and a ZYNQ processor;
the antifuse FPGA is communicated with the ARM processor, the DSP processor and the ZYNQ processor through an EBI bus, an EMIF bus and a RapidIO high-speed bus respectively;
the monitoring unit is integrated in the antifuse FPGA and comprises an interface module, a communication module, a data processing module and a system monitoring module; and switching high and low speed buses, and fusing, cross-backing and interacting data.
Further, the air conditioner is provided with a fan,
three processors ARM, DSP and ZYNQ of the processing unit are connected to a CAN bus on the satellite at the same time;
the three processors are mutually connected through an asynchronous parallel RS422 bus and a GPIO interface to realize point-to-point communication;
the data format of the RS422 bus adopts a ModBus protocol, and the data transmission rate is 20 Mbps;
and a UPP communication channel is designed between the DSP and the ZYNQ, and the maximum data transmission rate is 1.17 Gbps.
Further, the air conditioner is provided with a fan,
the antifuse FPGA clock frequency adopts 100 MHz; the bus comprises data lines, address lines and control lines;
the anti-fuse FPGA and the ARM are communicated by adopting an EBI bus, an EBI interface is an external memory bus of the ARM, and the ARM accesses a register of an internal designated address of the FPGA through an address line; configuring an EBI interface into an SMC mode, wherein the bit width of an address line of an EBI bus is 24 bits, the bit width of a data line is 16 bits, the ARM clock frequency adopts 100MHz, 10 EBI clocks are adopted, 3 clocks are established, 2 clocks are kept, 5 clocks are gated, and the highest data transmission rate reaches 160 Mbps; when ARM reading operation is carried out, address information is output by an address line firstly, then FPGA is enabled through chip selection, and finally data of a data line is valid after a reading signal is valid for one clock cycle;
EMIF bus communication is adopted between the anti-fuse FPGA and the DSP, the address bit width of the EMIF bus is 20 bits, the data bit width is 64 bits, the DSP clock frequency adopts 100MHz, 10 EMIF clocks are adopted, 3 clocks are established, 2 clocks are kept, 5 clocks are gated, and the highest data transmission rate is 640 Mbps; seamless connection is established with the FPGA through an EMIF interface;
RapidIO high-speed bus communication is adopted between the antifuse FPGA and the ZYNQ, the ZYNQ clock frequency is 125MHz, the transmission rate of Rapid IO is selected to be single-channel 1.25Gbps, and data transmission is completed through read operation, write operation and stream write operation of a serial Rapid IO protocol.
Further, the air conditioner is provided with a fan,
the interface module is used for realizing data interaction between the processing unit and the communication module; the interface module establishes bus connection with the three processors ARM, DSP and ZYNQ in a bus communication mode of the external memory;
when high-speed data transmission is needed, a high-speed bus is adopted; under the condition that high-speed data transmission is not needed or the data pressure is small or idle, the bus module is closed or a low-level bus is adopted to reduce the power consumption;
the communication module completes the logic compiling of a communication protocol bottom layer and is used for realizing external bus communication, and the bus communication comprises an EBI bus, an EMIF bus, a DDR control bus, an RS422 bus and a CAN bus;
the CAN bus is used as a primary bus on the satellite to realize information interaction between the host and the standby machine; the RS422 bus is used as a secondary low-speed bus for meeting the single machine with the requirement of the on-satellite asynchronous serial port communication; the ARM, the DSP and the ZYNQ respectively adopt an EBI bus, an EMIF bus and a RapidIO bus as a secondary high-speed bus to realize communication with the antifuse FPGA;
the data processing module realizes data acquisition, data integration and data transmission;
the data processing module firstly acquires data on the bus, arranges the data formats, integrates the acquired data, and sends the arranged data to the communication module again according to requirements, so that high-speed data transmission of different data formats among different processors is realized;
the system monitoring module is used for monitoring the states of each processor and the external bus;
when the processor is monitored to have a fault, closing an external bus of the processor, interacting with a standby machine, and starting data of a processor of the standby machine; and when the external bus is monitored to have a fault, starting the standby machine to exchange the external bus data, and realizing data interaction with each processor of the host machine.
A control method applied to a multi-bus architecture device facing a micro-nano spaceborne computer comprises the following steps:
the host machine is the same as the anti-fuse FPGA of the standby machine; the anti-fuse FPGA of the host and the backup respectively receives data of the three processors and data of an external bus through respective high-speed buses, and the data sharing of the anti-fuse FPGA of the host and the backup is realized through an inter-bridge link between the anti-fuse FPGA of the host and the backup;
the multi-bus architecture device has three working states: normal operating condition, fault operating condition and full speed operating condition.
Further, the air conditioner is provided with a fan,
and (3) normal working state:
after receiving ARM, DSP and ZYNQ data, the anti-fuse FPGA sorts and backs up the data through an internal data processing module to complete data fusion;
when the ARM, the DSP and the ZYNQ need data transmitted by other processors, the antifuse FPGA converts the data and serves as a bridge processor to realize data transmission among different buses of different processors;
the main machine is in a normal working state, the standby machine is in a hot backup state, the monitoring unit of the main machine and the standby machine performs cross backup on the key data of the bus, namely the monitoring unit of the main machine and the standby machine mutually backs up the external link data and the key data of the processor and prepares to enter a fault working state or a full-speed working state at any time.
Further, the air conditioner is provided with a fan,
and (3) fault working state:
when the bus fails and cannot work, the system can automatically identify the failed bus and convert the system into a failure mode.
When the host computer fails to the external link, the monitoring unit of the standby computer enters a failure mode, the monitoring units of the standby computer share the external link of the standby computer, the recombination of the external link of the standby computer, the monitoring units of the standby computer and the processing units of the standby computer is realized, and the fault tolerance is completed;
when one or more buses of the ARM, the DSP and the ZYNQ of the host are damaged, a processor damaged by the corresponding host in the monitoring unit and the processing unit of the standby machine enters a fault mode, and the monitoring units of the main machine and the standby machine can share the normal ARM, the DSP and the ZYNQ of the standby machine, so that system recombination is realized, and fault tolerance is completed;
when the corresponding processor of the standby processing unit is damaged, the data is transmitted to the processors of the rest processing units through data fusion and cross backup of bus data of the monitoring unit, and the rest processors are executed instead, so that the fault tolerance of the system is realized.
Further, the air conditioner is provided with a fan,
when the system needs to work at full speed in a full-speed working state, the standby machine starts to work with the host in a cooperative mode, all buses are controlled through the FPGA of the host and the standby machine to perform data interaction in a cooperative mode, and the performance of the system is improved by nearly two times.
The invention has the beneficial effects
(1) The invention realizes the fusion and sharing of the multi-bus data of the system, optimizes the resource allocation by the matching use of the high-speed bus and the low-speed bus, reduces the power consumption of the system, and improves the resource utilization rate and the reliability of the system;
(2) the invention establishes bridging links in the host and the backup machine and between the host and the backup machine, and realizes the information interaction and fault tolerance functions of the system by using the cross backup of the bus;
(3) compared with a system which does not adopt the scheme, the scheme can solve the problem that various bus data of the existing satellite-borne computer cannot be effectively interacted, and the bridge link can be directly used for information interaction between the main machine and the standby machine, so that the integration level of the system is improved;
(4) when the bus has a fault, the invention utilizes the scheme to realize the recombination between the system bus and the processor, so that the system can continuously and effectively work, and the fault tolerance of the system is enhanced.
Drawings
FIG. 1 is a block diagram of a satellite borne multi-bus system of the present invention;
fig. 2 is a structural diagram of a satellite-borne dual-computer redundancy fault-tolerant system of the present invention.
Detailed Description
The technical solutions in the embodiments of the present invention will be clearly and completely described below with reference to the drawings in the embodiments of the present invention, and it is obvious that the described embodiments are only a part of the embodiments of the present invention, and not all of the embodiments; all other embodiments, which can be derived by a person skilled in the art from the embodiments given herein without making any creative effort, shall fall within the protection scope of the present invention.
With reference to fig. 1 to 2;
a multi-bus architecture device for a micro-nano satellite-borne computer comprises: as shown in FIG. 1;
the multi-bus architecture device comprises a processing unit, an antifuse FPGA and a monitoring unit;
the processing unit comprises an ARM processor, a DSP processor and a ZYNQ processor;
the antifuse FPGA is communicated with the ARM processor, the DSP processor and the ZYNQ processor through an EBI bus, an EMIF bus and a RapidIO high-speed bus respectively;
the monitoring unit is integrated in the antifuse FPGA and comprises an interface module, a communication module, a data processing module and a system monitoring module; and switching high and low speed buses, and fusing, cross-backing and interacting data.
Three processors ARM, DSP and ZYNQ of the processing unit are connected to a CAN bus on the satellite at the same time;
the three processors are mutually connected through an asynchronous parallel RS422 bus and a GPIO interface to realize point-to-point communication;
the data format of the RS422 bus adopts a ModBus protocol, and the data transmission rate is 20 Mbps;
and a UPP communication channel is designed between the DSP and the ZYNQ, and the maximum data transmission rate is 1.17 Gbps.
The antifuse FPGA clock frequency adopts 100 MHz; the bus comprises data lines, address lines and control lines;
the anti-fuse FPGA and the ARM are communicated by adopting an EBI bus, an EBI interface is an external memory bus of the ARM, and the ARM accesses a register of an internal designated address of the FPGA through an address line; the interface can be configured into two modes of an SMC (static Memory controller) and an SDRAM (synchronous dynamic random access Memory) controller, and because the SMC controller has simpler time sequence and is convenient for the design of an FPGA (field programmable gate array) end, the EBI interface is configured into the SMC mode;
the bit width of an address line of the EBI bus is 24 bits, the bit width of a data line is 16 bits, the ARM clock frequency adopts 100MHz, 10 EBI clocks are adopted, 3 clocks are established, 2 clocks are kept, 5 clocks are gated, and the highest data transmission rate reaches 160 Mbps; when ARM reading operation is carried out, address information is output by an address line firstly, then FPGA is enabled through chip selection, and finally data of a data line is valid after a reading signal is valid for one clock cycle; therefore, the operation sequence of the mode is simple, and the method is very suitable for the logic design of the FPGA end. The circuit design comprises a data bus, an address bus and a control bus, the ARM can access a register of an internal designated address of the FPGA through the address bus, and the communication mode greatly simplifies the complex data communication between the ARM and the FPGA.
EMIF (external Memory interface) bus communication is adopted between the anti-fuse FPGA and the DSP, the address bit width of the EMIF bus is 20 bits, the data bit width is 64 bits, the DSP clock frequency adopts 100MHz, 10 EMIF clocks are adopted, 3 clocks are established, 2 clocks are kept, 5 clocks are gated, and the highest data transmission rate is 640 Mbps; seamless connection is established with the FPGA through an EMIF interface;
RapidIO high-speed bus communication is adopted between the antifuse FPGA and the ZYNQ, and Rapid IO is a high-performance packet switching system-level interconnection standard with few pins and is mainly used as an intra-system interface between a processor and inter-board communication at a Gbps baud rate level. The ZYNQ clock frequency is 125MHz, the transmission rate of Rapid IO is selected to be single channel 1.25Gbps, and the data transmission is completed by the read operation, the write operation and the stream write operation of the serial Rapid IO protocol. The Rapid IO communications protocol is implemented using the Serial RapidIO Gen2 IP core provided by Xilinx corporation.
The interface module is used for realizing data interaction between the processing unit and the communication module; the interface module establishes bus connection with the three processors ARM, DSP and ZYNQ in a bus communication mode of the external memory;
when high-speed data transmission is needed, a high-speed bus is adopted; under the condition that high-speed data transmission is not needed or the data pressure is small or idle, the bus module is closed or a low-level bus is adopted to reduce the power consumption;
the communication module completes the logic compiling of a communication protocol bottom layer and is used for realizing external bus communication, and the bus communication comprises an EBI bus, an EMIF bus, a DDR control bus, an RS422 bus and a CAN bus;
the CAN bus is used as a primary bus on the satellite to realize information interaction between the host and the standby machine; the RS422 bus is used as a secondary low-speed bus for meeting the single machine with the requirement of the on-satellite asynchronous serial port communication; the ARM, the DSP and the ZYNQ respectively adopt an EBI bus, an EMIF bus and a RapidIO bus as a secondary high-speed bus to realize communication with the antifuse FPGA;
the data processing module realizes data acquisition, data integration and data transmission;
the data processing module firstly acquires data on the bus, arranges the data formats, integrates the acquired data, and sends the arranged data to the communication module again according to requirements, so that high-speed data transmission of different data formats among different processors is realized;
the system monitoring module is used for monitoring the states of each processor and the external bus;
when the processor is monitored to have a fault, closing an external bus of the processor, interacting with a standby machine, and starting data of a processor of the standby machine; and when the external bus is monitored to have a fault, starting the standby machine to exchange the external bus data, and realizing data interaction with each processor of the host machine.
A control method applied to a multi-bus architecture device facing a micro-nano spaceborne computer comprises the following steps: as shown in FIG. 2;
the host machine is the same as the anti-fuse FPGA of the standby machine; the anti-fuse FPGA of the host and the backup respectively receives data of the three processors and data of an external bus through respective high-speed buses, and the data sharing of the anti-fuse FPGA of the host and the backup is realized through an inter-bridge link between the anti-fuse FPGA of the host and the backup;
for example, when the bus of the ARM processor of the host computer fails, the ARM processor of the standby computer can be started, and the same processing is adopted when the DSP and the ZYNQ fail; when the host external bus fails, the host processor can be connected with the external data through the external bus of the standby machine and the inter-bridge link between the host and the standby machine, so that the possibility of failure of the whole system caused by failure of a single processor is avoided.
The multi-bus architecture device has three working states: normal operating condition, fault operating condition and full speed operating condition.
And (3) normal working state:
after receiving ARM, DSP and ZYNQ data, the anti-fuse FPGA sorts and backs up the data through an internal data processing module to complete data fusion;
when the ARM, the DSP and the ZYNQ need data transmitted by other processors, the antifuse FPGA converts the data and serves as a bridge processor to realize data transmission among different buses of different processors;
the main machine is in a normal working state, the standby machine is in a hot backup state, the monitoring unit of the main machine and the standby machine performs cross backup on the key data of the bus, namely the monitoring unit of the main machine and the standby machine mutually backs up the external link data and the key data of the processor and prepares to enter a fault working state or a full-speed working state at any time.
And (3) fault working state:
when the bus fails and cannot work, the system can automatically identify the failed bus and convert the system into a failure mode.
When the host computer fails to the external link, the monitoring unit of the standby computer enters a failure mode, the monitoring units of the standby computer share the external link of the standby computer, the recombination of the external link of the standby computer, the monitoring units of the standby computer and the processing units of the standby computer is realized, and the fault tolerance is completed;
when one or more buses of the ARM, the DSP and the ZYNQ of the host are damaged, a processor damaged by the corresponding host in the monitoring unit and the processing unit of the standby machine enters a fault mode, and the monitoring units of the main machine and the standby machine can share the normal ARM, the DSP and the ZYNQ of the standby machine, so that system recombination is realized, and fault tolerance is completed;
when the corresponding processor of the standby processing unit is damaged, the data is transmitted to the processors of the rest processing units through data fusion and cross backup of bus data of the monitoring unit, and the rest processors are executed instead, so that the fault tolerance of the system is realized.
In a normal working state, the standby machine is in a warm standby state; when a fault occurs, a part of or all modules of the standby machine are started to work, specifically the fault state is described above.
The full-speed working state: when the system needs to work at full speed, the standby machine starts to work with the host machine in a cooperative mode, all buses are controlled through the FPGA of the host machine and the standby machine to perform data interaction in a cooperative mode, and the performance of the system is improved by nearly two times.
The multi-bus architecture device facing the micro-nano spaceborne computer and the control method thereof are introduced in detail, the principle and the implementation mode of the invention are explained, and the explanation of the embodiment is only used for helping to understand the method and the core idea of the invention; meanwhile, for a person skilled in the art, according to the idea of the present invention, there may be variations in the specific embodiments and the application scope, and in summary, the content of the present specification should not be construed as a limitation to the present invention.
Claims (8)
1. A multi-bus architecture device facing a micro-nano satellite-borne computer is characterized in that:
the multi-bus architecture device comprises a processing unit, an antifuse FPGA and a monitoring unit;
the processing unit comprises an ARM processor, a DSP processor and a ZYNQ processor;
the antifuse FPGA is communicated with the ARM processor, the DSP processor and the ZYNQ processor through an EBI bus, an EMIF bus and a RapidIO high-speed bus respectively;
the monitoring unit is integrated in the antifuse FPGA and comprises an interface module, a communication module, a data processing module and a system monitoring module; and switching high and low speed buses, and fusing, cross-backing and interacting data.
2. The multi-bus architecture device of claim 1, wherein:
three processors ARM, DSP and ZYNQ of the processing unit are connected to a CAN bus on the satellite at the same time;
the three processors are mutually connected through an asynchronous parallel RS422 bus and a GPIO interface to realize point-to-point communication;
the data format of the RS422 bus adopts a ModBus protocol, and the data transmission rate is 20 Mbps;
and a UPP communication channel is designed between the DSP and the ZYNQ, and the maximum data transmission rate is 1.17 Gbps.
3. The multi-bus architecture device of claim 1, wherein:
the antifuse FPGA clock frequency adopts 100 MHz; the bus comprises data lines, address lines and control lines;
the anti-fuse FPGA and the ARM are communicated by adopting an EBI bus, an EBI interface is an external memory bus of the ARM, and the ARM accesses a register of an internal designated address of the FPGA through an address line; configuring an EBI interface into an SMC mode, wherein the bit width of an address line of an EBI bus is 24 bits, the bit width of a data line is 16 bits, the ARM clock frequency adopts 100MHz, 10 EBI clocks are adopted, 3 clocks are established, 2 clocks are kept, 5 clocks are gated, and the highest data transmission rate reaches 160 Mbps; when ARM reading operation is carried out, address information is output by an address line firstly, then FPGA is enabled through chip selection, and finally data of a data line is valid after a reading signal is valid for one clock cycle;
EMIF bus communication is adopted between the anti-fuse FPGA and the DSP, the address bit width of the EMIF bus is 20 bits, the data bit width is 64 bits, the DSP clock frequency adopts 100MHz, 10 EMIF clocks are adopted, 3 clocks are established, 2 clocks are kept, 5 clocks are gated, and the highest data transmission rate is 640 Mbps; seamless connection is established with the FPGA through an EMIF interface;
RapidIO high-speed bus communication is adopted between the antifuse FPGA and the ZYNQ, the ZYNQ clock frequency is 125MHz, the transmission rate of Rapid IO is selected to be single-channel 1.25Gbps, and data transmission is completed through read operation, write operation and stream write operation of a serial Rapid IO protocol.
4. The multi-bus architecture device of claim 1, wherein:
the interface module is used for realizing data interaction between the processing unit and the communication module; the interface module establishes bus connection with the three processors ARM, DSP and ZYNQ in a bus communication mode of the external memory;
when high-speed data transmission is needed, a high-speed bus is adopted; under the condition that high-speed data transmission is not needed or the data pressure is small or idle, the bus module is closed or a low-level bus is adopted to reduce the power consumption;
the communication module completes the logic compiling of a communication protocol bottom layer and is used for realizing external bus communication, and the bus communication comprises an EBI bus, an EMIF bus, a DDR control bus, an RS422 bus and a CAN bus;
the CAN bus is used as a primary bus on the satellite to realize information interaction between the host and the standby machine; the RS422 bus is used as a secondary low-speed bus for meeting the single machine with the requirement of the on-satellite asynchronous serial port communication; the ARM, the DSP and the ZYNQ respectively adopt an EBI bus, an EMIF bus and a RapidIO bus as a secondary high-speed bus to realize communication with the antifuse FPGA;
the data processing module realizes data acquisition, data integration and data transmission;
the data processing module firstly acquires data on the bus, arranges the data formats, integrates the acquired data, and sends the arranged data to the communication module again according to requirements, so that high-speed data transmission of different data formats among different processors is realized;
the system monitoring module is used for monitoring the states of each processor and the external bus;
when the processor is monitored to have a fault, closing an external bus of the processor, interacting with a standby machine, and starting data of a processor of the standby machine; and when the external bus is monitored to have a fault, starting the standby machine to exchange the external bus data, and realizing data interaction with each processor of the host machine.
5. A control method applied to a multi-bus architecture device facing a micro-nano spaceborne computer is characterized in that:
the host machine is the same as the anti-fuse FPGA of the standby machine; the anti-fuse FPGA of the host and the backup respectively receives data of the three processors and data of an external bus through respective high-speed buses, and the data sharing of the anti-fuse FPGA of the host and the backup is realized through an inter-bridge link between the anti-fuse FPGA of the host and the backup;
the multi-bus architecture device has three working states: normal operating condition, fault operating condition and full speed operating condition.
6. The control method according to claim 5, characterized in that:
and (3) normal working state:
after receiving ARM, DSP and ZYNQ data, the anti-fuse FPGA sorts and backs up the data through an internal data processing module to complete data fusion;
when the ARM, the DSP and the ZYNQ need data transmitted by other processors, the antifuse FPGA converts the data and serves as a bridge processor to realize data transmission among different buses of different processors;
the main machine is in a normal working state, the standby machine is in a hot backup state, the monitoring unit of the main machine and the standby machine performs cross backup on the key data of the bus, namely the monitoring unit of the main machine and the standby machine mutually backs up the external link data and the key data of the processor and prepares to enter a fault working state or a full-speed working state at any time.
7. The control method according to claim 5, characterized in that:
and (3) fault working state:
when the bus fails and cannot work, the system can automatically identify the failed bus and convert the system into a failure mode.
When the host computer fails to the external link, the monitoring unit of the standby computer enters a failure mode, the monitoring units of the standby computer share the external link of the standby computer, the recombination of the external link of the standby computer, the monitoring units of the standby computer and the processing units of the standby computer is realized, and the fault tolerance is completed;
when one or more buses of the ARM, the DSP and the ZYNQ of the host are damaged, a processor damaged by the corresponding host in the monitoring unit and the processing unit of the standby machine enters a fault mode, and the monitoring units of the main machine and the standby machine can share the normal ARM, the DSP and the ZYNQ of the standby machine, so that system recombination is realized, and fault tolerance is completed;
when the corresponding processor of the standby processing unit is damaged, the data is transmitted to the processors of the rest processing units through data fusion and cross backup of bus data of the monitoring unit, and the rest processors are executed instead, so that the fault tolerance of the system is realized.
8. The control method according to claim 5, characterized in that:
when the system needs to work at full speed in a full-speed working state, the standby machine starts to work with the host in a cooperative mode, all buses are controlled through the FPGA of the host and the standby machine to perform data interaction in a cooperative mode, and the performance of the system is improved by nearly two times.
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