CN117149674A - Multi-host PCIe (peripheral component interconnect express) interconnection structure for embedded real-time scene - Google Patents
Multi-host PCIe (peripheral component interconnect express) interconnection structure for embedded real-time scene Download PDFInfo
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- CN117149674A CN117149674A CN202311062071.XA CN202311062071A CN117149674A CN 117149674 A CN117149674 A CN 117149674A CN 202311062071 A CN202311062071 A CN 202311062071A CN 117149674 A CN117149674 A CN 117149674A
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- pcie
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- pcie switch
- switch chip
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- 230000002093 peripheral effect Effects 0.000 title description 2
- 230000005540 biological transmission Effects 0.000 claims abstract description 7
- 238000012546 transfer Methods 0.000 claims description 2
- 239000004744 fabric Substances 0.000 claims 7
- 230000006870 function Effects 0.000 description 5
- 230000009286 beneficial effect Effects 0.000 description 2
- 238000010586 diagram Methods 0.000 description 2
- 230000000694 effects Effects 0.000 description 2
- 238000012423 maintenance Methods 0.000 description 2
- 238000012986 modification Methods 0.000 description 2
- 230000004048 modification Effects 0.000 description 2
- 238000013507 mapping Methods 0.000 description 1
- 238000013519 translation Methods 0.000 description 1
Classifications
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
- G06F13/10—Program control for peripheral devices
- G06F13/12—Program control for peripheral devices using hardware independent of the central processor, e.g. channel or peripheral processor
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
- G06F13/38—Information transfer, e.g. on bus
- G06F13/40—Bus structure
- G06F13/4063—Device-to-bus coupling
- G06F13/4068—Electrical coupling
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
- G06F13/38—Information transfer, e.g. on bus
- G06F13/42—Bus transfer protocol, e.g. handshake; Synchronisation
- G06F13/4282—Bus transfer protocol, e.g. handshake; Synchronisation on a serial bus, e.g. I2C bus, SPI bus
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F2213/00—Indexing scheme relating to interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
- G06F2213/0026—PCI express
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- Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
- Y02D—CLIMATE CHANGE MITIGATION TECHNOLOGIES IN INFORMATION AND COMMUNICATION TECHNOLOGIES [ICT], I.E. INFORMATION AND COMMUNICATION TECHNOLOGIES AIMING AT THE REDUCTION OF THEIR OWN ENERGY USE
- Y02D10/00—Energy efficient computing, e.g. low power processors, power management or thermal management
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- Theoretical Computer Science (AREA)
- General Engineering & Computer Science (AREA)
- Physics & Mathematics (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Hardware Redundancy (AREA)
Abstract
The application relates to the technical field of embedded systems and devices, and provides a multi-host PCIe interconnection structure for an embedded real-time scene, which comprises the following components: PCIe switch chip connected with one or more bridge chip slave devices; the main processor is respectively connected with the PCIe switch chip, performs data transmission through the PCIe switch chip and is respectively connected with one or more processor slave devices; and the FPGA is respectively connected with the plurality of main processors. The application solves the technical problems of low utilization rate of PCIE equipment and insufficient system reliability in the prior art, realizes a multi-master equipment architecture based on PCIE bus, and can maintain normal operation of standby slave equipment when RC fails, thereby increasing the reliability of the system.
Description
Technical Field
The application relates to the technical field of embedded systems and devices, in particular to a multi-host PCIe interconnection structure for an embedded real-time scene.
Background
In the information security era, some electronic devices still have risks and hazards in terms of technology and maintenance. In the prior art, the PCIe architecture has only one HOST bridge, one PCIe bus domain can be managed by only one PCIe controller, and a general PCIe device has only one PF (Physical Function ) and can only be managed by the PCIe controller of one HOST, so that a plurality of HOSTs cannot be supported to access one PCIe device at the same time, and the PCIe device has low utilization rate.
Disclosure of Invention
In view of this, the present application provides a multi-host PCIe interconnect structure for embedded real-time scenarios, so as to solve the technical problems of low PCIe device utilization and insufficient system reliability in the prior art.
The application provides a multi-host PCIe interconnection structure for an embedded real-time scene, which comprises the following components: a PCIe switch chip connected with one or more bridge chip slave devices; the plurality of main processors are respectively connected with the PCIe switch chip, the plurality of main processors perform data transmission through the PCIe switch chip, and the plurality of main processors are respectively connected with one or more processor slave devices; the FPGA is single and is respectively connected with a plurality of main processors.
Further, the PCIe switch chip includes a doorbell register and a note register, and a port of the PCIe switch chip has a function of configuring a non-transparent bridge mode.
Further, the main processor is an FT2000/4 type multi-core processor.
Furthermore, the PCIe switch chip is SM8619 type.
Further, the single main processor accesses the processor slave devices connected with the rest main processors through the PCIe switch chip.
Furthermore, the PCIe switch chip, the main processor, the processor slave device and the bridge chip slave device perform data transmission through DMA.
Compared with the prior art, the at least one technical scheme adopted by the application has the beneficial effects that at least the beneficial effects comprise: the application provides a multi-host PCIe interconnection structure for an embedded real-time scene, which adopts a multi-host redundancy processor architecture based on PCIe, thereby not only utilizing the self advantages of the PCIE architecture, but also realizing the functions of fault and load sharing. When a fault occurs, the standby processor slave can also maintain normal operation, and the reliability of the system is increased.
Drawings
In order to more clearly illustrate the technical solutions of the embodiments of the present application, the drawings that are needed in the embodiments will be briefly described below, and it is obvious that the drawings in the following description are only some embodiments of the present application, and that other drawings can be obtained according to these drawings without inventive effort for a person skilled in the art.
FIG. 1 is a schematic diagram of a multi-host PCIe interconnect structure for embedded real-time scenarios provided in the background section of the present application;
fig. 2 is a schematic diagram of a PCIe switch chip according to an embodiment of the present application.
Detailed Description
Embodiments of the present application will be described in detail below with reference to the accompanying drawings.
Other advantages and effects of the present application will become apparent to those skilled in the art from the following disclosure, which describes the embodiments of the present application with reference to specific examples. It will be apparent that the described embodiments are only some, but not all, embodiments of the application. The application may be practiced or carried out in other embodiments that depart from the specific details, and the details of the present description may be modified or varied from the spirit and scope of the present application. It should be noted that the following embodiments and features in the embodiments may be combined with each other without conflict. All other embodiments, which can be made by those skilled in the art based on the embodiments of the application without making any inventive effort, are intended to be within the scope of the application.
The application provides a multi-host PCIe interconnection structure for an embedded real-time scene, which adopts a multi-host redundancy processor architecture based on PCIe, thereby not only utilizing the own advantages of the PCIe architecture, but also realizing the functions of fault and load sharing. When a fault occurs, the standby equipment can also maintain normal operation, and the reliability of the system is increased.
The application provides a multi-host PCIe interconnection structure for an embedded real-time scene, which comprises the following components: a PCIe switch chip (PCIE SWITCH) to which one or more bridge chip slave devices are connected; the plurality of main processors are respectively connected with the PCIe switch chip, the plurality of main processors perform data transmission through the PCIe switch chip, and the plurality of main processors are respectively connected with one or more processor slave devices; the FPGA is single and is respectively connected with a plurality of main processors.
Specifically, in this embodiment, the main processor, i.e., the RC-terminal is a multi-core processor, a plurality of multi-core processors are used as multi-host terminals, and the PCIe switch chip is a core switch network. As shown in FIG. 1, the 2 RC terminals are preferably FT2000/4 processors. The plurality of main processors share the FPGA for sharing register resources. The plurality of EP devices constitute a processor slave. Processor slave device types include, but are not limited to, nvme memory cards (electronic disk), 1394 bus, FC bus, etc. In fig. 1, two main devices are connected with a PCIe switch through PCIe, and the two main devices are respectively connected with an FPGA, and memory sharing and data synchronization are performed in the FPGA. The PCIe switch is connected to the bridge chip slave device through a PCIe bus.
Further, the multiple master processors can be used as multiple master nodes to access the processor slave devices, and the EP devices are mounted on the PCIe switch. PCIe switches in this embodiment include, but are not limited to, SM8619 and other like functional chips.
Further, the single main processor accesses the processor slave devices connected with the rest main processors through the PCIe switch chip.
Further, data transmission is performed among the PCIe switch chip, the master processor, the processor slave device, and the bridge chip slave device through DMA (direct memory access).
Specifically, the prior art PCIe architecture has only one root, denoted RC, which is responsible for discovering the entire PCIe topology, which makes it difficult for conventional PCIe architectures to build multi-host systems. In this embodiment, a multi-master PCIe architecture is designed, and the master processor and the slave processor may be mutually backed up by configuring the master processor to be connected to the plurality of slave processors, so as to increase reliability of the system. When one processor fails, the other processor may continue to perform tasks as a backup. Through the multi-master PCIe architecture, multiple processors may be made to share access to multiple EP devices. The efficiency of use of EP equipment can be increased.
Further, as shown in fig. 2, the PCIe switch chip includes a doorbell register and a note register, and a port of the PCIe switch chip has a function of configuring a non-transparent bridge mode (NT mode). PCIe switches may be configured in a transparent bridge mode and a non-transparent bridge mode. The address space of the two PCIe domains is isolated by using the NT mode.
Further, the main processor is an FT2000/4 type multi-core processor.
Specifically, 2 FT2000/4 processors are configured as RC terminals. The 2X 4 ports of SM8619 are configured in a non-transparent bridge mode, serving to isolate the address space of and connect two PCIe domains. Interrupt is transmitted in two PCIe domains through the doorbell register, and cross-domain data reading and writing are performed through the scratch register. Cross-domain address access is performed through address mapping and direct address translation. Address access between 2 PCIe domains is implemented.
Furthermore, the PCIe switch chip is SM8619 type. The PCIe switch is an information switching center of the PCIe switching network. In this embodiment, the switch employs SM8619, the SM8619 having 16Lane, preferably, the 16Lane is configured as 2X 4 and 8X 1. Wherein 2X 4 are connected with 2 Feiteng main processors, 8X 1 are connected with a plurality of EP devices.
Further, all ports of the PCIe switch may be powered on and powered off of the endpoint device without removing power.
The multi-host PCIe interconnection structure for the embedded real-time scene provided by the embodiment can normally work at a severe temperature (-55- +70 ℃).
The application realizes the following technical effects through the above embodiments:
the multi-host PCIe interconnection structure for the embedded real-time scene can normally work at a severe temperature, and avoids risks and hidden dangers in technical and maintenance aspects; through designing a multi-master architecture based on a PCIe bus, when RC fails, the standby processor slave equipment can also maintain normal operation, so that the reliability of the system is improved; by using multiple devices to realize the functions of fault transfer and load sharing, under the architecture of multiple main devices, high-speed data transmission can be performed between nodes through DMA.
The above description is only of the preferred embodiments of the present application and is not intended to limit the present application, and various modifications and variations can be made to the embodiments of the present application by those skilled in the art. Any modification, equivalent replacement, improvement, etc. made within the spirit and principle of the present application should be included in the protection scope of the present application.
Claims (6)
1. A multi-host PCIe interconnect fabric for embedded real-time scenarios, the fabric comprising:
a PCIe switch chip connected with one or more bridge chip slave devices;
the plurality of main processors are respectively connected with the PCIe switch chip, the plurality of main processors perform data transmission through the PCIe switch chip, and the plurality of main processors are respectively connected with one or more processor slave devices;
the FPGA is single and is respectively connected with a plurality of main processors.
2. The multi-host PCIe interconnect fabric for embedded real time scenarios of claim 1, wherein the PCIe switch chip comprises doorbell registers and scratch registers, and wherein ports of the PCIe switch chip have functionality to configure non-transparent bridge modes.
3. The multi-host PCIe interconnect fabric for embedded real-time scenes of claim 1, wherein the host processor is an FT2000/4 type multi-core processor.
4. The multi-host PCIe interconnect fabric for embedded real-time scenarios of claim 1, wherein the PCIe switch chip is of the SM8619 type.
5. The multi-host PCIe interconnect fabric for embedded real time scenarios of claim 1 wherein a single said master processor accesses the processor slaves connected to the remaining master processors through PCIe switch chips.
6. The multi-host PCIe interconnect fabric for embedded real time scenarios of claim 1, wherein PCIe switch chips, master processors, processor slaves, bridge chip slaves are DMA-enabled for data transfer.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202311062071.XA CN117149674A (en) | 2023-08-22 | 2023-08-22 | Multi-host PCIe (peripheral component interconnect express) interconnection structure for embedded real-time scene |
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| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202311062071.XA CN117149674A (en) | 2023-08-22 | 2023-08-22 | Multi-host PCIe (peripheral component interconnect express) interconnection structure for embedded real-time scene |
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| CN117149674A true CN117149674A (en) | 2023-12-01 |
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| CN202311062071.XA Pending CN117149674A (en) | 2023-08-22 | 2023-08-22 | Multi-host PCIe (peripheral component interconnect express) interconnection structure for embedded real-time scene |
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Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN117743240A (en) * | 2024-02-19 | 2024-03-22 | 井芯微电子技术(天津)有限公司 | PCIe bridge device with transparent and non-transparent modes |
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2023
- 2023-08-22 CN CN202311062071.XA patent/CN117149674A/en active Pending
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN117743240A (en) * | 2024-02-19 | 2024-03-22 | 井芯微电子技术(天津)有限公司 | PCIe bridge device with transparent and non-transparent modes |
| CN117743240B (en) * | 2024-02-19 | 2024-04-19 | 井芯微电子技术(天津)有限公司 | PCIe bridge device with transparent and non-transparent modes |
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