CN105279133B - VPX Parallel DSP Signal transacting board analysis based on SoC on-line reorganizations - Google Patents
VPX Parallel DSP Signal transacting board analysis based on SoC on-line reorganizations Download PDFInfo
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Abstract
The invention discloses a kind of VPX Parallel DSP Signal transacting board analysis based on SoC on-line reorganizations, the level SoC controllers using fpga chip as plate, two panels dsp chip is its main operational chip of digital signal panel card.When actual disposition dsp chip, can be by carrying out hardware reset and start-up mode switching to DSP as the FPGA of SoC controllers, the dynamic recognition of operation code is completed using gigabit Ethernet, the flexibility ratio and real-time during Digital Signal Processing is greatly improved.SRIO X4 that dsp chip is transmitted by VPX interfaces, two kinds of high-speed serial bus signals of gigabit Ethernet, and repack by PCIE exchange chips the PCIE X2 high-speed serial bus signals of forwarding, receive pending data-signal and control instruction；Or the gigabit Ethernet protocol signal of external equipment is received by RJ45 network interfaces.
Description
Technical field
The invention belongs to digital signal processing technique field, more specifically, it is related to a kind of based on SoC on-line reorganizations
VPX Parallel DSP Signal transacting board analysis.
Background technology
As relevant treatment algorithm is continued to develop in digital processing field, its algorithm complex is complicated all the more,
The operand asked is improved into geometry multiple.By taking aircraft load as an example, aircraft integration signal handles payload platform according to each
Comprehensive task demand is planted, passes through the flexible hardware module that each is unified to internal system and carries out online dynamic configuration software/hardware reality
The existing different task function including detections of radar, telemetry communication, image procossing, navigator fix, photodetection etc..At signal
Reason system needs to call respective algorithms to realize these above-mentioned functions, and this requires back-end digital signal processing module is provided powerful
High-precision signal processing and data throughput capabilities, therefore design one kind possesses igh-speed wire-rod production line and Large Volume Data handling capacity
Signal transacting board analysis become urgent demand.
As embedded framework is continued to develop, new standard is constantly suggested.By taking VPX standards as an example, VPX is by VITA groups
Knit formulation to meet high reliability under adverse circumstances, high bandwidth requirement senior embedded platform bus standard of future generation,
With the features such as transmission bandwidth is high, transmission reliability is high, interconnection architecture flexibly can configure, it is more and more used in such as boat
In embedded signal processing system under the conditions of the particular job such as empty space flight.SRIO (Serial defined in VPX buses
RapidIO), three kinds of high-speed serial bus such as PCIe (PCI Express), 10Gb Ethernet, meet the high speed of different application
Data communication requirements.But, the external high-speed bus of current signal transacting support plate identical functions of the majority based on VPX buses is all only
There is provided one group, the problem of not accounting for data transmission bus redundancy backup causes it to be worked under the conditions of extreme environment
Reliability is difficult to ensure that.
At present, traditional embedded information processing platform typically uses FPGA+DSP design framework, and it is preferably utilized
Advantage in the flexible design meanses of fpga chip and abundant hardware logic resource and the processing of FPGA parallel data.Together
When, the monokaryon dominant frequency of high-end dsp chip has also reached 1GHz or so, and is integrated with conventional bus resource, possesses and preferably believes
Number disposal ability.But such design remains problems：
(1) so that FPGA is the processing platform of kernel processor chip as an example, although high-end fpga chip there is provided larger and
Row signal transacting bandwidth, but its is with high costs, Digital Signal Processing operational capability is not as good as dsp chip.At the same time, by monokaryon
Dsp chip is also difficult to provide enough signal throughputs as the design of main computing chip, and its ability is even more to be often limited to lead to
Believe the limited bandwidth of link.And FPGA+DSP design framework is all often multiple FPGA and the combination of multi-disc monokaryon dsp chip
Mentality of designing, certainly will so increase the area of board, not meet the trend of current demand signal processing system miniaturization, therefore traditional
Design framework is often limited to the requirement in system dimension space, and its mentality of designing can do nothing to help current high speed, Large Copacity number
The present situation of word signal transacting.
(2) traditional digital signal panel card uses parallel bus as the data link between processor, such
Design has that transmission rate is low, processor data throughput is small,.
(3) communication between traditional Signal transacting board analysis and system host computer typically use serial ports, USB2.0,100,000,000 with
The too single-protocol interface such as net, these agreements have the shortcomings that transmission rate is slow or transmission range is short, equally influence data transfer
With ordering the real-time issued.
(4) traditional digital signal panel card does not often consider that online flexibility can match somebody with somebody function, i.e. signal again in design
Process plate, using to the modification of the dynamic of object code, can not realize the dynamic of dsp chip resource according to the difference of analyzing and processing task
State is reconstructed and is multiplexed, therefore the flexibility of classical signal processing platform is more short of.
(5) traditional Signal transacting board analysis does not often have preliminary data link, and the design of shortage redundancy, which is often resulted in, is
The deficiency of stability of uniting and reliability.
In summary, traditional embedded information processing platform is difficult to take into account dimension volume and performance, exists many congenital
The design obstacle gone beyond of defect and being difficult to.
The content of the invention
It is an object of the invention to overcome the deficiencies of the prior art and provide a kind of VPX based on SoC on-line reorganizations is parallel
DSP Signal transacting board analysis, using the design framework of " SoC+ two CSTRs ", the level SoC controllers using FPGA as plate, and pass through FPGA
Peripheral HW High Way is controlled to DSP Signal transacting board analysis.
For achieving the above object, a kind of VPX Parallel DSP Signal transacting board analysis based on SoC on-line reorganizations of the present invention,
It is characterised in that it includes：
One VPX interfaces, including VPX P0 interfaces, VPX P1 interfaces and VPX P2 interfaces, for DSP Signal transacting board analysis with
The connection of outside master control interchanger plate and FPGA Signal Pretreatment plates, and provide input power for DSP Signal transacting board analysis
Interface；
Described VPX P0 interfaces include input power interface and system signal interface；
Described VPX P1 interfaces include datum plane interface, control plane interface, extension plane interface and user and made by oneself
Adopted interface；Wherein, datum plane interface provides two SRIO x4 high-speed serial bus interfaces, and DSP1, DSP2 two is connected respectively
Main computing master chip, and connection FPGA Signal Pretreatment plates, for the signal of outside FPGA Signal Pretreatments plate to be input to
DSP1、DSP2；Control plane interface provides two gigabit Ethernet EBIs, and two main computings of DSP1, DSP2 are connected respectively
Master chip, and connection master control interchanger plate, for by control signal and online reconfiguration of the master control interchanger plate to dsp chip
Order is transmitted to dsp chip；Extend plane interface and one PCIe x4 high-speed serial bus interface is provided, and be connected to PCIE exchanges
Chip, the PCIE protocol signals for master control interchanger plate to be used are synchronized to PCIE exchange chips；Use in VPX P1 interfaces
Family self defined interface provides two asynchronous serial port interfaces, and DSP1, DSP2 are met respectively, main control switchboard and the tune of dsp chip is used as
Try mouth；
Described VPX P2 interfaces are used as User Defined interface；VPX P2 interfaces provide 32 pairs of differential signal line interfaces and
8 road single-ended signal line interfaces；Differential signal line interface is connected to FPGA Soc controllers, and single-ended signal line interface is connected to
DSP1、DSP2；VPX P2 interfaces are mainly as the control command of master control interchanger plate, the data link interface of preliminary data, together
Handshake, data exchange interface between Shi Zuowei and backboard other boards, and be connected with I O board below, realization connects with outside
The data exchange of mouth；
One Ethernet PHY chip, with RJ45 network interface connections, outside sends signal to ethernet PHY by RJ45 network interfaces
Chip, Ethernet PHY chip is sent data by SGMII high-speed serial bus after physical layer completes protocol translation respectively
Signal operation processing is carried out to DSP1 and DSP2 chips；Meanwhile, DSP1 and DSP2 can be sent data to by the link
RJ45 network interfaces realize the communication with external equipment；
Two dsp chips, respectively DSP1 and DSP2；Two dsp chips receive the SRIO X4 of VPX interfaces transmission, gigabit with
Too two kinds of high-speed serial bus signals of net, and the PCIE X2 high speed serializations for repacking forwarding by PCIE exchange chips are total
Line signal, according to the instruction and data in the bus signals received, completes signal transacting work；Between two panels DSP, pass through
The channel pattern of Hyper-Link HSSI High-Speed Serial Interfaces 4 realizes the high-speed bus interconnection between dsp chip, accesses two panels DSP
Mutual memory space, realizes that data interaction cooperates；
Eight DDR3 storage chips are divided into two groups, and every group four, one group of DDR3 storage chip of a piece of dsp chip correspondence is used
High-capacity data access expanded function is realized when dsp chip does signal transacting computing；
Two panels FLASH storage chips, two panels FLASH storage chips are connected with FPGA SoC controllers respectively, every FLASH
Chip also corresponds to a piece of dsp chip of connection；FLASH storage chips effect one is independent as dsp chip or as FPGA
The external memory interface of the fpga chip of SoC controllers, i.e. EMIF interfaces, are controlled for dsp chip or as FPGA SoC
Data storage defencive function after the fpga chip power down of device processed；Two be as public memory space realize dsp chip and
Data interaction function between FPGA SoC controllers；
One PCIE exchange chips, are split with order for the data to the bus protocol using PCIE X4, are beaten again
Bao Hou, is changed into two-way PCIE X2 high-speed serial bus signals, and is separately sent to DSP1 and DSP2, to realize and dsp chip
Control and data exchange；
One FPGA SoC controllers, i.e. PFGA chips are used as on-chip system, abbreviation SoC；It is mainly used in completing plate level control
Management function, realizes the control, configuration, monitoring work to each chip in the DSP signal-processing boards, is inputted while completing part
The pretreatment work of signal.
What the goal of the invention of the present invention was realized in：
VPX Parallel DSP Signal transacting board analysis of the invention based on SoC on-line reorganizations, the level SoC controls using fpga chip as plate
Device processed, two panels dsp chip is its main operational chip of digital signal panel card.When actual disposition dsp chip, as
The FPGA of SoC controllers can utilize gigabit Ethernet completion work by carrying out hardware reset and start-up mode switching to DSP
The dynamic recognition of code, greatly improves the flexibility ratio and real-time during Digital Signal Processing.Dsp chip is passed by VPX interfaces
Defeated SRIO X4, two kinds of high-speed serial bus signals of gigabit Ethernet, and repack forwarding by PCIE exchange chips
PCIE X2 high-speed serial bus signals, the pending data-signal of reception and control instruction；Or receive outer by RJ45 network interfaces
Connect the gigabit Ethernet protocol signal of equipment.The controlling bus of this signal-processing board uses gigabit Ethernet bus protocol；Data
Bus can need selection SRIO buses or PCIE buses according to user, and wherein SRIO bus protocols are used for and Signal Pretreatment plate
Carry out data interaction；PCIE bus protocols are used to carry out data interaction with master control interchanger plate.Dsp chip completes the number to reception
According to progress signal transacting work, data interaction is realized using HYPZER-LINK high-speed serial bus between dsp chip.
Meanwhile, the VPX Parallel DSPs Signal transacting board analysis of the invention based on SoC on-line reorganizations also has the advantages that：
(1), the present invention proposes a kind of new based on " SoC+ two CSTRs " signal processing platform framework, and dsp chip is independently set
Signal transacting board analysis is calculated as and as core calculations unit, by calling soft core to control the SoC of fpga chip as whole board
Device processed, the totality that real time high-speed signal-processing board designs and gives the platform is realized using the framework of this " SoC+ two CSTRs "
Framework map, proposes specific embodiment；
(2), the two-way PCIE X2 signal links that two panels dsp chip is each provided are merged into by PCI-E exchange chips
PCIE X4 are connected that there is provided realize control signal/Broadband high-speed data communication link by backboard with master control borad all the way；
(3), the serial multi-core DSP chips of the TI company's Ts MS320C667x that DSP Signal transacting board analysis is used, which have, flexibly opens
Flowing mode is provided more there is provided the load mode of multiple channel for the online reconfiguration and Reconfigurable Computation of dsp chip
Possibility.Acquiescence loads the program being solidificated in NOR Flash using SPI mode when this board starts for the first time, in DSP signals
Handle on board during electricity operation, FPGA can be by carrying out hardware reset and start-up mode as SoC controllers to DSP
Switching, the dynamic recognition of operation code is completed using gigabit Ethernet, flexibility ratio when greatly improving Digital Signal Processing and
Real-time.
(4), DSP Signal transacting board analysis employs SRIO, PCIE, three kinds of high speed bus interfaces of gigabit Ethernet, is compared to
Traditional design is using a kind of bus as data link, and the design provides bigger data bandwidth and more preferable bus compatible.
Brief description of the drawings
Fig. 1 is the VPX Parallel DSP Signal transacting board analysis theory diagrams of the invention based on SoC on-line reorganizations；
Fig. 2 is VPX interface diagrams；
Fig. 3 is two panels TMS320C667x chip on-line reorganization structural representations；
Fig. 4 is Serial RapidIO HSSI High-Speed Serial Interface connection diagrams on two panels TMS320C667x chips；
Fig. 5 is GE HSSI High-Speed Serial Interface connection diagrams on two panels TMS320C667x chips
Fig. 6 is SGMII HSSI High-Speed Serial Interface connection diagrams on two panels TMS320C667x chips；
Fig. 7 is the PCIE HSSI High-Speed Serial Interface connection diagrams using PCIE exchange chips as nucleus module.
Embodiment
The embodiment to the present invention is described below in conjunction with the accompanying drawings, so as to those skilled in the art preferably
Understand the present invention.Requiring particular attention is that, in the following description, when known function and design detailed description perhaps
When can desalinate the main contents of the present invention, these descriptions will be ignored herein.
Embodiment
Describe, the relevant speciality term occurred in embodiment is illustrated for convenience first：
VPX：It is organized in by VITA (VME International Trade Association, VME international trade associations)
The high-speed serial bus standard of new generation proposed on its VME bus foundation for 2007；
VPX3U：3U in VPX3U is a kind of board dimensional standard specified in VPX agreements；
DSP(Digital Signal Processing)：Digital Signal Processing；
PHY(physical layer)：Physical layer；
DDR3(Double Data Rate 3)：Third generation Double Data Rate synchronous DRAM；
FLASH(Flash EEPROM Memory)：Non-volatile internal memory；
FPGA(Field Programmable Gate Array)：Field programmable gate array chip；
SOC(System on a Chip)：On-chip system；
PCIE(Peripheral Component Interface Express)：Ancillary equipment interconnection interface；
SRIO(Serial Rapid Input Output)：Serial high speed bus interface；
GE(Gigabit Ethernet)：Gigabit Ethernet；
SGMII(Serial Gigabit Media Independent Interface)：Serial gigabit media are independently total
Line interface；
Hyper-Link：A kind of high-speed serial communication interface proposed by TI companies；
JTAG(Joint Test Action Group)：Joint test working group；
EMIF(External Memory Interface)：External memory interface；
QSPI(quad serial peripheral interface)：Queuing type Serial Peripheral Interface；
AXI(Advanced extensible Interface)：The senior expansible bus protocol proposed by ARM companies；
I2C(InterIntegrated Circuit)：The twin wire universal serial bus developed by PHILIPS companies；
GPIO(General Purpose Input Output)：Universal input/output.
Fig. 1 is the VPX Parallel DSP Signal transacting board analysis theory diagrams of the invention based on SoC on-line reorganizations.
In the present embodiment, as shown in figure 1, a kind of VPX Parallel DSP signal transactings based on SoC on-line reorganizations of the present invention
Board, mainly includes：VPX interfaces 1, Ethernet PHY chip 2, two panels dsp chip 3, two groups of DDR3 storage chips 4, two panels
FLASH storage chips 5, PCIE exchange chips 6 and FPGA SoC controllers 7；
In the present embodiment, VPX interfaces 1 use SLT3-PAY-2F1F2U-14.2.1 standard interfaces；Ethernet PHY chip
2 BCM5482 produced using Broadcom companies；DSP storage chips 3 are using the production of Texas Instruments companies
TMS320C667x series multi-core DSP chips；The MT41J256M16 types DDR3 that DDR3 storage chips 4 are produced using Micron companies
Memory chip；The MT29F1G08ABBEAH4 type NAND FLASH chips that FLASH storage chips 5 are produced using Micron companies；
The PI7C9X2G308GP exchange chips that PCIE exchange chips 6 are produced using PERICOM companies；FPGA SoC control chips 7 are used
The Artix-7 family chips of Xilinx companies；
Wherein, as shown in Fig. 2 VPX interfaces 1 are used for again including VPX P0 interfaces, VPX P1 interfaces and VPX P2 interfaces
DSP Signal transacting board analysis and the connection of outside master control interchanger plate and FPGA Signal Pretreatment plates, and be DSP signal transactings
Board provides input power interface；
Wherein, as shown in Fig. 2 VPX P0 interfaces include input power interface and system signal interface；In the present embodiment,
Power interface provides power supply for other modules in processing support plate, and there is provided the input powers such as 5V, 12V；
As shown in Fig. 2 VPX P1 interfaces include datum plane interface, control plane interface, extension plane interface and user
Self defined interface；Wherein, datum plane interface provides two SRIO x4 high-speed serial bus interfaces, and DSP1, DSP2 are connected respectively
Two main computing master chips, and FPGA Signal Pretreatment plates, for the signal of outside FPGA Signal Pretreatments plate to be input to
DSP1、DSP2；Control plane interface provides two gigabit Ethernet EBIs, and two main computings of DSP1, DSP2 are connected respectively
Master chip, and master control interchanger plate, for master control interchanger plate to be transmitted to the control signal and configuration order of dsp chip 3
Dsp chip 3, wherein master control interchanger plate use gigabit Ethernet agreement；Dsp chip 3 is carried out by FPGA SoC controllers
Reset, switch the program loading mode of dsp chip 3 using FPGA SoC controllers 7 loads for gigabit Ethernet, gigabit Ethernet
Loaded again by the real-time program to dsp chip 3, realize that on-line reconfiguration is calculated；Extend plane interface and one PCIe x4 is provided
High-speed serial bus interface, PCIe x4 high-speed serial bus interfaces are connected to PCIE exchange chips 6, in by master control interchanger plate
The PCIE protocol signals of use are synchronized to PCIE exchange chips 6；The User Defined interface offer two of VPX P1 interfaces is asynchronous
Serial interface, two asynchronous serial port interfaces meet DSP1, DSP2 respectively, are used as main control switchboard and the debugging interface of dsp chip 3；
As shown in Fig. 2 VPX P2 interfaces are used as User Defined interface；VPX P2 interfaces provide 32 pairs of differential signal lines and connect
Mouth and 8 road single-ended signal line interfaces, in the present embodiment, only remain 28 pairs of differential signal line interfaces；Utilize differential signal line
Interface is connected to FPGA SoC controllers 7, and DSP1, DSP2 are connected to using single-ended signal line interface；VPX P2 interfaces are used as master
The control command of controlled switching system plate, the data link interface of preliminary data, while being used as the letter of shaking hands between backboard other boards
Number, data exchange interface, and be connected with I O board below, realize the data exchange with external interface；
In summary, VPX interfaces 1 are transmitted using two groups of gigabit Ethernets and SRIO X4 high-speed serial bus, in structure
On employ dual redundant design, and at least ensure the signal link normal work of one of dsp chip 3；
Ethernet PHY chip 2, with RJ45 network interface connections, outside is by two RJ45 network interfaces respectively by two groups of crossover network cables
In 4 pairs of differential lines signals be sent to Ethernet PHY chip 2, Ethernet PHY chip 2 passes through after physical layer completes protocol translation
SGMII high-speed serial bus is separately sent to DSP1 and DSP2 chips and carries out signal operation processing；Meanwhile, DSP1 and DSP2 can be with
The realization of RJ45 network interfaces and the communication of external equipment are sent data to by the link；
Two dsp chips 3, respectively DSP1 and DSP2；Two dsp chips 3 receive the SRIO X4 of the transmission of VPX interfaces 1, thousand
Two kinds of high-speed serial bus signals of mbit ethernet, and the PCIE X2 for repacking forwarding by PCIE exchange chips 6 go here and there at a high speed
Row bus signal, according to the instruction and data in the bus signals of reception, completes signal transacting work；Two panels dsp chip 3 it
Between, realize that the high-speed bus between dsp chip 3 is interconnected by the channel pattern of Hyper-Link HSSI High-Speed Serial Interfaces 4, make two panels DSP
Chip 3 can access mutual memory space, realize that data interaction cooperates；
In the present embodiment, two dsp chips 3 use the multi-core DSP chip series of TI companies, with two panels
Exemplified by TMS320C667x chips, by Hyper-Link HSSI High-Speed Serial Interfaces, (Hyper-Link supports 1 to lead between two chips
Road or 4 channel patterns, 12.5GBaud transmission rates are supported per passage) realize that the high-speed bus between piece is interconnected, two panels DSP passes through
Hyper-Link can access mutual memory space to realize data interaction.
Two panels TMS320C667x DSP JTAG emulation interfaces are connected to 14 core standard in the form of daisy chain
On JTAG connector bodies, to facilitate user to debug.
Eight DDR3 storage chips are divided into two groups, and every group four, a piece of dsp chip 3 corresponds to one group of DDR3 storage chip 4,
High-capacity data access expanded function is realized when doing signal transacting computing for dsp chip 3；
Two panels FLASH storage chips 5, two panels FLASH storage chips 5 are connected with FPGA SoC controllers 7 respectively, every
FLASH chip 5 also corresponds to a piece of dsp chip 3 of connection；The effect of FLASH storage chips 5 one is the external storage as dsp chip 3
Device interface, i.e. EMIF interfaces, for the data storage defencive function after the power down of dsp chip 3；Two be to realize the He of dsp chip 3
Data interaction function between FPGA SoC controllers 7；
PCIE exchange chips 6, after the data in PCIE protocol signals and order are split, repacked, become
For two-way PCIE X2 high-speed serial bus signals, and be separately sent to DSP1 and DSP2, with realize control with dsp chip 3 and
Data exchange；
FPGA SoC controllers 7, i.e. PFGA chips are used as on-chip system, abbreviation SoC；Fpga chip is managed as plate level SoC
Device module is managed, whole DSP Signal transacting board analysis is controlled, the power supply power consumption management of the whole board of completion, Clock management, plate
Level logic control and working state monitoring, realize chip controls, configuration, the monitoring work to each in the signal-processing board, together
When be responsible for the pretreatment work of input signal；
In the present embodiment, using Xilinx companies FPGA family chips as FPGA SoC controllers 7 control core
Piece.Fpga chip uses QSPI configuration mode, and after the completion of configuration, user calls FPGA by loading the soft cores of Micro Blaze
Internal logic resource, realizes that the electrifying timing sequence control to signal-processing board, clock produce control, related chip configuration work；Together
When, the fpga chip also is responsible for the work of the simple Signal Pretreatment in part, such as Digital Down Convert, phase compensation, data splicing,
Data cutout etc..
Wherein, Micro Blaze as a kind of Embedded Soft Core can be embedded in by what Xilinx companies optimized
The soft core of risc processor in FPGA, has the advantages that the speed of service is fast, taking resource, few, configurability is strong, is widely used in
The fields such as communication, military, high-end consumption market.User, should by calling Micro Blaze Embedded Soft Cores on fpga chip
Soft core calls logical resource in piece so as to realize corresponding control function, such as using AXI buses：I2C controls, SPI controls, GPIO
Control, interruption control etc..
In the present embodiment, when DSP Signal transacting board analysis is normally run, two groups of high speed data bus of identical function are extremely
Ensure one of which normal operation less, when one of which high speed data bus breaks down, FPGA SoC controllers can be with fast
Speed implements on-line reorganization configuration to dsp chip, shields the data link of error and switches to data available link, by anomaly link
Data be sent to data available link.
Fig. 3 is two panels TMS320C667x chip on-line reorganization structural representations；
In the present embodiment, FPGA Soc controllers are given in figure as the controller of the on-line reorganization of dsp chip
The internal structure schematic diagram of FPGA Soc controllers；Dsp chip uses software reconfiguration mode, i.e., controlled using described FPGA SoC
Device processed and main control switchboard cooperate, and pass through the online weight of the dynamic of the gigabit Ethernet bus completion code of control plane interface
Structure；Shown in DSP on-line reorganization interconnection structures schematic diagram 3, the idiographic flow of its on-line reorganization is：Main control switchboard card is by interrupting
Control to issue to FPGA SoC controllers and reconfigure order, FPGA SoC controllers carry out power on reset operation to dsp chip, together
When switching dsp chip from start-up mode to gigabit Ethernet loading mode；FPGA SoC controllers notify master by interrupting control
Control power board to prepare to carry out dsp chip on-line reorganization, main control switchboard loads dsp chip using gigabit Ethernet in new mesh
Code is marked, dsp chip completes on-line reorganization after running new object code.
Fig. 4 is Serial RapidIO HSSI High-Speed Serial Interface connection diagrams on two panels TMS320C667x chips.
In the present embodiment, respective 1 road X4Serial RapidIO (every passage branch on two panels TMS320C667x chips
Hold 5GBaud speed) high speed serial port connected by backboard with corresponding FPGA boards, two panels TMS320C667x chips profit
The high speed data transfer with other signal pre-processing modules on backboard can be realized with Serial RapidIO.Wherein, Serial
RapidIO HSSI High-Speed Serial Interface interconnection modes are as shown in Figure 4.
Fig. 5 is GE HSSI High-Speed Serial Interface connection diagrams on two panels TMS320C667x chips.
Respectively there are 1 road X1GE high speed serial ports (to support 1GBaud speed per passage on two panels TMS320C667x chips
Rate) as alternate channel, it is connected by backboard with master control borad feature board, realization instruction loading/high speed Point-to-Point Data communication/
DSP such as reconfigures at the function online.Wherein, GE HSSI High-Speed Serial Interfaces annexation is as shown in Figure 5.
Fig. 6 is SGMII HSSI High-Speed Serial Interface connection diagrams on two panels TMS320C667x chips.
Respectively there are 1 road SGMII high speed serial ports (to support 1GBaud speed per passage on two panels TMS320C667x chips
Rate) by Ethernet PHY chip and RJ45 network interface connections, realize external data and the function of instruction loading.Wherein, SGMII is high
Fast serial line interface annexation is as shown in Figure 6.
Fig. 7 is the PCIE HSSI High-Speed Serial Interfaces connection diagram in PI7C9X2G308GP.
Due to the demand of VPX interface standards, the two-way PCIE X2 signal links that two panels DSP is provided are merged into all the way
PCIE X4 are connected by backboard with master control borad, realize the functions such as control signal/high-speed data communication function, therefore, the present embodiment
Middle selection PI7C9X2G308GP chips realize above-mentioned functions.Wherein, PI7C9X2G308GP provides three PCIE ports and eight
The links of bar PCIE 2.0 are closed there is provided the downlink port of X4 uplink port and two X2, its specific connection
System is as shown in Figure 7.
Although illustrative embodiment of the invention is described above, in order to the technology of the art
Personnel understand the present invention, it should be apparent that the invention is not restricted to the scope of embodiment, to the common skill of the art
For art personnel, as long as various change is in the spirit and scope of the present invention that appended claim is limited and is determined, these
Change is it will be apparent that all utilize the innovation and creation of present inventive concept in the row of protection.
Claims (3)
1. a kind of VPX Parallel DSP Signal transacting board analysis based on SoC on-line reorganizations, it is characterised in that including：
One VPX interfaces, including VPX P0 interfaces, VPX P1 interfaces and VPX P2 interfaces, for DSP Signal transacting board analysis and outside
Master control interchanger plate and FPGA Signal Pretreatment plates connection, and provide input power interface for DSP Signal transacting board analysis；
Described VPX P0 interfaces include input power interface and system signal interface；
Described VPX P1 interfaces include datum plane interface, control plane interface, extension plane interface and User Defined and connect
Mouthful；Wherein, datum plane interface provides two SRIO x4 high-speed serial bus interfaces, and the main fortune of DSP1, DSP2 two is connected respectively
Calculate master chip, and connection FPGA Signal Pretreatment plates, for by the signal of outside FPGA Signal Pretreatments plate be input to DSP1,
DSP2；Control plane interface provides two gigabit Ethernet EBIs, and the main main cores of computing of DSP1, DSP2 two are connected respectively
Piece, and connection master control interchanger plate, for the control signal by master control interchanger plate to dsp chip and online reconfiguration order
It is transmitted to dsp chip；Extend plane interface and one PCIe x4 high-speed serial bus interface be provided, and be connected to PCIE exchange chips,
PCIE protocol signals for master control interchanger plate to be used are synchronized to PCIE exchange chips；User in VPX P1 interfaces makes by oneself
Adopted interface provides two asynchronous serial port interfaces, and DSP1, DSP2 are met respectively, main control switchboard and the debugging interface of dsp chip is used as；
Described VPX P2 interfaces are used as User Defined interface；VPX P2 interfaces provide 32 pairs of differential signal line interfaces and 8 tunnels
Single-ended signal line interface；Differential signal line interface is connected to FPGA Soc controllers, single-ended signal line interface be connected to DSP1,
DSP2；VPX P2 interfaces are mainly as the control command of master control interchanger plate, the data link interface of preliminary data, while conduct
With the handshake between backboard other boards, data exchange interface, and it is connected with I O board below, realizes the number with external interface
According to exchange；
One Ethernet PHY chip, with RJ45 network interface connections, outside sends signal to Ethernet PHY chip by RJ45 network interfaces,
Data are separately sent to DSP1 by Ethernet PHY chip after physical layer completes protocol translation by SGMII high-speed serial bus
Signal operation processing is carried out with DSP2 chips；Meanwhile, DSP1 and DSP2 can send data to RJ45 network interfaces by the link
Realize the communication with external equipment；
Two dsp chips, respectively DSP1 and DSP2；Two dsp chips receive the SRIO X4 of VPX interfaces transmission, gigabit Ethernet
Two kinds of high-speed serial bus signals, and the PCIE X2 high-speed serial bus for repacking forwarding by PCIE exchange chips are believed
Number, according to the instruction and data in the bus signals received, complete signal transacting work；Between two panels DSP, pass through
The channel pattern of Hyper-Link HSSI High-Speed Serial Interfaces 4 realizes the high-speed bus interconnection between dsp chip, accesses two panels DSP
Mutual memory space, realizes that data interaction cooperates；
Eight DDR3 storage chips are divided into two groups, every group four, one group of DDR3 storage chip of a piece of dsp chip correspondence, for DSP
Chip realizes high-capacity data access expanded function when doing signal transacting computing；
Two panels FLASH storage chips, two panels FLASH storage chips are connected with FPGA SoC controllers respectively, every FLASH chip
Also correspond to a piece of dsp chip of connection；FLASH storage chips effect one is independent as dsp chip or as FPGA SoC controls
The external memory interface of the fpga chip of device, i.e. EMIF interfaces, for dsp chip or are used as FPGA SoC controllers
Data storage defencive function after fpga chip power down；Two be to realize dsp chip and FPGA as public memory space
Data interaction function between SoC controllers；
One PCIE exchange chips, are split with order for the data to the bus protocol using PCIE X4, are repacked
Afterwards, it is changed into two-way PCIE X2 high-speed serial bus signals, and is separately sent to DSP1 and DSP2, realizes the control with dsp chip
System and data exchange；
One FPGA SoC controllers, i.e. PFGA chips are used as on-chip system, abbreviation SoC；It is mainly used in completing plate level control management
Function, realizes the control, configuration, monitoring work to each chip in the signal-processing board, while completing part input signal
Pretreatment work；
Wherein, described dsp chip uses software reconfiguration mode, that is, utilizes described FPGA SoC controllers and main control switchboard
Cooperate, pass through the dynamic on-line reorganization of the gigabit Ethernet bus completion code of control plane interface；
The idiographic flow of its on-line reorganization is：Main control switchboard card controls to issue to FPGA SoC controllers to reconfigure by interrupting
Order, FPGA SoC controllers carry out power on reset operation to dsp chip, while switching dsp chip from start-up mode to gigabit
Ethernet loading mode；FPGA SoC controllers notify main control switchboard preparation is carried out to dsp chip online by interrupting control
Reconstruct, main control switchboard loads new object code using gigabit Ethernet to dsp chip, and dsp chip runs new target generation
On-line reorganization is completed after code.
2. the VPX Parallel DSP Signal transacting board analysis according to claim 1 based on SoC on-line reorganizations, it is characterised in that
Described DSP Signal transacting board analysis uses the Signal transacting board analysis overall architecture of " SoC+ two CSTRs "；
Fpga chip is controlled to whole DSP Signal transacting board analysis as plate level SoC manager modules, completes whole board
Power supply power consumption management, Clock management, plate level logic control, working state monitoring；
Two panels dsp chip is respectively configured one group of DDR3 chip as real time data and accesses expanded function as its main operational module,
The FLASH chip that configuration is shared with FPGA SoC controllers stores peripheral hardware as EMIF, and there is provided data storage interactive function；DSP
Chip directly realizes data interaction with FPGA SoC controllers by EMIF interfaces；Main control switchboard card can utilize gigabit ether
Net reloads program online, neatly realizes that dsp chip on-line reorganization is calculated；Dsp chip is by respective algorithms to receiving number
Pass through SRIO, PCIE, GE high-speed serial bus and main control switchboard and other according to progress signal transacting, and using VPX connectors
Signal transacting board analysis realizes data interaction, or realizes data interaction using RJ45 network interfaces and external equipment.
3. the VPX Parallel DSP Signal transacting board analysis according to claim 1 based on SoC on-line reorganizations, it is characterised in that
Described VPX connectors are designed using dual redundant data bus interface, realize the Hot Spare of data；
In VPX Interface Controllers plane using two groups of gigabit Ethernets, VPX interface data plane is gone here and there at a high speed using two SRIO X4
Row bus are transmitted, and RJ45 interfaces provide two-way interface；
When DSP Signal transacting board analysis is normally run, two groups of high speed data bus of identical function at least ensure that one of which is transported
Row is normal, when one of which high speed data bus breaks down, and FPGA SoC controllers can be implemented rapidly to dsp chip
Line reconstruct configuration, shields the data link of error and switches to data available link, the data of anomaly link are sent to available
Data link.
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